- Decrease upscale glitches in dx10 (dx9 later) by hacking the UV coordinate system in borderline cases.
git-svn-id: http://pcsx2.googlecode.com/svn/trunk@2348 96395faa-99c1-11dd-bbfe-3dabce05a288
* Added feature to align call targets for EErec functions and blocks on P4's and AMDs, and pack them on Core2/i7's.
* Fixed some svn:native props.
git-svn-id: http://pcsx2.googlecode.com/svn/trunk@2347 96395faa-99c1-11dd-bbfe-3dabce05a288
* Configuration panels are all modal-less now, so that you can open the config panel and leave it open while running games.
* Handful of thread sync improvements.
* Fixed on-the-fly interpreter/recompiler configuration.
* Fixed plugin hotswapping (mostly works, but still a little funny at times)
* All new assertion dialogs and popup message handlers.
* RecentIsoList defaults to 12 instead of 6
Dev Notes:
* I had to create a new set of assertion functions called pxAssume*. Originally I hoped to avoid that complexity, and just use a single one-assert-fits-all case, but turned out blanketly using __assume() for all assertion cases wasn't reliable.
* wxGuiTools: Replaced the operator, with operator& -- the latter has proper order of precedence, the former required () to scope correctly. >_<
git-svn-id: http://pcsx2.googlecode.com/svn/trunk@2339 96395faa-99c1-11dd-bbfe-3dabce05a288
In theory this would be the correct thing to do, but with our current DMAC and event test system it just causes problems.
Note: This commit *could* break/improve/fix games, please test :p
git-svn-id: http://pcsx2.googlecode.com/svn/trunk@2333 96395faa-99c1-11dd-bbfe-3dabce05a288
This is part of PATH 3 masking mess, so it could fix other PATH 3 using games.
Added some debug lines as well, should there be problems.
git-svn-id: http://pcsx2.googlecode.com/svn/trunk@2331 96395faa-99c1-11dd-bbfe-3dabce05a288
* Removed some hacks from cpuDetectInit's use of cpuId.
* Improved assertion checking for thread affinity.
git-svn-id: http://pcsx2.googlecode.com/svn/trunk@2327 96395faa-99c1-11dd-bbfe-3dabce05a288
DevNote: Moved jNO_DEFAULT from the Pcsx2Defs.h, since it's too dependent on the Common libraries. It's now in Assertions.h. Plugins can use __assume(0); directly instead or roll their own.
git-svn-id: http://pcsx2.googlecode.com/svn/trunk@2326 96395faa-99c1-11dd-bbfe-3dabce05a288
* Better error handling for when sVU fails allocating memory at a specific location (should fail less).
* Partial support for detecting and handling non-SSE2 machines with some grace.
* Improved sVU's allocation chances with a second try at another randomish address (and removed alloc fail spam from the console -- only logs on complete fail now).
git-svn-id: http://pcsx2.googlecode.com/svn/trunk@2321 96395faa-99c1-11dd-bbfe-3dabce05a288
- Added microVU_Clamp.inl to the project file which holds all of mVU's clamping routines.
- Added tmmk's optimized clamping method for sse4 (preserve sign clamp mode only) <-- untested
- Not using regalloc for preserved-sign non-sse4 code anymore since it seems to be bugged (thanks to nneeve for pointing it out)
- Extra mode was using preserve-sign code before; but changed it now to never preserve nan sign...
- Fixed a bug in extra clamp modes where it was clamping all 4 vectors on SS SSE instructions, destroying upper 3 vectors...
After these changes the compatibility of extra / preserve sign clamp modes have gone up.
git-svn-id: http://pcsx2.googlecode.com/svn/trunk@2315 96395faa-99c1-11dd-bbfe-3dabce05a288
Note:
What extra clamp mode does is whenever an SSE ADD/SUB/MUL/DIV instruction is used in mVU, it will have its operands clamped.
Currently seems to cause sps in some games instead of fixing it...
There might be some reason for it that I'm not aware of yet, or it could be 'random' based on what a game is doing.
A quick explanation of what mVU's clamp modes do:
None - Does no clamping (fast)
Normal - Clamp certain instructions which have proven to fix games
Extra - Clamps every SSE instruction (slow)
Extra + Preserve Sign - Same as extra but preserves sign of the NaN (super slow)
git-svn-id: http://pcsx2.googlecode.com/svn/trunk@2313 96395faa-99c1-11dd-bbfe-3dabce05a288
- Let's use dx10 software rendering for the F9 renderer switch, if it's available.
git-svn-id: http://pcsx2.googlecode.com/svn/trunk@2307 96395faa-99c1-11dd-bbfe-3dabce05a288
I don't have DX10 so this is (as usual!) untested. I'll be adding support for it to PCSX2 soon.
git-svn-id: http://pcsx2.googlecode.com/svn/trunk@2301 96395faa-99c1-11dd-bbfe-3dabce05a288
ramapcsx2