mirror of https://github.com/PCSX2/pcsx2.git
microVU:
- Added microVU_Clamp.inl to the project file which holds all of mVU's clamping routines. - Added tmmk's optimized clamping method for sse4 (preserve sign clamp mode only) <-- untested - Not using regalloc for preserved-sign non-sse4 code anymore since it seems to be bugged (thanks to nneeve for pointing it out) - Extra mode was using preserve-sign code before; but changed it now to never preserve nan sign... - Fixed a bug in extra clamp modes where it was clamping all 4 vectors on SS SSE instructions, destroying upper 3 vectors... After these changes the compatibility of extra / preserve sign clamp modes have gone up. git-svn-id: http://pcsx2.googlecode.com/svn/trunk@2315 96395faa-99c1-11dd-bbfe-3dabce05a288
This commit is contained in:
cottonvibes
parent
e01cfedd2b
commit
316e7ffccc
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@ -651,6 +651,10 @@
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RelativePath="..\..\x86\microVU_Branch.inl"
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>
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</File>
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<File
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RelativePath="..\..\x86\microVU_Clamp.inl"
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>
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</File>
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<File
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RelativePath="..\..\x86\microVU_Compile.inl"
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>
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@ -144,6 +144,7 @@ struct microVU {
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__aligned16 u32 macFlag[4]; // 4 instances of mac flag (used in execution)
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__aligned16 u32 clipFlag[4]; // 4 instances of clip flag (used in execution)
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__aligned16 u32 xmmPQb[4]; // Backup for xmmPQ
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__aligned16 u32 xmmCTemp[4]; // Backup used in mVUclamp2()
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u32 index; // VU Index (VU0 or VU1)
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u32 cop2; // VU is in COP2 mode? (No/Yes)
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@ -208,6 +209,7 @@ typedef void (__fastcall *mVUrecCall)(u32, u32);
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// Include all the *.inl files (Needed because C++ sucks with templates and *.cpp files)
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#include "microVU_Clamp.inl"
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#include "microVU_Misc.inl"
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#include "microVU_Log.inl"
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#include "microVU_Analyze.inl"
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@ -0,0 +1,106 @@
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/* PCSX2 - PS2 Emulator for PCs
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* Copyright (C) 2002-2009 PCSX2 Dev Team
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*
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* PCSX2 is free software: you can redistribute it and/or modify it under the terms
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* of the GNU Lesser General Public License as published by the Free Software Found-
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* ation, either version 3 of the License, or (at your option) any later version.
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*
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* PCSX2 is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
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* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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* PURPOSE. See the GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along with PCSX2.
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* If not, see <http://www.gnu.org/licenses/>.
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*/
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#pragma once
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//------------------------------------------------------------------
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// Micro VU - Clamp Functions
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//------------------------------------------------------------------
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const __aligned16 u32 sse4_minvals[2][4] = {
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{ 0xff7fffff, 0xffffffff, 0xffffffff, 0xffffffff }, //1000
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{ 0xff7fffff, 0xff7fffff, 0xff7fffff, 0xff7fffff }, //1111
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};
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const __aligned16 u32 sse4_maxvals[2][4] = {
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{ 0x7f7fffff, 0x7fffffff, 0x7fffffff, 0x7fffffff }, //1000
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{ 0x7f7fffff, 0x7f7fffff, 0x7f7fffff, 0x7f7fffff }, //1111
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};
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// Used for Result Clamping
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// Note: This function will not preserve NaN values' sign.
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// The theory behind this is that when we compute a result, and we've
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// gotten a NaN value, then something went wrong; and the NaN's sign
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// is not to be trusted. Games like positive values better usually,
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// and its faster... so just always make NaNs into positive infinity.
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void mVUclamp1(int reg, int regT1, int xyzw, bool bClampE = 0) {
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if ((!clampE && CHECK_VU_OVERFLOW) || (clampE && bClampE)) {
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switch (xyzw) {
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case 1: case 2: case 4: case 8:
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SSE_MINSS_M32_to_XMM(reg, (uptr)mVUglob.maxvals);
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SSE_MAXSS_M32_to_XMM(reg, (uptr)mVUglob.minvals);
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break;
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default:
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SSE_MINPS_M128_to_XMM(reg, (uptr)mVUglob.maxvals);
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SSE_MAXPS_M128_to_XMM(reg, (uptr)mVUglob.minvals);
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break;
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}
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}
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}
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// Used for Operand Clamping
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// Note 1: If 'preserve sign' mode is on, it will preserve the sign of NaN values.
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// Note 2: Using regalloc here seems to contaminate some regs in certain games.
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// Must be some specific case I've overlooked (or I used regalloc improperly on an opcode)
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// so we just use a temporary mem location for our backup for now... (non-sse4 version only)
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void mVUclamp2(microVU* mVU, int reg, int regT1, int xyzw, bool bClampE = 0) {
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if ((!clampE && CHECK_VU_SIGN_OVERFLOW) || (clampE && bClampE && CHECK_VU_SIGN_OVERFLOW)) {
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if (x86caps.hasStreamingSIMD4Extensions) {
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int i = (xyzw==1||xyzw==2||xyzw==4||xyzw==8) ? 0: 0xf;
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SSE4_PMINSD_M128_to_XMM(reg, (uptr)&sse4_maxvals[i][0]);
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SSE4_PMINUD_M128_to_XMM(reg, (uptr)&sse4_minvals[i][0]);
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return;
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}
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int regT1b = 0;
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if (regT1 < 0) {
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regT1b = 1; regT1=(reg+1)%8;
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SSE_MOVAPS_XMM_to_M128((uptr)mVU->xmmCTemp, regT1);
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//regT1 = mVU->regAlloc->allocReg();
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}
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switch (xyzw) {
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case 1: case 2: case 4: case 8:
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SSE_MOVSS_XMM_to_XMM (regT1, reg);
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SSE_ANDPS_M128_to_XMM(regT1, (uptr)mVUglob.signbit);
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SSE_MINSS_M32_to_XMM (reg, (uptr)mVUglob.maxvals);
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SSE_MAXSS_M32_to_XMM (reg, (uptr)mVUglob.minvals);
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SSE_ORPS_XMM_to_XMM (reg, regT1);
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break;
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default:
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SSE_MOVAPS_XMM_to_XMM(regT1, reg);
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SSE_ANDPS_M128_to_XMM(regT1, (uptr)mVUglob.signbit);
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SSE_MINPS_M128_to_XMM(reg, (uptr)mVUglob.maxvals);
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SSE_MAXPS_M128_to_XMM(reg, (uptr)mVUglob.minvals);
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SSE_ORPS_XMM_to_XMM (reg, regT1);
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break;
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}
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//if (regT1b) mVU->regAlloc->clearNeeded(regT1);
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if (regT1b) SSE_MOVAPS_M128_to_XMM(regT1, (uptr)mVU->xmmCTemp);
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}
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else mVUclamp1(reg, regT1, xyzw, bClampE);
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}
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// Used for operand clamping on every SSE instruction (add/sub/mul/div)
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void mVUclamp3(microVU* mVU, int reg, int regT1, int xyzw) {
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if (clampE) mVUclamp2(mVU, reg, regT1, xyzw, 1);
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}
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// Used for result clamping on every SSE instruction (add/sub/mul/div)
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// Note: Disabled in "preserve sign" mode because in certain cases it
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// makes too much code-gen, and you get jump8-overflows in certain
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// emulated opcodes (causing crashes). Since we're clamping the operands
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// with mVUclamp3, we should almost never be getting a NaN result,
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// but this clamp is just a precaution just-in-case.
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void mVUclamp4(int reg, int regT1, int xyzw) {
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if (clampE && !CHECK_VU_SIGN_OVERFLOW) mVUclamp1(reg, regT1, xyzw, 1);
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}
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@ -15,60 +15,6 @@
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#pragma once
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//------------------------------------------------------------------
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// Micro VU - Clamp Functions
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//------------------------------------------------------------------
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// Used for Result Clamping
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void mVUclamp1(int reg, int regT1, int xyzw, bool bClampE = 0) {
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if ((!clampE && CHECK_VU_OVERFLOW) || (clampE && bClampE)) {
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switch (xyzw) {
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case 1: case 2: case 4: case 8:
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SSE_MINSS_M32_to_XMM(reg, (uptr)mVUglob.maxvals);
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SSE_MAXSS_M32_to_XMM(reg, (uptr)mVUglob.minvals);
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break;
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default:
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SSE_MINPS_M128_to_XMM(reg, (uptr)mVUglob.maxvals);
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SSE_MAXPS_M128_to_XMM(reg, (uptr)mVUglob.minvals);
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break;
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}
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}
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}
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// Used for Operand Clamping
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void mVUclamp2(microVU* mVU, int reg, int regT1, int xyzw, bool bClampE = 0) {
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if ((!clampE && CHECK_VU_SIGN_OVERFLOW) || (clampE && bClampE)) {
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int regT1b = 0;
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if (regT1 < 0) { regT1 = mVU->regAlloc->allocReg(); regT1b = 1; }
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switch (xyzw) {
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case 1: case 2: case 4: case 8:
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SSE_MOVSS_XMM_to_XMM (regT1, reg);
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SSE_ANDPS_M128_to_XMM(regT1, (uptr)mVUglob.signbit);
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SSE_MINSS_M32_to_XMM (reg, (uptr)mVUglob.maxvals);
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SSE_MAXSS_M32_to_XMM (reg, (uptr)mVUglob.minvals);
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SSE_ORPS_XMM_to_XMM (reg, regT1);
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break;
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default:
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SSE_MOVAPS_XMM_to_XMM(regT1, reg);
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SSE_ANDPS_M128_to_XMM(regT1, (uptr)mVUglob.signbit);
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SSE_MINPS_M128_to_XMM(reg, (uptr)mVUglob.maxvals);
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SSE_MAXPS_M128_to_XMM(reg, (uptr)mVUglob.minvals);
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SSE_ORPS_XMM_to_XMM (reg, regT1);
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break;
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}
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if (regT1b) mVU->regAlloc->clearNeeded(regT1);
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}
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else mVUclamp1(reg, regT1, xyzw, bClampE);
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}
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void mVUclamp3(microVU* mVU, int reg, int regT1, int xyzw) {
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if (clampE) mVUclamp2(mVU, reg, regT1, xyzw, 1);
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}
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void mVUclamp4(int reg, int regT1, int xyzw) {
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if (clampE) mVUclamp1(reg, regT1, xyzw, 1);
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}
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//------------------------------------------------------------------
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// Micro VU - Reg Loading/Saving/Shuffling/Unpacking/Merging...
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//------------------------------------------------------------------
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@ -455,11 +401,11 @@ void ADD_SS(microVU* mVU, int to, int from, int t1, int t2) {
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if (t2b) mVU->regAlloc->clearNeeded(t2);
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}
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#define clampOp(opX) { \
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mVUclamp3(mVU, to, t1, 0xf); \
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mVUclamp3(mVU, from, t1, 0xf); \
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opX(to, from); \
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mVUclamp4(to, t1, 0xf); \
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#define clampOp(opX, isPS) { \
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mVUclamp3(mVU, to, t1, (isPS)?0xf:0x8); \
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mVUclamp3(mVU, from, t1, (isPS)?0xf:0x8); \
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opX(to, from); \
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mVUclamp4(to, t1, (isPS)?0xf:0x8); \
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}
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void SSE_MAXPS(mV, int to, int from, int t1 = -1, int t2 = -1) {
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@ -479,36 +425,36 @@ void SSE_MINSS(mV, int to, int from, int t1 = -1, int t2 = -1) {
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else { MIN_MAX_SS(mVU, to, from, t1, 1); }
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}
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void SSE_ADD2SS(mV, int to, int from, int t1 = -1, int t2 = -1) {
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if (!CHECK_VUADDSUBHACK) { clampOp(SSE_ADDSS_XMM_to_XMM); }
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if (!CHECK_VUADDSUBHACK) { clampOp(SSE_ADDSS_XMM_to_XMM, 0); }
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else { ADD_SS(mVU, to, from, t1, t2); }
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}
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void SSE_ADD2PS(mV, int to, int from, int t1 = -1, int t2 = -1) {
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clampOp(SSE_ADDPS_XMM_to_XMM);
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clampOp(SSE_ADDPS_XMM_to_XMM, 1);
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}
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void SSE_ADDPS(mV, int to, int from, int t1 = -1, int t2 = -1) {
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clampOp(SSE_ADDPS_XMM_to_XMM);
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clampOp(SSE_ADDPS_XMM_to_XMM, 1);
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}
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void SSE_ADDSS(mV, int to, int from, int t1 = -1, int t2 = -1) {
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clampOp(SSE_ADDSS_XMM_to_XMM);
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clampOp(SSE_ADDSS_XMM_to_XMM, 0);
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}
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void SSE_SUBPS(mV, int to, int from, int t1 = -1, int t2 = -1) {
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clampOp(SSE_SUBPS_XMM_to_XMM);
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clampOp(SSE_SUBPS_XMM_to_XMM, 1);
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}
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void SSE_SUBSS(mV, int to, int from, int t1 = -1, int t2 = -1) {
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clampOp(SSE_SUBSS_XMM_to_XMM);
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clampOp(SSE_SUBSS_XMM_to_XMM, 0);
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}
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void SSE_MULPS(mV, int to, int from, int t1 = -1, int t2 = -1) {
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clampOp(SSE_MULPS_XMM_to_XMM);
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clampOp(SSE_MULPS_XMM_to_XMM, 1);
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}
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void SSE_MULSS(mV, int to, int from, int t1 = -1, int t2 = -1) {
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clampOp(SSE_MULSS_XMM_to_XMM);
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clampOp(SSE_MULSS_XMM_to_XMM, 0);
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}
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void SSE_DIVPS(mV, int to, int from, int t1 = -1, int t2 = -1) {
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clampOp(SSE_DIVPS_XMM_to_XMM);
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clampOp(SSE_DIVPS_XMM_to_XMM, 1);
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}
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void SSE_DIVSS(mV, int to, int from, int t1 = -1, int t2 = -1) {
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clampOp(SSE_DIVSS_XMM_to_XMM);
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clampOp(SSE_DIVSS_XMM_to_XMM, 0);
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}
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//------------------------------------------------------------------
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