2017-01-18 03:03:19 +00:00
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/*
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2019-01-22 14:58:29 +00:00
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Copyright 2016-2019 Arisotura
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2017-01-18 03:03:19 +00:00
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This file is part of melonDS.
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melonDS is free software: you can redistribute it and/or modify it under
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the terms of the GNU General Public License as published by the Free
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Software Foundation, either version 3 of the License, or (at your option)
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any later version.
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melonDS is distributed in the hope that it will be useful, but WITHOUT ANY
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WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
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You should have received a copy of the GNU General Public License along
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with melonDS. If not, see http://www.gnu.org/licenses/.
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*/
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#include <stdio.h>
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#include <string.h>
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#include "NDS.h"
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#include "GPU.h"
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2019-03-31 19:15:45 +00:00
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u64 vbltime;
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2017-01-18 03:03:19 +00:00
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namespace GPU
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{
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2017-01-31 02:54:51 +00:00
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#define LINE_CYCLES (355*6)
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2017-06-26 20:01:29 +00:00
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#define HBLANK_CYCLES (48+(256*6))
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2017-01-18 03:03:19 +00:00
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#define FRAME_CYCLES (LINE_CYCLES * 263)
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u16 VCount;
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2017-05-10 00:21:02 +00:00
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u32 NextVCount;
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u16 TotalScanlines;
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2017-01-18 03:03:19 +00:00
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2017-06-26 09:02:10 +00:00
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bool RunFIFO;
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2017-01-18 03:03:19 +00:00
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u16 DispStat[2], VMatch[2];
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u8 Palette[2*1024];
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u8 OAM[2*1024];
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u8 VRAM_A[128*1024];
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u8 VRAM_B[128*1024];
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u8 VRAM_C[128*1024];
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u8 VRAM_D[128*1024];
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u8 VRAM_E[ 64*1024];
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u8 VRAM_F[ 16*1024];
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u8 VRAM_G[ 16*1024];
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u8 VRAM_H[ 32*1024];
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u8 VRAM_I[ 16*1024];
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u8* VRAM[9] = {VRAM_A, VRAM_B, VRAM_C, VRAM_D, VRAM_E, VRAM_F, VRAM_G, VRAM_H, VRAM_I};
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u8 VRAMCNT[9];
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u8 VRAMSTAT;
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2017-02-27 20:26:11 +00:00
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u32 VRAMMap_LCDC;
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u32 VRAMMap_ABG[0x20];
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u32 VRAMMap_AOBJ[0x10];
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u32 VRAMMap_BBG[0x8];
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u32 VRAMMap_BOBJ[0x8];
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u32 VRAMMap_ABGExtPal[4];
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u32 VRAMMap_AOBJExtPal;
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u32 VRAMMap_BBGExtPal[4];
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u32 VRAMMap_BOBJExtPal;
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u32 VRAMMap_Texture[4];
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2017-03-24 19:53:01 +00:00
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u32 VRAMMap_TexPal[8];
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2017-02-27 20:26:11 +00:00
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u32 VRAMMap_ARM7[2];
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2019-05-12 13:01:40 +00:00
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int FrontBuffer;
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u32* Framebuffer[2][2];
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2019-05-16 14:27:45 +00:00
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bool Accelerated;
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2017-01-18 03:03:19 +00:00
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GPU2D* GPU2D_A;
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GPU2D* GPU2D_B;
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2017-02-07 21:23:46 +00:00
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bool Init()
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2017-01-18 03:03:19 +00:00
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{
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GPU2D_A = new GPU2D(0);
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GPU2D_B = new GPU2D(1);
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2017-02-07 21:23:46 +00:00
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if (!GPU3D::Init()) return false;
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2019-05-12 13:01:40 +00:00
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FrontBuffer = 0;
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Framebuffer[0][0] = NULL; Framebuffer[0][1] = NULL;
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Framebuffer[1][0] = NULL; Framebuffer[1][1] = NULL;
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2019-05-21 20:28:46 +00:00
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Accelerated = false;
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SetDisplaySettings(false);
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2019-05-03 17:28:15 +00:00
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2017-02-07 21:23:46 +00:00
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return true;
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}
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void DeInit()
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{
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delete GPU2D_A;
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delete GPU2D_B;
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GPU3D::DeInit();
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2019-05-03 17:28:15 +00:00
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2019-05-12 13:01:40 +00:00
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if (Framebuffer[0][0]) delete[] Framebuffer[0][0];
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if (Framebuffer[0][1]) delete[] Framebuffer[0][1];
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if (Framebuffer[1][0]) delete[] Framebuffer[1][0];
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if (Framebuffer[1][1]) delete[] Framebuffer[1][1];
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2017-01-18 03:03:19 +00:00
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}
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void Reset()
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{
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VCount = 0;
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2017-05-10 00:21:02 +00:00
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NextVCount = -1;
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TotalScanlines = 0;
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2017-01-18 03:03:19 +00:00
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DispStat[0] = 0;
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DispStat[1] = 0;
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VMatch[0] = 0;
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VMatch[1] = 0;
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memset(Palette, 0, 2*1024);
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memset(OAM, 0, 2*1024);
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memset(VRAM_A, 0, 128*1024);
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memset(VRAM_B, 0, 128*1024);
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memset(VRAM_C, 0, 128*1024);
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memset(VRAM_D, 0, 128*1024);
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memset(VRAM_E, 0, 64*1024);
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memset(VRAM_F, 0, 16*1024);
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memset(VRAM_G, 0, 16*1024);
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memset(VRAM_H, 0, 32*1024);
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memset(VRAM_I, 0, 16*1024);
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memset(VRAMCNT, 0, 9);
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VRAMSTAT = 0;
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2017-02-27 20:26:11 +00:00
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VRAMMap_LCDC = 0;
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memset(VRAMMap_ABG, 0, sizeof(VRAMMap_ABG));
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memset(VRAMMap_AOBJ, 0, sizeof(VRAMMap_AOBJ));
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memset(VRAMMap_BBG, 0, sizeof(VRAMMap_BBG));
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memset(VRAMMap_BOBJ, 0, sizeof(VRAMMap_BOBJ));
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memset(VRAMMap_ABGExtPal, 0, sizeof(VRAMMap_ABGExtPal));
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VRAMMap_AOBJExtPal = 0;
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memset(VRAMMap_BBGExtPal, 0, sizeof(VRAMMap_BBGExtPal));
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VRAMMap_BOBJExtPal = 0;
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memset(VRAMMap_Texture, 0, sizeof(VRAMMap_Texture));
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memset(VRAMMap_TexPal, 0, sizeof(VRAMMap_TexPal));
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VRAMMap_ARM7[0] = 0;
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VRAMMap_ARM7[1] = 0;
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2019-05-19 17:47:23 +00:00
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for (int i = 0; i < (256*192); i++)
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2017-01-18 03:03:19 +00:00
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{
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2019-05-12 13:01:40 +00:00
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Framebuffer[0][0][i] = 0xFFFFFFFF;
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Framebuffer[1][0][i] = 0xFFFFFFFF;
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}
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2019-05-19 17:47:23 +00:00
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for (int i = 0; i < (256*192); i++)
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2019-05-12 13:01:40 +00:00
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{
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Framebuffer[0][1][i] = 0xFFFFFFFF;
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Framebuffer[1][1][i] = 0xFFFFFFFF;
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2017-01-18 03:03:19 +00:00
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}
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GPU2D_A->Reset();
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GPU2D_B->Reset();
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2017-02-07 21:23:46 +00:00
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GPU3D::Reset();
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2017-01-18 03:03:19 +00:00
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2019-05-12 13:01:40 +00:00
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int backbuf = FrontBuffer ? 0 : 1;
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GPU2D_A->SetFramebuffer(Framebuffer[backbuf][1]);
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GPU2D_B->SetFramebuffer(Framebuffer[backbuf][0]);
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2017-01-18 03:03:19 +00:00
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}
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2017-09-21 02:08:03 +00:00
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void Stop()
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{
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2019-05-19 17:47:23 +00:00
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memset(Framebuffer[0][0], 0, 256*192);
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memset(Framebuffer[0][1], 0, 256*192);
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memset(Framebuffer[1][0], 0, 256*192);
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memset(Framebuffer[1][1], 0, 256*192);
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2017-09-21 02:08:03 +00:00
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}
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2018-10-17 23:38:33 +00:00
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void DoSavestate(Savestate* file)
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{
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2018-10-18 00:31:01 +00:00
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file->Section("GPUG");
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file->Var16(&VCount);
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file->Var32(&NextVCount);
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file->Var16(&TotalScanlines);
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file->Var16(&DispStat[0]);
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file->Var16(&DispStat[1]);
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file->Var16(&VMatch[0]);
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file->Var16(&VMatch[1]);
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file->VarArray(Palette, 2*1024);
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file->VarArray(OAM, 2*1024);
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file->VarArray(VRAM_A, 128*1024);
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file->VarArray(VRAM_B, 128*1024);
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file->VarArray(VRAM_C, 128*1024);
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file->VarArray(VRAM_D, 128*1024);
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file->VarArray(VRAM_E, 64*1024);
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file->VarArray(VRAM_F, 16*1024);
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file->VarArray(VRAM_G, 16*1024);
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file->VarArray(VRAM_H, 32*1024);
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file->VarArray(VRAM_I, 16*1024);
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file->VarArray(VRAMCNT, 9);
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file->Var8(&VRAMSTAT);
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file->Var32(&VRAMMap_LCDC);
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file->VarArray(VRAMMap_ABG, sizeof(VRAMMap_ABG));
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file->VarArray(VRAMMap_AOBJ, sizeof(VRAMMap_AOBJ));
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file->VarArray(VRAMMap_BBG, sizeof(VRAMMap_BBG));
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file->VarArray(VRAMMap_BOBJ, sizeof(VRAMMap_BOBJ));
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file->VarArray(VRAMMap_ABGExtPal, sizeof(VRAMMap_ABGExtPal));
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file->Var32(&VRAMMap_AOBJExtPal);
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file->VarArray(VRAMMap_BBGExtPal, sizeof(VRAMMap_BBGExtPal));
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file->Var32(&VRAMMap_BOBJExtPal);
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file->VarArray(VRAMMap_Texture, sizeof(VRAMMap_Texture));
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file->VarArray(VRAMMap_TexPal, sizeof(VRAMMap_TexPal));
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file->Var32(&VRAMMap_ARM7[0]);
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file->Var32(&VRAMMap_ARM7[1]);
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GPU2D_A->DoSavestate(file);
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GPU2D_B->DoSavestate(file);
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GPU3D::DoSavestate(file);
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2018-10-17 23:38:33 +00:00
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}
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2019-05-12 13:01:40 +00:00
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void AssignFramebuffers()
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{
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int backbuf = FrontBuffer ? 0 : 1;
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if (NDS::PowerControl9 & (1<<15))
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{
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GPU2D_A->SetFramebuffer(Framebuffer[backbuf][0]);
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GPU2D_B->SetFramebuffer(Framebuffer[backbuf][1]);
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}
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else
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{
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GPU2D_A->SetFramebuffer(Framebuffer[backbuf][1]);
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GPU2D_B->SetFramebuffer(Framebuffer[backbuf][0]);
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}
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}
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2019-05-21 20:28:46 +00:00
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void SetDisplaySettings(bool accel)
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{
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2019-05-19 17:47:23 +00:00
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if (accel != Accelerated)
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2019-05-12 13:01:40 +00:00
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{
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2019-05-16 14:27:45 +00:00
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int fbsize;
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2019-05-17 23:42:50 +00:00
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if (accel) fbsize = (256*3 + 2) * 192;
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2019-05-19 17:47:23 +00:00
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else fbsize = 256 * 192;
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2019-05-12 13:01:40 +00:00
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if (Framebuffer[0][0]) delete[] Framebuffer[0][0];
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if (Framebuffer[1][0]) delete[] Framebuffer[1][0];
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2019-05-19 17:47:23 +00:00
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if (Framebuffer[0][1]) delete[] Framebuffer[0][1];
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if (Framebuffer[1][1]) delete[] Framebuffer[1][1];
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2019-05-12 13:01:40 +00:00
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Framebuffer[0][0] = new u32[fbsize];
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Framebuffer[1][0] = new u32[fbsize];
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2019-05-19 17:47:23 +00:00
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Framebuffer[0][1] = new u32[fbsize];
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Framebuffer[1][1] = new u32[fbsize];
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2019-05-12 14:32:53 +00:00
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2019-05-12 14:47:34 +00:00
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memset(Framebuffer[0][0], 0, fbsize*4);
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memset(Framebuffer[1][0], 0, fbsize*4);
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2019-05-19 17:47:23 +00:00
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memset(Framebuffer[0][1], 0, fbsize*4);
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memset(Framebuffer[1][1], 0, fbsize*4);
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AssignFramebuffers();
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}
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2019-05-21 20:28:46 +00:00
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GPU2D_A->SetDisplaySettings(accel);
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GPU2D_B->SetDisplaySettings(accel);
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2019-05-16 14:27:45 +00:00
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Accelerated = accel;
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2019-05-03 17:28:15 +00:00
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}
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2017-01-18 03:03:19 +00:00
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2017-01-30 17:36:11 +00:00
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// VRAM mapping notes
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//
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// mirroring:
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// unmapped range reads zero
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// LCD is mirrored every 0x100000 bytes, the gap between each mirror reads zero
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// ABG:
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// bank A,B,C,D,E mirror every 0x80000 bytes
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// bank F,G mirror at base+0x8000, mirror every 0x80000 bytes
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// AOBJ:
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// bank A,B,E mirror every 0x40000 bytes
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// bank F,G mirror at base+0x8000, mirror every 0x40000 bytes
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// BBG:
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// bank C mirrors every 0x20000 bytes
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// bank H mirrors every 0x10000 bytes
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// bank I mirrors at base+0x4000, mirrors every 0x10000 bytes
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// BOBJ:
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// bank D mirrors every 0x20000 bytes
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// bank I mirrors every 0x4000 bytes
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//
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// untested:
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// ARM7 (TODO)
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// extended palette (mirroring doesn't apply)
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// texture/texpal (does mirroring apply?)
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2017-02-07 21:23:46 +00:00
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// -> trying to use extpal/texture/texpal with no VRAM mapped.
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// would likely read all black, but has to be tested.
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2017-01-30 17:36:11 +00:00
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//
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// overlap:
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// when reading: values are read from each bank and ORed together
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// when writing: value is written to each bank
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2017-01-18 03:03:19 +00:00
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2017-02-27 20:26:11 +00:00
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#define MAP_RANGE(map, base, n) for (int i = 0; i < n; i++) map[(base)+i] |= bankmask;
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#define UNMAP_RANGE(map, base, n) for (int i = 0; i < n; i++) map[(base)+i] &= ~bankmask;
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|
2017-01-18 03:03:19 +00:00
|
|
|
void MapVRAM_AB(u32 bank, u8 cnt)
|
|
|
|
{
|
|
|
|
u8 oldcnt = VRAMCNT[bank];
|
|
|
|
VRAMCNT[bank] = cnt;
|
|
|
|
|
|
|
|
if (oldcnt == cnt) return;
|
|
|
|
|
|
|
|
u8 oldofs = (oldcnt >> 3) & 0x3;
|
|
|
|
u8 ofs = (cnt >> 3) & 0x3;
|
2017-02-27 20:26:11 +00:00
|
|
|
u32 bankmask = 1 << bank;
|
2017-01-18 03:03:19 +00:00
|
|
|
|
|
|
|
if (oldcnt & (1<<7))
|
|
|
|
{
|
|
|
|
switch (oldcnt & 0x3)
|
|
|
|
{
|
2017-02-27 20:26:11 +00:00
|
|
|
case 0: // LCDC
|
|
|
|
VRAMMap_LCDC &= ~bankmask;
|
2017-01-18 03:03:19 +00:00
|
|
|
break;
|
|
|
|
|
2017-02-27 20:26:11 +00:00
|
|
|
case 1: // ABG
|
|
|
|
UNMAP_RANGE(VRAMMap_ABG, oldofs<<3, 8);
|
2017-01-18 03:03:19 +00:00
|
|
|
break;
|
|
|
|
|
2017-02-27 20:26:11 +00:00
|
|
|
case 2: // AOBJ
|
2017-01-18 03:03:19 +00:00
|
|
|
oldofs &= 0x1;
|
2017-02-27 20:26:11 +00:00
|
|
|
UNMAP_RANGE(VRAMMap_AOBJ, oldofs<<3, 8);
|
2017-01-18 03:03:19 +00:00
|
|
|
break;
|
|
|
|
|
2017-02-27 20:26:11 +00:00
|
|
|
case 3: // texture
|
|
|
|
VRAMMap_Texture[oldofs] &= ~bankmask;
|
2017-01-18 03:03:19 +00:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (cnt & (1<<7))
|
|
|
|
{
|
|
|
|
switch (cnt & 0x3)
|
|
|
|
{
|
2017-02-27 20:26:11 +00:00
|
|
|
case 0: // LCDC
|
|
|
|
VRAMMap_LCDC |= bankmask;
|
2017-01-18 03:03:19 +00:00
|
|
|
break;
|
|
|
|
|
2017-02-27 20:26:11 +00:00
|
|
|
case 1: // ABG
|
|
|
|
MAP_RANGE(VRAMMap_ABG, ofs<<3, 8);
|
2017-01-18 03:03:19 +00:00
|
|
|
break;
|
|
|
|
|
2017-02-27 20:26:11 +00:00
|
|
|
case 2: // AOBJ
|
2017-01-18 03:03:19 +00:00
|
|
|
ofs &= 0x1;
|
2017-02-27 20:26:11 +00:00
|
|
|
MAP_RANGE(VRAMMap_AOBJ, ofs<<3, 8);
|
2017-01-18 03:03:19 +00:00
|
|
|
break;
|
|
|
|
|
2017-02-27 20:26:11 +00:00
|
|
|
case 3: // texture
|
|
|
|
VRAMMap_Texture[ofs] |= bankmask;
|
2017-01-18 03:03:19 +00:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void MapVRAM_CD(u32 bank, u8 cnt)
|
|
|
|
{
|
|
|
|
u8 oldcnt = VRAMCNT[bank];
|
|
|
|
VRAMCNT[bank] = cnt;
|
|
|
|
|
|
|
|
VRAMSTAT &= ~(1 << (bank-2));
|
|
|
|
|
|
|
|
if (oldcnt == cnt) return;
|
|
|
|
|
|
|
|
u8 oldofs = (oldcnt >> 3) & 0x7;
|
|
|
|
u8 ofs = (cnt >> 3) & 0x7;
|
2017-02-27 20:26:11 +00:00
|
|
|
u32 bankmask = 1 << bank;
|
2017-01-18 03:03:19 +00:00
|
|
|
|
|
|
|
if (oldcnt & (1<<7))
|
|
|
|
{
|
|
|
|
switch (oldcnt & 0x7)
|
|
|
|
{
|
2017-02-27 20:26:11 +00:00
|
|
|
case 0: // LCDC
|
|
|
|
VRAMMap_LCDC &= ~bankmask;
|
2017-01-18 03:03:19 +00:00
|
|
|
break;
|
|
|
|
|
2017-02-27 20:26:11 +00:00
|
|
|
case 1: // ABG
|
|
|
|
UNMAP_RANGE(VRAMMap_ABG, oldofs<<3, 8);
|
2017-01-18 03:03:19 +00:00
|
|
|
break;
|
|
|
|
|
2017-02-27 20:26:11 +00:00
|
|
|
case 2: // ARM7 VRAM
|
2017-01-18 03:03:19 +00:00
|
|
|
oldofs &= 0x1;
|
2017-02-27 20:26:11 +00:00
|
|
|
VRAMMap_ARM7[oldofs] &= ~bankmask;
|
2017-01-18 03:03:19 +00:00
|
|
|
break;
|
|
|
|
|
2017-02-27 20:26:11 +00:00
|
|
|
case 3: // texture
|
|
|
|
VRAMMap_Texture[oldofs] &= ~bankmask;
|
2017-01-18 03:03:19 +00:00
|
|
|
break;
|
|
|
|
|
2017-02-27 20:26:11 +00:00
|
|
|
case 4: // BBG/BOBJ
|
2017-01-18 03:03:19 +00:00
|
|
|
if (bank == 2)
|
2017-02-27 20:26:11 +00:00
|
|
|
{
|
|
|
|
UNMAP_RANGE(VRAMMap_BBG, 0, 8);
|
|
|
|
}
|
2017-01-18 03:03:19 +00:00
|
|
|
else
|
2017-02-27 20:26:11 +00:00
|
|
|
{
|
|
|
|
UNMAP_RANGE(VRAMMap_BOBJ, 0, 8);
|
|
|
|
}
|
2017-01-18 03:03:19 +00:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (cnt & (1<<7))
|
|
|
|
{
|
|
|
|
switch (cnt & 0x7)
|
|
|
|
{
|
2017-02-27 20:26:11 +00:00
|
|
|
case 0: // LCDC
|
|
|
|
VRAMMap_LCDC |= bankmask;
|
2017-01-18 03:03:19 +00:00
|
|
|
break;
|
|
|
|
|
2017-02-27 20:26:11 +00:00
|
|
|
case 1: // ABG
|
|
|
|
MAP_RANGE(VRAMMap_ABG, ofs<<3, 8);
|
2017-01-18 03:03:19 +00:00
|
|
|
break;
|
|
|
|
|
2017-02-27 20:26:11 +00:00
|
|
|
case 2: // ARM7 VRAM
|
2017-01-18 03:03:19 +00:00
|
|
|
ofs &= 0x1;
|
2017-02-27 20:26:11 +00:00
|
|
|
VRAMMap_ARM7[ofs] |= bankmask;
|
2017-01-18 03:03:19 +00:00
|
|
|
VRAMSTAT |= (1 << (bank-2));
|
|
|
|
break;
|
|
|
|
|
2017-02-27 20:26:11 +00:00
|
|
|
case 3: // texture
|
|
|
|
VRAMMap_Texture[ofs] |= bankmask;
|
2017-01-18 03:03:19 +00:00
|
|
|
break;
|
|
|
|
|
2017-02-27 20:26:11 +00:00
|
|
|
case 4: // BBG/BOBJ
|
2017-01-18 03:03:19 +00:00
|
|
|
if (bank == 2)
|
2017-02-27 20:26:11 +00:00
|
|
|
{
|
|
|
|
MAP_RANGE(VRAMMap_BBG, 0, 8);
|
|
|
|
}
|
2017-01-18 03:03:19 +00:00
|
|
|
else
|
2017-02-27 20:26:11 +00:00
|
|
|
{
|
|
|
|
MAP_RANGE(VRAMMap_BOBJ, 0, 8);
|
|
|
|
}
|
2017-01-18 03:03:19 +00:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void MapVRAM_E(u32 bank, u8 cnt)
|
|
|
|
{
|
|
|
|
u8 oldcnt = VRAMCNT[bank];
|
|
|
|
VRAMCNT[bank] = cnt;
|
|
|
|
|
|
|
|
if (oldcnt == cnt) return;
|
|
|
|
|
2017-02-27 20:26:11 +00:00
|
|
|
u32 bankmask = 1 << bank;
|
2017-01-18 03:03:19 +00:00
|
|
|
|
|
|
|
if (oldcnt & (1<<7))
|
|
|
|
{
|
|
|
|
switch (oldcnt & 0x7)
|
|
|
|
{
|
2017-02-27 20:26:11 +00:00
|
|
|
case 0: // LCDC
|
|
|
|
VRAMMap_LCDC &= ~bankmask;
|
2017-01-18 03:03:19 +00:00
|
|
|
break;
|
|
|
|
|
2017-02-27 20:26:11 +00:00
|
|
|
case 1: // ABG
|
|
|
|
UNMAP_RANGE(VRAMMap_ABG, 0, 4);
|
2017-01-18 03:03:19 +00:00
|
|
|
break;
|
|
|
|
|
2017-02-27 20:26:11 +00:00
|
|
|
case 2: // AOBJ
|
|
|
|
UNMAP_RANGE(VRAMMap_AOBJ, 0, 4);
|
2017-01-18 03:03:19 +00:00
|
|
|
break;
|
|
|
|
|
2017-02-27 20:26:11 +00:00
|
|
|
case 3: // texture palette
|
|
|
|
UNMAP_RANGE(VRAMMap_TexPal, 0, 4);
|
2017-01-18 03:03:19 +00:00
|
|
|
break;
|
|
|
|
|
2017-02-27 20:26:11 +00:00
|
|
|
case 4: // ABG ext palette
|
|
|
|
UNMAP_RANGE(VRAMMap_ABGExtPal, 0, 4);
|
|
|
|
GPU2D_A->BGExtPalDirty(0);
|
|
|
|
GPU2D_A->BGExtPalDirty(2);
|
2017-01-18 03:03:19 +00:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (cnt & (1<<7))
|
|
|
|
{
|
|
|
|
switch (cnt & 0x7)
|
|
|
|
{
|
2017-02-27 20:26:11 +00:00
|
|
|
case 0: // LCDC
|
|
|
|
VRAMMap_LCDC |= bankmask;
|
2017-01-18 03:03:19 +00:00
|
|
|
break;
|
|
|
|
|
2017-02-27 20:26:11 +00:00
|
|
|
case 1: // ABG
|
|
|
|
MAP_RANGE(VRAMMap_ABG, 0, 4);
|
2017-01-18 03:03:19 +00:00
|
|
|
break;
|
|
|
|
|
2017-02-27 20:26:11 +00:00
|
|
|
case 2: // AOBJ
|
|
|
|
MAP_RANGE(VRAMMap_AOBJ, 0, 4);
|
2017-01-18 03:03:19 +00:00
|
|
|
break;
|
|
|
|
|
2017-02-27 20:26:11 +00:00
|
|
|
case 3: // texture palette
|
|
|
|
MAP_RANGE(VRAMMap_TexPal, 0, 4);
|
2017-01-18 03:03:19 +00:00
|
|
|
break;
|
|
|
|
|
2017-02-27 20:26:11 +00:00
|
|
|
case 4: // ABG ext palette
|
|
|
|
MAP_RANGE(VRAMMap_ABGExtPal, 0, 4);
|
|
|
|
GPU2D_A->BGExtPalDirty(0);
|
|
|
|
GPU2D_A->BGExtPalDirty(2);
|
2017-01-18 03:03:19 +00:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void MapVRAM_FG(u32 bank, u8 cnt)
|
|
|
|
{
|
|
|
|
u8 oldcnt = VRAMCNT[bank];
|
|
|
|
VRAMCNT[bank] = cnt;
|
|
|
|
|
|
|
|
if (oldcnt == cnt) return;
|
|
|
|
|
|
|
|
u8 oldofs = (oldcnt >> 3) & 0x7;
|
|
|
|
u8 ofs = (cnt >> 3) & 0x7;
|
2017-02-27 20:26:11 +00:00
|
|
|
u32 bankmask = 1 << bank;
|
2017-01-18 03:03:19 +00:00
|
|
|
|
|
|
|
if (oldcnt & (1<<7))
|
|
|
|
{
|
|
|
|
switch (oldcnt & 0x7)
|
|
|
|
{
|
2017-02-27 20:26:11 +00:00
|
|
|
case 0: // LCDC
|
|
|
|
VRAMMap_LCDC &= ~bankmask;
|
2017-01-18 03:03:19 +00:00
|
|
|
break;
|
|
|
|
|
2017-02-27 20:26:11 +00:00
|
|
|
case 1: // ABG
|
|
|
|
VRAMMap_ABG[(oldofs & 0x1) + ((oldofs & 0x2) << 1)] &= ~bankmask;
|
|
|
|
VRAMMap_ABG[(oldofs & 0x1) + ((oldofs & 0x2) << 1) + 2] &= ~bankmask;
|
2017-01-18 03:03:19 +00:00
|
|
|
break;
|
|
|
|
|
2017-02-27 20:26:11 +00:00
|
|
|
case 2: // AOBJ
|
|
|
|
VRAMMap_AOBJ[(oldofs & 0x1) + ((oldofs & 0x2) << 1)] &= ~bankmask;
|
|
|
|
VRAMMap_AOBJ[(oldofs & 0x1) + ((oldofs & 0x2) << 1) + 2] &= ~bankmask;
|
2017-01-18 03:03:19 +00:00
|
|
|
break;
|
|
|
|
|
2017-02-27 20:26:11 +00:00
|
|
|
case 3: // texture palette
|
|
|
|
VRAMMap_TexPal[(oldofs & 0x1) + ((oldofs & 0x2) << 1)] &= ~bankmask;
|
2017-01-18 03:03:19 +00:00
|
|
|
break;
|
|
|
|
|
2017-02-27 20:26:11 +00:00
|
|
|
case 4: // ABG ext palette
|
|
|
|
VRAMMap_ABGExtPal[((oldofs & 0x1) << 1)] &= ~bankmask;
|
|
|
|
VRAMMap_ABGExtPal[((oldofs & 0x1) << 1) + 1] &= ~bankmask;
|
2017-03-24 19:53:01 +00:00
|
|
|
GPU2D_A->BGExtPalDirty((oldofs & 0x1) << 1);
|
2017-01-18 03:03:19 +00:00
|
|
|
break;
|
|
|
|
|
2017-02-27 20:26:11 +00:00
|
|
|
case 5: // AOBJ ext palette
|
|
|
|
VRAMMap_AOBJExtPal &= ~bankmask;
|
|
|
|
GPU2D_A->OBJExtPalDirty();
|
2017-01-18 03:03:19 +00:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (cnt & (1<<7))
|
|
|
|
{
|
|
|
|
switch (cnt & 0x7)
|
|
|
|
{
|
2017-02-27 20:26:11 +00:00
|
|
|
case 0: // LCDC
|
|
|
|
VRAMMap_LCDC |= bankmask;
|
2017-01-18 03:03:19 +00:00
|
|
|
break;
|
|
|
|
|
2017-02-27 20:26:11 +00:00
|
|
|
case 1: // ABG
|
|
|
|
VRAMMap_ABG[(ofs & 0x1) + ((ofs & 0x2) << 1)] |= bankmask;
|
|
|
|
VRAMMap_ABG[(ofs & 0x1) + ((ofs & 0x2) << 1) + 2] |= bankmask;
|
2017-01-18 03:03:19 +00:00
|
|
|
break;
|
|
|
|
|
2017-02-27 20:26:11 +00:00
|
|
|
case 2: // AOBJ
|
|
|
|
VRAMMap_AOBJ[(ofs & 0x1) + ((ofs & 0x2) << 1)] |= bankmask;
|
|
|
|
VRAMMap_AOBJ[(ofs & 0x1) + ((ofs & 0x2) << 1) + 2] |= bankmask;
|
2017-01-18 03:03:19 +00:00
|
|
|
break;
|
|
|
|
|
2017-02-27 20:26:11 +00:00
|
|
|
case 3: // texture palette
|
|
|
|
VRAMMap_TexPal[(ofs & 0x1) + ((ofs & 0x2) << 1)] |= bankmask;
|
2017-01-18 03:03:19 +00:00
|
|
|
break;
|
|
|
|
|
2017-02-27 20:26:11 +00:00
|
|
|
case 4: // ABG ext palette
|
|
|
|
VRAMMap_ABGExtPal[((ofs & 0x1) << 1)] |= bankmask;
|
|
|
|
VRAMMap_ABGExtPal[((ofs & 0x1) << 1) + 1] |= bankmask;
|
2017-03-24 19:53:01 +00:00
|
|
|
GPU2D_A->BGExtPalDirty((ofs & 0x1) << 1);
|
2017-01-18 03:03:19 +00:00
|
|
|
break;
|
|
|
|
|
2017-02-27 20:26:11 +00:00
|
|
|
case 5: // AOBJ ext palette
|
|
|
|
VRAMMap_AOBJExtPal |= bankmask;
|
|
|
|
GPU2D_A->OBJExtPalDirty();
|
2017-01-18 03:03:19 +00:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void MapVRAM_H(u32 bank, u8 cnt)
|
|
|
|
{
|
|
|
|
u8 oldcnt = VRAMCNT[bank];
|
|
|
|
VRAMCNT[bank] = cnt;
|
|
|
|
|
|
|
|
if (oldcnt == cnt) return;
|
|
|
|
|
2017-02-27 20:26:11 +00:00
|
|
|
u32 bankmask = 1 << bank;
|
2017-01-18 03:03:19 +00:00
|
|
|
|
|
|
|
if (oldcnt & (1<<7))
|
|
|
|
{
|
|
|
|
switch (oldcnt & 0x3)
|
|
|
|
{
|
2017-02-27 20:26:11 +00:00
|
|
|
case 0: // LCDC
|
|
|
|
VRAMMap_LCDC &= ~bankmask;
|
2017-01-18 03:03:19 +00:00
|
|
|
break;
|
|
|
|
|
2017-02-27 20:26:11 +00:00
|
|
|
case 1: // BBG
|
|
|
|
VRAMMap_BBG[0] &= ~bankmask;
|
|
|
|
VRAMMap_BBG[1] &= ~bankmask;
|
|
|
|
VRAMMap_BBG[4] &= ~bankmask;
|
|
|
|
VRAMMap_BBG[5] &= ~bankmask;
|
2017-01-18 03:03:19 +00:00
|
|
|
break;
|
|
|
|
|
2017-02-27 20:26:11 +00:00
|
|
|
case 2: // BBG ext palette
|
|
|
|
UNMAP_RANGE(VRAMMap_BBGExtPal, 0, 4);
|
|
|
|
GPU2D_B->BGExtPalDirty(0);
|
|
|
|
GPU2D_B->BGExtPalDirty(2);
|
2017-01-18 03:03:19 +00:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (cnt & (1<<7))
|
|
|
|
{
|
|
|
|
switch (cnt & 0x3)
|
|
|
|
{
|
2017-02-27 20:26:11 +00:00
|
|
|
case 0: // LCDC
|
|
|
|
VRAMMap_LCDC |= bankmask;
|
2017-01-18 03:03:19 +00:00
|
|
|
break;
|
|
|
|
|
2017-02-27 20:26:11 +00:00
|
|
|
case 1: // BBG
|
|
|
|
VRAMMap_BBG[0] |= bankmask;
|
|
|
|
VRAMMap_BBG[1] |= bankmask;
|
|
|
|
VRAMMap_BBG[4] |= bankmask;
|
|
|
|
VRAMMap_BBG[5] |= bankmask;
|
2017-01-18 03:03:19 +00:00
|
|
|
break;
|
|
|
|
|
2017-02-27 20:26:11 +00:00
|
|
|
case 2: // BBG ext palette
|
|
|
|
MAP_RANGE(VRAMMap_BBGExtPal, 0, 4);
|
|
|
|
GPU2D_B->BGExtPalDirty(0);
|
|
|
|
GPU2D_B->BGExtPalDirty(2);
|
2017-01-18 03:03:19 +00:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void MapVRAM_I(u32 bank, u8 cnt)
|
|
|
|
{
|
|
|
|
u8 oldcnt = VRAMCNT[bank];
|
|
|
|
VRAMCNT[bank] = cnt;
|
|
|
|
|
|
|
|
if (oldcnt == cnt) return;
|
|
|
|
|
2017-02-27 20:26:11 +00:00
|
|
|
u32 bankmask = 1 << bank;
|
2017-01-18 03:03:19 +00:00
|
|
|
|
|
|
|
if (oldcnt & (1<<7))
|
|
|
|
{
|
|
|
|
switch (oldcnt & 0x3)
|
|
|
|
{
|
2017-02-27 20:26:11 +00:00
|
|
|
case 0: // LCDC
|
|
|
|
VRAMMap_LCDC &= ~bankmask;
|
2017-01-18 03:03:19 +00:00
|
|
|
break;
|
|
|
|
|
2017-02-27 20:26:11 +00:00
|
|
|
case 1: // BBG
|
|
|
|
VRAMMap_BBG[2] &= ~bankmask;
|
|
|
|
VRAMMap_BBG[3] &= ~bankmask;
|
|
|
|
VRAMMap_BBG[6] &= ~bankmask;
|
|
|
|
VRAMMap_BBG[7] &= ~bankmask;
|
2017-01-18 03:03:19 +00:00
|
|
|
break;
|
|
|
|
|
2017-02-27 20:26:11 +00:00
|
|
|
case 2: // BOBJ
|
|
|
|
UNMAP_RANGE(VRAMMap_BOBJ, 0, 8);
|
2017-01-18 03:03:19 +00:00
|
|
|
break;
|
|
|
|
|
2017-02-27 20:26:11 +00:00
|
|
|
case 3: // BOBJ ext palette
|
|
|
|
VRAMMap_BOBJExtPal &= ~bankmask;
|
|
|
|
GPU2D_B->OBJExtPalDirty();
|
2017-01-18 03:03:19 +00:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (cnt & (1<<7))
|
|
|
|
{
|
|
|
|
switch (cnt & 0x3)
|
|
|
|
{
|
2017-02-27 20:26:11 +00:00
|
|
|
case 0: // LCDC
|
|
|
|
VRAMMap_LCDC |= bankmask;
|
2017-01-18 03:03:19 +00:00
|
|
|
break;
|
|
|
|
|
2017-02-27 20:26:11 +00:00
|
|
|
case 1: // BBG
|
|
|
|
VRAMMap_BBG[2] |= bankmask;
|
|
|
|
VRAMMap_BBG[3] |= bankmask;
|
|
|
|
VRAMMap_BBG[6] |= bankmask;
|
|
|
|
VRAMMap_BBG[7] |= bankmask;
|
2017-01-18 03:03:19 +00:00
|
|
|
break;
|
|
|
|
|
2017-02-27 20:26:11 +00:00
|
|
|
case 2: // BOBJ
|
|
|
|
MAP_RANGE(VRAMMap_BOBJ, 0, 8);
|
2017-01-18 03:03:19 +00:00
|
|
|
break;
|
|
|
|
|
2017-02-27 20:26:11 +00:00
|
|
|
case 3: // BOBJ ext palette
|
|
|
|
VRAMMap_BOBJExtPal |= bankmask;
|
|
|
|
GPU2D_B->OBJExtPalDirty();
|
2017-01-18 03:03:19 +00:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2018-12-18 16:04:42 +00:00
|
|
|
void SetPowerCnt(u32 val)
|
2017-02-01 20:57:25 +00:00
|
|
|
{
|
2018-12-18 16:04:42 +00:00
|
|
|
// POWCNT1 effects:
|
|
|
|
// * bit0: asplodes hardware??? not tested.
|
|
|
|
// * bit1: disables engine A palette and OAM (zero-filled) (TODO: affects mem timings???)
|
|
|
|
// * bit2: disables rendering engine, resets its internal state (polygons and registers)
|
|
|
|
// * bit3: disables geometry engine
|
|
|
|
// * bit9: disables engine B palette, OAM and rendering (screen turns white)
|
|
|
|
// * bit15: screen swap
|
|
|
|
|
|
|
|
if (!(val & (1<<0))) printf("!!! CLEARING POWCNT BIT0. DANGER\n");
|
|
|
|
|
|
|
|
GPU2D_A->SetEnabled(val & (1<<1));
|
|
|
|
GPU2D_B->SetEnabled(val & (1<<9));
|
|
|
|
GPU3D::SetEnabled(val & (1<<3), val & (1<<2));
|
|
|
|
|
2019-05-12 13:01:40 +00:00
|
|
|
AssignFramebuffers();
|
2017-02-01 20:57:25 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
2017-06-26 09:02:10 +00:00
|
|
|
void DisplayFIFO(u32 x)
|
|
|
|
{
|
|
|
|
// sample the FIFO
|
|
|
|
// as this starts 16 cycles (~3 pixels) before display start,
|
|
|
|
// we aren't aligned to the 8-pixel grid
|
|
|
|
if (x > 0)
|
|
|
|
{
|
|
|
|
if (x == 8)
|
|
|
|
GPU2D_A->SampleFIFO(0, 5);
|
|
|
|
else
|
|
|
|
GPU2D_A->SampleFIFO(x-11, 8);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (x < 256)
|
|
|
|
{
|
|
|
|
// transfer the next 8 pixels
|
|
|
|
NDS::CheckDMAs(0, 0x04);
|
|
|
|
NDS::ScheduleEvent(NDS::Event_DisplayFIFO, true, 6*8, DisplayFIFO, x+8);
|
|
|
|
}
|
|
|
|
else
|
|
|
|
GPU2D_A->SampleFIFO(253, 3); // sample the remaining pixels
|
|
|
|
}
|
|
|
|
|
2017-01-18 03:03:19 +00:00
|
|
|
void StartFrame()
|
|
|
|
{
|
2017-06-26 09:02:10 +00:00
|
|
|
// only run the display FIFO if needed:
|
|
|
|
// * if it is used for display or capture
|
|
|
|
// * if we have display FIFO DMA
|
|
|
|
RunFIFO = GPU2D_A->UsesFIFO() || NDS::DMAsInMode(0, 0x04);
|
|
|
|
|
2017-05-10 00:21:02 +00:00
|
|
|
TotalScanlines = 0;
|
2017-01-18 03:03:19 +00:00
|
|
|
StartScanline(0);
|
|
|
|
}
|
|
|
|
|
2017-02-03 17:47:40 +00:00
|
|
|
void StartHBlank(u32 line)
|
|
|
|
{
|
|
|
|
DispStat[0] |= (1<<1);
|
|
|
|
DispStat[1] |= (1<<1);
|
|
|
|
|
2017-05-27 21:47:20 +00:00
|
|
|
if (VCount < 192)
|
|
|
|
{
|
2017-06-26 09:02:10 +00:00
|
|
|
// draw
|
|
|
|
// note: this should start 48 cycles after the scanline start
|
2017-07-21 08:19:56 +00:00
|
|
|
if (line < 192)
|
|
|
|
{
|
|
|
|
GPU2D_A->DrawScanline(line);
|
|
|
|
GPU2D_B->DrawScanline(line);
|
|
|
|
}
|
2017-06-26 09:02:10 +00:00
|
|
|
|
2017-05-27 21:47:20 +00:00
|
|
|
NDS::CheckDMAs(0, 0x02);
|
|
|
|
}
|
|
|
|
else if (VCount == 215)
|
|
|
|
{
|
|
|
|
GPU3D::VCount215();
|
|
|
|
}
|
2017-02-03 17:47:40 +00:00
|
|
|
|
2017-03-02 23:48:26 +00:00
|
|
|
if (DispStat[0] & (1<<4)) NDS::SetIRQ(0, NDS::IRQ_HBlank);
|
|
|
|
if (DispStat[1] & (1<<4)) NDS::SetIRQ(1, NDS::IRQ_HBlank);
|
2017-02-03 17:47:40 +00:00
|
|
|
|
2017-05-10 00:21:02 +00:00
|
|
|
if (VCount < 262)
|
2017-02-03 17:47:40 +00:00
|
|
|
NDS::ScheduleEvent(NDS::Event_LCD, true, (LINE_CYCLES - HBLANK_CYCLES), StartScanline, line+1);
|
2017-05-10 00:21:02 +00:00
|
|
|
else
|
|
|
|
NDS::ScheduleEvent(NDS::Event_LCD, true, (LINE_CYCLES - HBLANK_CYCLES), FinishFrame, line+1);
|
|
|
|
}
|
|
|
|
|
|
|
|
void FinishFrame(u32 lines)
|
|
|
|
{
|
2019-05-12 13:01:40 +00:00
|
|
|
FrontBuffer = FrontBuffer ? 0 : 1;
|
|
|
|
AssignFramebuffers();
|
|
|
|
|
2017-05-10 00:21:02 +00:00
|
|
|
TotalScanlines = lines;
|
2017-02-03 17:47:40 +00:00
|
|
|
}
|
|
|
|
|
2017-01-18 03:03:19 +00:00
|
|
|
void StartScanline(u32 line)
|
|
|
|
{
|
2017-05-10 00:21:02 +00:00
|
|
|
if (line == 0)
|
|
|
|
VCount = 0;
|
|
|
|
else if (NextVCount != -1)
|
|
|
|
VCount = NextVCount;
|
|
|
|
else
|
|
|
|
VCount++;
|
|
|
|
|
|
|
|
NextVCount = -1;
|
2017-01-18 03:03:19 +00:00
|
|
|
|
2017-02-03 17:47:40 +00:00
|
|
|
DispStat[0] &= ~(1<<1);
|
|
|
|
DispStat[1] &= ~(1<<1);
|
|
|
|
|
2017-05-10 00:21:02 +00:00
|
|
|
if (VCount == VMatch[0])
|
2017-01-18 03:03:19 +00:00
|
|
|
{
|
|
|
|
DispStat[0] |= (1<<2);
|
|
|
|
|
2017-03-02 23:48:26 +00:00
|
|
|
if (DispStat[0] & (1<<5)) NDS::SetIRQ(0, NDS::IRQ_VCount);
|
2017-01-18 03:03:19 +00:00
|
|
|
}
|
|
|
|
else
|
|
|
|
DispStat[0] &= ~(1<<2);
|
|
|
|
|
2017-05-10 00:21:02 +00:00
|
|
|
if (VCount == VMatch[1])
|
2017-01-18 03:03:19 +00:00
|
|
|
{
|
|
|
|
DispStat[1] |= (1<<2);
|
|
|
|
|
2017-03-02 23:48:26 +00:00
|
|
|
if (DispStat[1] & (1<<5)) NDS::SetIRQ(1, NDS::IRQ_VCount);
|
2017-01-18 03:03:19 +00:00
|
|
|
}
|
|
|
|
else
|
|
|
|
DispStat[1] &= ~(1<<2);
|
|
|
|
|
2017-05-10 00:21:02 +00:00
|
|
|
GPU2D_A->CheckWindows(VCount);
|
|
|
|
GPU2D_B->CheckWindows(VCount);
|
2017-04-09 01:35:32 +00:00
|
|
|
|
2017-05-10 00:21:02 +00:00
|
|
|
if (VCount >= 2 && VCount < 194)
|
2017-03-20 21:18:35 +00:00
|
|
|
NDS::CheckDMAs(0, 0x03);
|
2017-05-10 00:21:02 +00:00
|
|
|
else if (VCount == 194)
|
2017-03-20 21:18:35 +00:00
|
|
|
NDS::StopDMAs(0, 0x03);
|
|
|
|
|
2017-01-18 03:03:19 +00:00
|
|
|
if (line < 192)
|
|
|
|
{
|
2017-03-21 01:11:49 +00:00
|
|
|
if (line == 0)
|
|
|
|
{
|
|
|
|
GPU2D_A->VBlankEnd();
|
|
|
|
GPU2D_B->VBlankEnd();
|
|
|
|
}
|
|
|
|
|
2017-06-26 09:02:10 +00:00
|
|
|
if (RunFIFO)
|
2019-01-05 04:28:58 +00:00
|
|
|
NDS::ScheduleEvent(NDS::Event_DisplayFIFO, false, 32, DisplayFIFO, 0);
|
2017-01-18 03:03:19 +00:00
|
|
|
}
|
2017-05-10 00:21:02 +00:00
|
|
|
|
|
|
|
if (VCount == 262)
|
2017-01-18 03:03:19 +00:00
|
|
|
{
|
|
|
|
// frame end
|
|
|
|
|
|
|
|
DispStat[0] &= ~(1<<0);
|
|
|
|
DispStat[1] &= ~(1<<0);
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
2017-05-10 00:21:02 +00:00
|
|
|
if (VCount == 192)
|
2019-05-17 20:50:41 +00:00
|
|
|
{
|
2017-01-18 03:03:19 +00:00
|
|
|
// VBlank
|
|
|
|
DispStat[0] |= (1<<0);
|
|
|
|
DispStat[1] |= (1<<0);
|
|
|
|
|
2017-03-20 21:18:35 +00:00
|
|
|
NDS::StopDMAs(0, 0x04);
|
|
|
|
|
2017-02-03 17:47:40 +00:00
|
|
|
NDS::CheckDMAs(0, 0x01);
|
|
|
|
NDS::CheckDMAs(1, 0x11);
|
|
|
|
|
2017-03-02 23:48:26 +00:00
|
|
|
if (DispStat[0] & (1<<3)) NDS::SetIRQ(0, NDS::IRQ_VBlank);
|
|
|
|
if (DispStat[1] & (1<<3)) NDS::SetIRQ(1, NDS::IRQ_VBlank);
|
2017-02-10 14:24:46 +00:00
|
|
|
|
|
|
|
GPU2D_A->VBlank();
|
|
|
|
GPU2D_B->VBlank();
|
|
|
|
GPU3D::VBlank();
|
2017-01-18 03:03:19 +00:00
|
|
|
}
|
2017-05-23 21:38:28 +00:00
|
|
|
else if (VCount == 144)
|
|
|
|
{
|
|
|
|
GPU3D::VCount144();
|
|
|
|
}
|
2017-01-18 03:03:19 +00:00
|
|
|
}
|
2017-02-03 17:47:40 +00:00
|
|
|
|
|
|
|
NDS::ScheduleEvent(NDS::Event_LCD, true, HBLANK_CYCLES, StartHBlank, line);
|
2017-01-18 03:03:19 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
void SetDispStat(u32 cpu, u16 val)
|
|
|
|
{
|
|
|
|
val &= 0xFFB8;
|
|
|
|
DispStat[cpu] &= 0x0047;
|
|
|
|
DispStat[cpu] |= val;
|
|
|
|
|
|
|
|
VMatch[cpu] = (val >> 8) | ((val & 0x80) << 1);
|
|
|
|
}
|
|
|
|
|
2017-05-10 00:21:02 +00:00
|
|
|
void SetVCount(u16 val)
|
|
|
|
{
|
|
|
|
// VCount write is delayed until the next scanline
|
|
|
|
|
|
|
|
// TODO: how does the 3D engine react to VCount writes while it's rendering?
|
2018-12-18 16:04:42 +00:00
|
|
|
// 3D engine seems to give up on the current frame in that situation, repeating the last two scanlines
|
2017-05-10 00:21:02 +00:00
|
|
|
// TODO: also check the various DMA types that can be involved
|
|
|
|
|
|
|
|
NextVCount = val;
|
|
|
|
}
|
|
|
|
|
2017-01-18 03:03:19 +00:00
|
|
|
}
|