Commit Graph

40760 Commits

Author SHA1 Message Date
JosJuice a2a733f4a3 Contributing.md: Make our stance on leaked information explicit
We have been operating on this principle for a while. Let's make it
explicit so that new contributors know about it.
2023-11-03 18:53:49 +01:00
Admiral H. Curtiss c7243c368f
Merge pull request #12270 from AdmiralCurtiss/clang-enum-out-of-range-2
Netplay: Fix building on clang 17.
2023-11-03 16:34:50 +01:00
Admiral H. Curtiss b181842092
Netplay: Fix building on clang 17. 2023-11-03 16:15:04 +01:00
Admiral H. Curtiss 7dae4dd3d2
Merge pull request #12266 from noahpistilli/kd-junk-data
IOS/KD: Disable download and mail when files are invalid
2023-11-03 15:27:44 +01:00
Sketch ad2044993d IOS/KD: Disable download and mail when files are invalid 2023-11-02 22:05:56 -04:00
JosJuice 482da7975b Jit: Define new terms related to fastmem
Dolphin's JITs have a minor terminology problem: The term "fastmem" can
refer to either the system of switching between a fast path and a slow
path using backpatching, or to the fast path itself. To hopefully make
things clearer, I'm adding some new terms, defining the old and new
terms as follows:

Fastmem: The system of switching from a fast path to a slow path by
backpatching when an invalid memory access occurs.

Fast access: A code path that accesses guest memory without calling C++
code.

Slow access: A code path that accesses guest memory by calling C++ code.
2023-11-02 21:30:12 +01:00
Admiral H. Curtiss b4c0da30bd
Merge pull request #12244 from DacoTaco/feature/crypto
IOS: implement /dev/aes & /dev/sha
2023-11-02 19:36:40 +01:00
DacoTaco 2241aaf168 IOS: implement /dev/aes 2023-11-01 22:08:39 +01:00
DacoTaco d4c18f3f31 IOS: implement /dev/sha 2023-11-01 22:08:39 +01:00
JosJuice 13c70eeb31
Merge pull request #12257 from Wack0/patch-1
JIT64 (Jit_Integer): for twx instructions, raise exception with correct SRR0
2023-11-01 21:10:39 +01:00
Admiral H. Curtiss 17122f171a
Merge pull request #12260 from Pokechu22/multiple-fifo-recording-regression
Fix regression when recording multiple fifologs
2023-11-01 12:01:52 +01:00
Admiral H. Curtiss ff009dd8b5
Merge pull request #12258 from skyfloogle/traversal-logging
Netplay: Don't log skippable events as errors
2023-11-01 11:56:39 +01:00
Admiral H. Curtiss 166d8a1aa3
Merge pull request #12211 from JosJuice/toggle-dcache
PowerPC: Allow toggling write-back cache during emulation
2023-11-01 11:53:56 +01:00
JosJuice d04e67be3d Add fastmem arena setting
Just for debugging.
2023-10-31 19:43:49 +01:00
JosJuice 8686536d7d Jit: Always initialize fastmem arena
If dcache is enabled when the game starts, initializing the fastmem
arena is still useful in case the user changes the dcache setting.
And initializing it doesn't really cost anything.
2023-10-31 19:43:49 +01:00
JosJuice 0606433404 JitArm64: Check fastmem instead of fastmem_arena
Preparation for the next commit.

JitArm64 has been conflating these two flags. Most of the stuff that's
been guarded by fastmem_arena checks in fact requires fastmem.

When we have fastmem_arena without fastmem, it would be possible to do
things a bit more efficiently than what this commit does, but it's
non-trivial and therefore I will leave it out of this PR. With this
commit, we effectively have the same behavior as before this PR - plus
the added ability to toggle fastmem with a cache clear.
2023-10-31 19:43:49 +01:00
JosJuice b3bfcc5d7f PowerPC: Allow toggling write-back cache during emulation
Now that PR 10575 is merged, the JIT automatically clears its cache
when this setting is changed, making this reasonable to implement.
2023-10-31 19:43:49 +01:00
JosJuice 899d61bc7d Jit64: Recompile asm routines on cache clear
This is needed so that the checks added in the previous commit will be
reevaluated if the value of m_enable_dcache changes.

JitArm64 was already recompiling its asm routines on cache clear by
necessity. It doesn't have the same setup as Jit64 where the asm
routines are in a separate region, so clearing the JitArm64 cache
results in the asm routines being cleared too.
2023-10-31 19:43:49 +01:00
JosJuice 5e74a8b850 Jit64: Don't make use of fastmem arena when dcache is enabled
Some code paths in EmuCodeBlock.cpp that were checking fastmem_arena
should really also be checking m_enable_dcache.

Because JitArm64 centralizes more or less all memory access to the
EmitBackpatchRoutine function and because that function already
contained a check, JitArm64 works fine without the additional checks
added by this commit. Regardless, I added the checks to MMU.cpp instead
of EmuCodeBlock.cpp where applicable so they would be available to
JitArm64. Maybe one day JitArm64 will need them if its code gets
restructured.
2023-10-31 19:43:40 +01:00
JosJuice b32ac9353e
Merge pull request #12262 from AdmiralCurtiss/last-state-order-refactor
Core/State: Refactor logic for determining the relative age of existing savestates.
2023-10-31 19:39:47 +01:00
Admiral H. Curtiss 8e51f0c054
Merge pull request #12264 from Dentomologist/cheats_manager_fix_factory_widget_spacing
Cheats Manager: Fix factory widget spacing
2023-10-31 19:02:58 +01:00
Dentomologist 74d3ba7c46 Cheats Manager: Fix factory widget spacing
Add stretch to bottom of factory widget to prevent the Data Type
QGroupBox from getting stretched out awkwardly.
2023-10-30 17:44:39 -07:00
Sintendo ef7f3b5bac UnitTests: Test ApproximateReciprocalSquareRoot 2023-10-30 22:39:12 +01:00
Admiral H. Curtiss 437946fb1a
Core/State: Refactor logic for determining the relative age of existing savestates.
The code previously did this indirectly via `std::map<double, int>`, the key being the timestamp, which required a questionable workaround for the case where multiple states have the same timestamp. By having a particular combination of timestamps in the on-disk savestates, you could cause this workaround to infinitely loop, locking up Dolphin. This avoids this completely by refactoring the logic and just using `std::vector` instead.
2023-10-30 19:19:01 +01:00
Admiral H. Curtiss 99a3bbc055
Core/State: Return an empty string on invalid input to SystemTimeAsDoubleToString(). 2023-10-30 19:19:01 +01:00
Admiral H. Curtiss 03f8ec09eb
Merge pull request #12261 from TryTwo/Bugfix_GetAddress
PPCDebugInterface:  Tweak regex in GetMemoryAddressFromInstruction to fix bugs
2023-10-30 10:49:13 +01:00
Admiral H. Curtiss 045868bbb4
Merge pull request #12256 from malleoz/savestate_read_header_fix
Core: Fix UI slowdown for savestate timestamp reads
2023-10-30 10:45:14 +01:00
TryTwo 490e4b78a7 Bugfixes for PPCDebugInterface::GetMemoryAddressFromInstruction
FromChars cannot return a value prefixed with 0x.
Possible regex failures on rX, rY, rZ
2023-10-29 22:54:45 -07:00
Pokechu22 35831f342e Fix regression when recording multiple fifologs
Since ccf92a3e56, recording fifologs multiple times after launching dolphin caused all initial state to not be saved (the initial contents of bpmem, cpmem, etc were all zeroed out). For some games, this was not noticeable, as most registers were set each frame, but for others, this resulted in completely broken fifologs. (Note that recording fifologs also required 05181f6b88 and 9e0755a598 to be cherry-picked due to other, since fixed, regressions.)

This was because previously, `Renderer::CheckFifoRecording` was called every frame, but ccf92a3e56 changed it into a callback (`m_end_of_frame_event`) that was removed when recording ended. Thus, before, `OpcodeDecoder::g_record_fifo_data = IsRecording()` was called when `IsRecording()` returned false, but after that commit `g_record_fifo_data` never got changed back to false, so the check for `was_recording` only ever passed on the first fifolog recorded (even after stopping and starting a game).

There may still be another issue lurking, as I'm not sure if all broken fifologs were caused by recording multiple fifologs (for instance, on https://bugs.dolphin-emu.org/issues/13377, only one fifolog was initially uploaded, but it was affected by an issue with the same symptoms as this).
2023-10-29 15:23:31 -07:00
Floogle bee6d5bfb6 Netplay: Don't log skippable events as errors 2023-10-28 18:06:07 +02:00
Tilka 220988d064
Merge pull request #12161 from krnlyng/tools_no_show_raw_insn
Tools: fix perf-disassemble.sh.
2023-10-28 03:28:28 +01:00
Tilka 2ccc2bfb2e
Merge pull request #12250 from Sintendo/dcbx-nit
Jit_LoadStore: Minor dcbx register optimizations
2023-10-28 02:33:51 +01:00
Tilka 9bea807732
Merge pull request #12249 from Sintendo/frsqrte-nit
PowerPC: Negate m_dec values in frsqrte table
2023-10-28 02:15:05 +01:00
Tilka 2212a5b225
Merge pull request #12254 from AdmiralCurtiss/savestate-no-xfb-stride
VideoCommon: Don't swap on state load when there's no XFB.
2023-10-28 02:14:30 +01:00
Tilka 7c243a110a
Merge pull request #12253 from TellowKrinkle/AsahiGL
Fix shader compiles on Asahi Linux
2023-10-28 02:12:40 +01:00
Tilka ef447bb40b
Merge pull request #12248 from Dentomologist/cheatsearch_use_std_comparison_functions
CheatSearch: Use std comparison function objects
2023-10-28 02:11:18 +01:00
Tilka ce895f1205
Merge pull request #12255 from jordan-woyak/sdl-360
ControllerInterface/SDL: Remove Xbox 360 controller disabling hack.
2023-10-28 02:10:46 +01:00
Tilka 6bac012001
Merge pull request #12251 from Dentomologist/skylanderportal_make_protected_variables_private
SkylanderPortal: Make protected variables private
2023-10-28 02:09:28 +01:00
Rairii c9cd0b626b
JIT64: for twx instruction, raise exception with correct SRR0 2023-10-27 13:27:36 +01:00
sowens99 cddc75c28b Core: Fix UI slowdown for savestate timestamp reads 2023-10-26 22:32:47 -04:00
Jordan Woyak 30ce1f2ec2 ControllerInterface/SDL: Remove Xbox 360 controller disabling hack. 2023-10-26 18:04:11 -05:00
JosJuice 3454bc4c3c Translation resources sync with Transifex 2023-10-25 22:43:24 +02:00
Admiral H. Curtiss 4f0c8b1657
VideoCommon: Don't swap on state load when there's no XFB.
This triggers an assert in TCacheEntry::SetXfbCopy() otherwise if you load a savestate that was made before the first XFB has been rendered.
2023-10-25 18:24:42 +02:00
TellowKrinkle 4f2a79058a VideoBackends:OGL: Handle when SSBOs are only supported in some shader stages 2023-10-25 17:47:04 +02:00
TellowKrinkle 323aea60d6 VideoCommon: Fix VS point/line on older GLSL 2023-10-24 23:18:01 -05:00
Sintendo 171f76ae07 Jit_LoadStore: Another minor dcbx optimization
The multiplication needs the value from RSCRATCH2, but shouldn't
overwrite it as it is still needed later. The original code solved this
by copying RSCRATCH2 to another register first.

As it turns out, the other register involved in the multiplication can
safely be overwritten, so we can swap the operands around and use
RSCRATCH2 directly without making a copy.

Before:
33 D2                xor         edx,edx
8B 45 64             mov         eax,dword ptr [rbp+64h]
85 C0                test        eax,eax
7E 30                jle         000002D4DF373F6B
44 8B B5 D4 02 00 00 mov         r14d,dword ptr [rbp+2D4h]
44 8B E8             mov         r13d,eax
BF 07 00 00 00       mov         edi,7
F7 F7                div         eax,edi
41 8D 56 FF          lea         edx,[r14-1]
3B C2                cmp         eax,edx
0F 42 D0             cmovb       edx,eax
44 2B F2             sub         r14d,edx
44 89 B5 D4 02 00 00 mov         dword ptr [rbp+2D4h],r14d
8B C2                mov         eax,edx
0F AF C7             imul        eax,edi
44 2B E8             sub         r13d,eax
44 89 6D 64          mov         dword ptr [rbp+64h],r13d
44 8D 72 01          lea         r14d,[rdx+1]

After:
33 D2                xor         edx,edx
8B 45 64             mov         eax,dword ptr [rbp+64h]
85 C0                test        eax,eax
7E 2E                jle         0000021C01013F69
44 8B B5 D4 02 00 00 mov         r14d,dword ptr [rbp+2D4h]
44 8B E8             mov         r13d,eax
BF 07 00 00 00       mov         edi,7
F7 F7                div         eax,edi
41 8D 56 FF          lea         edx,[r14-1]
3B C2                cmp         eax,edx
0F 42 D0             cmovb       edx,eax
44 2B F2             sub         r14d,edx
44 89 B5 D4 02 00 00 mov         dword ptr [rbp+2D4h],r14d
0F AF FA             imul        edi,edx
44 2B EF             sub         r13d,edi
44 89 6D 64          mov         dword ptr [rbp+64h],r13d
44 8D 72 01          lea         r14d,[rdx+1]
2023-10-24 00:42:35 +02:00
Dentomologist 3ba5cd30ff SkylanderPortal: Make protected variables private
SkylanderPortal is final, so having member variables be protected
instead of private is just misleading.
2023-10-22 12:00:49 -07:00
Sintendo dd58a8d65e Jit_LoadStore: Minor dcbx register optimization
Instructions referencing registers r8-r15 take an additional byte to
encode. `reg_downcount` may be assigned to one of these registers, so it
is a small size win to store the downcount value in `RSCRATCH` first.

Before:
33 D2                xor         edx,edx
44 8B 6D 64          mov         r13d,dword ptr [rbp+64h]
45 85 ED             test        r13d,r13d
7E 30                jle         0000023546B43F6D
44 8B B5 D4 02 00 00 mov         r14d,dword ptr [rbp+2D4h]
41 8B C5             mov         eax,r13d
BF 07 00 00 00       mov         edi,7
F7 F7                div         eax,edi

After:
33 D2                xor         edx,edx
8B 45 64             mov         eax,dword ptr [rbp+64h]
85 C0                test        eax,eax
7E 30                jle         000001AFBBAE359D
44 8B B5 D4 02 00 00 mov         r14d,dword ptr [rbp+2D4h]
44 8B E8             mov         r13d,eax
BF 07 00 00 00       mov         edi,7
F7 F7                div         eax,edi
2023-10-22 15:13:52 +02:00
Sintendo 3c3168706c PowerPC: Negate m_dec values in frsqrte table
This value is used in a multiplication. The result of this
multiplication is then subtracted from m_base. By negating m_dec, we are
free to use an addition instead.

On x64, this saves an instruction.
2023-10-21 21:08:21 +02:00
Dentomologist c5a8a3fd4a CheatSearch: Use std comparison function objects 2023-10-20 16:05:47 -07:00