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Jit_LoadStore: Minor dcbx register optimization 

Instructions referencing registers r8-r15 take an additional byte to
encode. `reg_downcount` may be assigned to one of these registers, so it
is a small size win to store the downcount value in `RSCRATCH` first.

Before:
33 D2                xor         edx,edx
44 8B 6D 64          mov         r13d,dword ptr [rbp+64h]
45 85 ED             test        r13d,r13d
7E 30                jle         0000023546B43F6D
44 8B B5 D4 02 00 00 mov         r14d,dword ptr [rbp+2D4h]
41 8B C5             mov         eax,r13d
BF 07 00 00 00       mov         edi,7
F7 F7                div         eax,edi

After:
33 D2                xor         edx,edx
8B 45 64             mov         eax,dword ptr [rbp+64h]
85 C0                test        eax,eax
7E 30                jle         000001AFBBAE359D
44 8B B5 D4 02 00 00 mov         r14d,dword ptr [rbp+2D4h]
44 8B E8             mov         r13d,eax
BF 07 00 00 00       mov         edi,7
F7 F7                div         eax,edi
This commit is contained in:
Sintendo 2023-10-22 15:13:46 +02:00
parent 60e3b4c093
commit dd58a8d65e
1 changed files with 3 additions and 3 deletions
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6
Source/Core/Core/PowerPC/Jit64/Jit_LoadStore.cpp
View File

@ -274,11 +274,11 @@ void Jit64::dcbx(UGeckoInstruction inst)
// the upper bits for the DIV instruction in the downcount > 0 case.
XOR(32, R(RSCRATCH2), R(RSCRATCH2));
MOV(32, R(reg_downcount), PPCSTATE(downcount));
TEST(32, R(reg_downcount), R(reg_downcount)); // if (downcount <= 0)
MOV(32, R(RSCRATCH), PPCSTATE(downcount));
TEST(32, R(RSCRATCH), R(RSCRATCH)); // if (downcount <= 0)
FixupBranch downcount_is_zero_or_negative = J_CC(CC_LE); // only do 1 invalidation; else:
MOV(32, R(loop_counter), PPCSTATE_CTR);
MOV(32, R(RSCRATCH), R(reg_downcount));
MOV(32, R(reg_downcount), R(RSCRATCH));
MOV(32, R(reg_cycle_count), Imm32(cycle_count_per_loop));
DIV(32, R(reg_cycle_count)); // RSCRATCH = downcount / cycle_count
LEA(32, RSCRATCH2, MDisp(loop_counter, -1)); // RSCRATCH2 = CTR - 1