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Jit64: Don't make use of fastmem arena when dcache is enabled 

Some code paths in EmuCodeBlock.cpp that were checking fastmem_arena
should really also be checking m_enable_dcache.

Because JitArm64 centralizes more or less all memory access to the
EmitBackpatchRoutine function and because that function already
contained a check, JitArm64 works fine without the additional checks
added by this commit. Regardless, I added the checks to MMU.cpp instead
of EmuCodeBlock.cpp where applicable so they would be available to
JitArm64. Maybe one day JitArm64 will need them if its code gets
restructured.
This commit is contained in:
JosJuice 2023-09-30 19:13:52 +02:00
parent b32ac9353e
commit 5e74a8b850
2 changed files with 10 additions and 2 deletions
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6
Source/Core/Core/PowerPC/Jit64Common/EmuCodeBlock.cpp
View File

@ -372,7 +372,8 @@ void EmuCodeBlock::SafeLoadToReg(X64Reg reg_value, const Gen::OpArg& opAddress,
FixupBranch exit;
const bool dr_set = (flags & SAFE_LOADSTORE_DR_ON) || m_jit.m_ppc_state.msr.DR;
const bool fast_check_address = !slowmem && dr_set && m_jit.jo.fastmem_arena;
const bool fast_check_address =
!slowmem && dr_set && m_jit.jo.fastmem_arena && !m_jit.m_ppc_state.m_enable_dcache;
if (fast_check_address)
{
FixupBranch slow = CheckIfSafeAddress(R(reg_value), reg_addr, registersInUse);
@ -541,7 +542,8 @@ void EmuCodeBlock::SafeWriteRegToReg(OpArg reg_value, X64Reg reg_addr, int acces
FixupBranch exit;
const bool dr_set = (flags & SAFE_LOADSTORE_DR_ON) || m_jit.m_ppc_state.msr.DR;
const bool fast_check_address = !slowmem && dr_set && m_jit.jo.fastmem_arena;
const bool fast_check_address =
!slowmem && dr_set && m_jit.jo.fastmem_arena && !m_jit.m_ppc_state.m_enable_dcache;
if (fast_check_address)
{
FixupBranch slow = CheckIfSafeAddress(reg_value, reg_addr, registersInUse);

6
Source/Core/Core/PowerPC/MMU.cpp
View File

@ -914,6 +914,9 @@ bool MMU::IsOptimizableRAMAddress(const u32 address) const
if (!m_ppc_state.msr.DR)
return false;
if (m_ppc_state.m_enable_dcache)
return false;
// TODO: This API needs to take an access size
//
// We store whether an access can be optimized to an unchecked access
@ -1211,6 +1214,9 @@ u32 MMU::IsOptimizableMMIOAccess(u32 address, u32 access_size) const
if (!m_ppc_state.msr.DR)
return 0;
if (m_ppc_state.m_enable_dcache)
return 0;
// Translate address
// If we also optimize for TLB mappings, we'd have to clear the
// JitCache on each TLB invalidation.