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Merge pull request #12250 from Sintendo/dcbx-nit 

Jit_LoadStore: Minor dcbx register optimizations
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Tilka 2023-10-28 02:33:51 +01:00 committed by GitHub
parent 9bea807732 171f76ae07
commit 2ccc2bfb2e
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GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 5 additions and 6 deletions
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11
Source/Core/Core/PowerPC/Jit64/Jit_LoadStore.cpp
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@ -274,11 +274,11 @@ void Jit64::dcbx(UGeckoInstruction inst)
// the upper bits for the DIV instruction in the downcount > 0 case.
XOR(32, R(RSCRATCH2), R(RSCRATCH2));
MOV(32, R(reg_downcount), PPCSTATE(downcount));
TEST(32, R(reg_downcount), R(reg_downcount)); // if (downcount <= 0)
MOV(32, R(RSCRATCH), PPCSTATE(downcount));
TEST(32, R(RSCRATCH), R(RSCRATCH)); // if (downcount <= 0)
FixupBranch downcount_is_zero_or_negative = J_CC(CC_LE); // only do 1 invalidation; else:
MOV(32, R(loop_counter), PPCSTATE_CTR);
MOV(32, R(RSCRATCH), R(reg_downcount));
MOV(32, R(reg_downcount), R(RSCRATCH));
MOV(32, R(reg_cycle_count), Imm32(cycle_count_per_loop));
DIV(32, R(reg_cycle_count)); // RSCRATCH = downcount / cycle_count
LEA(32, RSCRATCH2, MDisp(loop_counter, -1)); // RSCRATCH2 = CTR - 1
@ -291,10 +291,9 @@ void Jit64::dcbx(UGeckoInstruction inst)
// registers.
SUB(32, R(loop_counter), R(RSCRATCH2));
MOV(32, PPCSTATE_CTR, R(loop_counter)); // CTR -= RSCRATCH2
MOV(32, R(RSCRATCH), R(RSCRATCH2));
IMUL(32, RSCRATCH, R(reg_cycle_count));
IMUL(32, reg_cycle_count, R(RSCRATCH2));
// ^ Note that this cannot overflow because it's limited by (downcount/cycle_count).
SUB(32, R(reg_downcount), R(RSCRATCH));
SUB(32, R(reg_downcount), R(reg_cycle_count));
MOV(32, PPCSTATE(downcount), R(reg_downcount)); // downcount -= (RSCRATCH2 * reg_cycle_count)
SetJumpTarget(downcount_is_zero_or_negative);