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bsnes/higan/processor/z80/disassembler.cpp

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Update to v101r13 release. byuu says: Changelog: - MS: added ms/bus - Z80: implemented JP/JR/CP/DI/IM/IN instructions - MD/VDP: added window layer emulation - MD/controller/gamepad: fixed d2,d3 bits (Altered Beast requires this) The Z80 is definitely a lot nastier than the LR35902. There's a lot of table duplication with HL→IX→IY; and two of them nest two levels deep (eg FD CB xx xx), so the design may change as I implement more.
2016-08-27 04:48:21 +00:00
auto Z80::disassemble(uint16 pc) -> string {
Update to v101r27 release. byuu says: Changelog: - SMS: emulated the generic Sega memory mapper (none of the more limited forms of it yet) - (missing ROM shift, ROM write enable emulation -- no commercial games use either, though) - SMS: bus I/O returns 0xff instead of 0x00 so games don't think every key is being pressed at once - (this is a hack until I implement proper controller pad reading) - SMS: very limited protection against reading/writing past the end of ROM/RAM (todo: should mirror) - SMS: VDP background HSCROLL subtracts, rather than adds, to the offset (unlike VSCROLL) - SMS: VDP VSCROLL is 9-bit, modulates voffset+vscroll to 224 in 192-line mode (32x28 tilemap) - SMS: VDP tiledata for backgrounds and sprites use `7-(x&7)` rather than `(x&7)` - SMS: fix output color to be 6-bit rather than 5-bit - SMS: left clip uses register `#7`, not palette color `#7` - (todo: do we want `color[reg7]` or `color[16 + reg7]`?) - SMS: refined handling of 0xcb, 0xed prefixes in the Z80 core and its disassembler - SMS: emulated (0xfd, 0xdd) 0xcb opcodes 0x00-0x0f (still missing 0x10-0xff) - SMS: fixed 0xcb 0b-----110 opcodes to use direct HL and never allow (IX,IY)+d - SMS: fixed major logic bug in (IX,IY)+d displacement - (was using `read(x)` instead of `operand()` for the displacement byte fetch before) - icarus: fake there always being 32KiB of RAM in all SMS cartridges for the time being - (not sure how to detect this stuff yet; although I've read it's not even really possible `>_>`) TODO: remove processor/z80/dissassembler.cpp code block at line 396 (as it's unnecessary.) Lots of commercial games are starting to show trashed graphical output now.
2017-01-06 08:11:38 +00:00
string s, output;
Update to v101r14 release. byuu says: Changelog: - rewrote the Z80 core to properly handle 0xDD (IX0 and 0xFD (IY) prefixes - added Processor::Z80::Bus as a new type of abstraction - all of the instructions implemented have their proper T-cycle counts now - added nall/certificates for my public keys The goal of `Processor::Z80::Bus` is to simulate the opcode fetches being 2-read + 2-wait states; operand+regular reads/writes being 3-read. For now, this puts the cycle counts inside the CPU core. At the moment, I can't think of any CPU core where this wouldn't be appropriate. But it's certainly possible that such a case exists. So this may not be the perfect solution. The reason for having it be a subclass of Processor::Z80 instead of virtual functions for the MasterSystem::CPU core to define is due to naming conflicts. I wanted the core to say `in(addr)` and have it take the four clocks. But I also wanted a version of the function that didn't consume time when called. One way to do that would be for the core to call `Z80::in(addr)`, which then calls the regular `in(addr)` that goes to `MasterSystem::CPU::in(addr)`. But I don't want to put the `Z80::` prefix on all of the opcodes. Very easy to forget it, and then end up not consuming any time. Another is to use uglier names in the `MasterSystem::CPU` core, like `read_`, `write_`, `in_`, `out_`, etc. But, yuck. So ... yeah, this is an experiment. We'll see how it goes.
2016-09-03 11:26:04 +00:00
s.append(hex(pc, 4L), " ");
uint8 prefix = 0x00;
Update to v101r16 release. byuu says: Changelog: - Z80: implemented 113 new instructions (all the easy LD/ADC/ADD/AND/OR/SBC/SUB/XOR ones) - Z80: used alternative to castable<To, With> type (manual cast inside instruction() register macros) - Z80: debugger: used register macros to reduce typing and increase readability - Z80: debugger: smarter way of handling multiple DD/FD prefixes (using gotos, yay!) - ruby: fixed crash with Windows input driver on exit (from SuperMikeMan) I have no idea how the P/V flag is supposed to work on AND/OR/XOR, so that's probably wrong for now. HALT is also mostly a dummy function for now. But I typically implement those inside instruction(), so it probably won't need to be changed? We'll see.
2016-09-06 00:09:33 +00:00
auto code = bus->read(pc++);
if(code == 0xdd || code == 0xfd) {
prefix = code;
code = bus->read(pc++);
Update to v101r14 release. byuu says: Changelog: - rewrote the Z80 core to properly handle 0xDD (IX0 and 0xFD (IY) prefixes - added Processor::Z80::Bus as a new type of abstraction - all of the instructions implemented have their proper T-cycle counts now - added nall/certificates for my public keys The goal of `Processor::Z80::Bus` is to simulate the opcode fetches being 2-read + 2-wait states; operand+regular reads/writes being 3-read. For now, this puts the cycle counts inside the CPU core. At the moment, I can't think of any CPU core where this wouldn't be appropriate. But it's certainly possible that such a case exists. So this may not be the perfect solution. The reason for having it be a subclass of Processor::Z80 instead of virtual functions for the MasterSystem::CPU core to define is due to naming conflicts. I wanted the core to say `in(addr)` and have it take the four clocks. But I also wanted a version of the function that didn't consume time when called. One way to do that would be for the core to call `Z80::in(addr)`, which then calls the regular `in(addr)` that goes to `MasterSystem::CPU::in(addr)`. But I don't want to put the `Z80::` prefix on all of the opcodes. Very easy to forget it, and then end up not consuming any time. Another is to use uglier names in the `MasterSystem::CPU` core, like `read_`, `write_`, `in_`, `out_`, etc. But, yuck. So ... yeah, this is an experiment. We'll see how it goes.
2016-09-03 11:26:04 +00:00
if(code == 0xdd || code == 0xfd) {
Update to v101r16 release. byuu says: Changelog: - Z80: implemented 113 new instructions (all the easy LD/ADC/ADD/AND/OR/SBC/SUB/XOR ones) - Z80: used alternative to castable<To, With> type (manual cast inside instruction() register macros) - Z80: debugger: used register macros to reduce typing and increase readability - Z80: debugger: smarter way of handling multiple DD/FD prefixes (using gotos, yay!) - ruby: fixed crash with Windows input driver on exit (from SuperMikeMan) I have no idea how the P/V flag is supposed to work on AND/OR/XOR, so that's probably wrong for now. HALT is also mostly a dummy function for now. But I typically implement those inside instruction(), so it probably won't need to be changed? We'll see.
2016-09-06 00:09:33 +00:00
if(prefix == 0xdd) {
s.append("ix:");
goto finish;
}
if(prefix == 0xfd) {
s.append("iy:");
goto finish;
}
Update to v101r14 release. byuu says: Changelog: - rewrote the Z80 core to properly handle 0xDD (IX0 and 0xFD (IY) prefixes - added Processor::Z80::Bus as a new type of abstraction - all of the instructions implemented have their proper T-cycle counts now - added nall/certificates for my public keys The goal of `Processor::Z80::Bus` is to simulate the opcode fetches being 2-read + 2-wait states; operand+regular reads/writes being 3-read. For now, this puts the cycle counts inside the CPU core. At the moment, I can't think of any CPU core where this wouldn't be appropriate. But it's certainly possible that such a case exists. So this may not be the perfect solution. The reason for having it be a subclass of Processor::Z80 instead of virtual functions for the MasterSystem::CPU core to define is due to naming conflicts. I wanted the core to say `in(addr)` and have it take the four clocks. But I also wanted a version of the function that didn't consume time when called. One way to do that would be for the core to call `Z80::in(addr)`, which then calls the regular `in(addr)` that goes to `MasterSystem::CPU::in(addr)`. But I don't want to put the `Z80::` prefix on all of the opcodes. Very easy to forget it, and then end up not consuming any time. Another is to use uglier names in the `MasterSystem::CPU` core, like `read_`, `write_`, `in_`, `out_`, etc. But, yuck. So ... yeah, this is an experiment. We'll see how it goes.
2016-09-03 11:26:04 +00:00
}
}
Update to v101r13 release. byuu says: Changelog: - MS: added ms/bus - Z80: implemented JP/JR/CP/DI/IM/IN instructions - MD/VDP: added window layer emulation - MD/controller/gamepad: fixed d2,d3 bits (Altered Beast requires this) The Z80 is definitely a lot nastier than the LR35902. There's a lot of table duplication with HL→IX→IY; and two of them nest two levels deep (eg FD CB xx xx), so the design may change as I implement more.
2016-08-27 04:48:21 +00:00
Update to v101r27 release. byuu says: Changelog: - SMS: emulated the generic Sega memory mapper (none of the more limited forms of it yet) - (missing ROM shift, ROM write enable emulation -- no commercial games use either, though) - SMS: bus I/O returns 0xff instead of 0x00 so games don't think every key is being pressed at once - (this is a hack until I implement proper controller pad reading) - SMS: very limited protection against reading/writing past the end of ROM/RAM (todo: should mirror) - SMS: VDP background HSCROLL subtracts, rather than adds, to the offset (unlike VSCROLL) - SMS: VDP VSCROLL is 9-bit, modulates voffset+vscroll to 224 in 192-line mode (32x28 tilemap) - SMS: VDP tiledata for backgrounds and sprites use `7-(x&7)` rather than `(x&7)` - SMS: fix output color to be 6-bit rather than 5-bit - SMS: left clip uses register `#7`, not palette color `#7` - (todo: do we want `color[reg7]` or `color[16 + reg7]`?) - SMS: refined handling of 0xcb, 0xed prefixes in the Z80 core and its disassembler - SMS: emulated (0xfd, 0xdd) 0xcb opcodes 0x00-0x0f (still missing 0x10-0xff) - SMS: fixed 0xcb 0b-----110 opcodes to use direct HL and never allow (IX,IY)+d - SMS: fixed major logic bug in (IX,IY)+d displacement - (was using `read(x)` instead of `operand()` for the displacement byte fetch before) - icarus: fake there always being 32KiB of RAM in all SMS cartridges for the time being - (not sure how to detect this stuff yet; although I've read it's not even really possible `>_>`) TODO: remove processor/z80/dissassembler.cpp code block at line 396 (as it's unnecessary.) Lots of commercial games are starting to show trashed graphical output now.
2017-01-06 08:11:38 +00:00
if(code == 0xcb && prefix) {
Update to v101r29 release. byuu says: Changelog: - SMS: background VDP clips partial tiles on the left (math may not be right ... it's hard to reason about) - SMS: fix background VDP scroll locks - SMS: fix VDP sprite coordinates - SMS: paint black after the end of the visible display - todo: shouldn't be a brute force at the end of the main VDP loop, should happen in each rendering unit - higan: removed emulator/debugger.hpp - higan: removed privileged: access specifier - SFC: removed debugger hooks - todo: remove sfc/debugger.hpp - Z80: fixed disassembly of (fd,dd) cb (displacement) (opcode) instructions - Z80: fix to prevent interrupts from firing between ix/iy prefixes and opcodes - todo: this is a rather hacky fix that could, if exploited, crash the stack frame - Z80: fix BIT flags - Z80: fix ADD hl,reg flags - Z80: fix CPD, CPI flags - Z80: fix IND, INI flags - Z80: fix INDR, INIT loop flag check - Z80: fix OUTD, OUTI flags - Z80: fix OTDR, OTIR loop flag check
2017-01-09 21:27:13 +00:00
auto d = (int8)bus->read(pc++);
Update to v101r27 release. byuu says: Changelog: - SMS: emulated the generic Sega memory mapper (none of the more limited forms of it yet) - (missing ROM shift, ROM write enable emulation -- no commercial games use either, though) - SMS: bus I/O returns 0xff instead of 0x00 so games don't think every key is being pressed at once - (this is a hack until I implement proper controller pad reading) - SMS: very limited protection against reading/writing past the end of ROM/RAM (todo: should mirror) - SMS: VDP background HSCROLL subtracts, rather than adds, to the offset (unlike VSCROLL) - SMS: VDP VSCROLL is 9-bit, modulates voffset+vscroll to 224 in 192-line mode (32x28 tilemap) - SMS: VDP tiledata for backgrounds and sprites use `7-(x&7)` rather than `(x&7)` - SMS: fix output color to be 6-bit rather than 5-bit - SMS: left clip uses register `#7`, not palette color `#7` - (todo: do we want `color[reg7]` or `color[16 + reg7]`?) - SMS: refined handling of 0xcb, 0xed prefixes in the Z80 core and its disassembler - SMS: emulated (0xfd, 0xdd) 0xcb opcodes 0x00-0x0f (still missing 0x10-0xff) - SMS: fixed 0xcb 0b-----110 opcodes to use direct HL and never allow (IX,IY)+d - SMS: fixed major logic bug in (IX,IY)+d displacement - (was using `read(x)` instead of `operand()` for the displacement byte fetch before) - icarus: fake there always being 32KiB of RAM in all SMS cartridges for the time being - (not sure how to detect this stuff yet; although I've read it's not even really possible `>_>`) TODO: remove processor/z80/dissassembler.cpp code block at line 396 (as it's unnecessary.) Lots of commercial games are starting to show trashed graphical output now.
2017-01-06 08:11:38 +00:00
code = bus->read(pc++);
output = disassembleCBd(pc, prefix, d, code);
} else if(code == 0xcb) {
code = bus->read(pc++);
output = disassembleCB(pc, prefix, code);
} else if(code == 0xed) {
code = bus->read(pc++);
output = disassembleED(pc, prefix, code);
} else {
output = disassemble(pc, prefix, code);
}
s.append(pad(output, -18L, ' '));
Update to v101r16 release. byuu says: Changelog: - Z80: implemented 113 new instructions (all the easy LD/ADC/ADD/AND/OR/SBC/SUB/XOR ones) - Z80: used alternative to castable<To, With> type (manual cast inside instruction() register macros) - Z80: debugger: used register macros to reduce typing and increase readability - Z80: debugger: smarter way of handling multiple DD/FD prefixes (using gotos, yay!) - ruby: fixed crash with Windows input driver on exit (from SuperMikeMan) I have no idea how the P/V flag is supposed to work on AND/OR/XOR, so that's probably wrong for now. HALT is also mostly a dummy function for now. But I typically implement those inside instruction(), so it probably won't need to be changed? We'll see.
2016-09-06 00:09:33 +00:00
finish:
Update to v101r17 release. byuu says: Changelog: - Z80: added most opcodes between 0x00 and 0x3f (two or three hard ones missing still) - Z80: redid register declaration *again* to handle AF', BC', DE', HL' (ugggggh, the fuck? Alternate registers??) - basically, using `#define <register name>` values to get around horrendously awful naming syntax - Z80: improved handling of displace() so that it won't ever trigger on (BC) or (DE)
2016-09-06 13:53:14 +00:00
s.append(" AF:", hex(r.af.word, 4L));
s.append(" BC:", hex(r.bc.word, 4L));
s.append(" DE:", hex(r.de.word, 4L));
s.append(" HL:", hex(r.hl.word, 4L));
s.append(" IX:", hex(r.ix.word, 4L));
s.append(" IY:", hex(r.iy.word, 4L));
Update to v101r14 release. byuu says: Changelog: - rewrote the Z80 core to properly handle 0xDD (IX0 and 0xFD (IY) prefixes - added Processor::Z80::Bus as a new type of abstraction - all of the instructions implemented have their proper T-cycle counts now - added nall/certificates for my public keys The goal of `Processor::Z80::Bus` is to simulate the opcode fetches being 2-read + 2-wait states; operand+regular reads/writes being 3-read. For now, this puts the cycle counts inside the CPU core. At the moment, I can't think of any CPU core where this wouldn't be appropriate. But it's certainly possible that such a case exists. So this may not be the perfect solution. The reason for having it be a subclass of Processor::Z80 instead of virtual functions for the MasterSystem::CPU core to define is due to naming conflicts. I wanted the core to say `in(addr)` and have it take the four clocks. But I also wanted a version of the function that didn't consume time when called. One way to do that would be for the core to call `Z80::in(addr)`, which then calls the regular `in(addr)` that goes to `MasterSystem::CPU::in(addr)`. But I don't want to put the `Z80::` prefix on all of the opcodes. Very easy to forget it, and then end up not consuming any time. Another is to use uglier names in the `MasterSystem::CPU` core, like `read_`, `write_`, `in_`, `out_`, etc. But, yuck. So ... yeah, this is an experiment. We'll see how it goes.
2016-09-03 11:26:04 +00:00
s.append(" SP:", hex(r.sp, 4L));
Update to v101r13 release. byuu says: Changelog: - MS: added ms/bus - Z80: implemented JP/JR/CP/DI/IM/IN instructions - MD/VDP: added window layer emulation - MD/controller/gamepad: fixed d2,d3 bits (Altered Beast requires this) The Z80 is definitely a lot nastier than the LR35902. There's a lot of table duplication with HL→IX→IY; and two of them nest two levels deep (eg FD CB xx xx), so the design may change as I implement more.
2016-08-27 04:48:21 +00:00
Update to v101r14 release. byuu says: Changelog: - rewrote the Z80 core to properly handle 0xDD (IX0 and 0xFD (IY) prefixes - added Processor::Z80::Bus as a new type of abstraction - all of the instructions implemented have their proper T-cycle counts now - added nall/certificates for my public keys The goal of `Processor::Z80::Bus` is to simulate the opcode fetches being 2-read + 2-wait states; operand+regular reads/writes being 3-read. For now, this puts the cycle counts inside the CPU core. At the moment, I can't think of any CPU core where this wouldn't be appropriate. But it's certainly possible that such a case exists. So this may not be the perfect solution. The reason for having it be a subclass of Processor::Z80 instead of virtual functions for the MasterSystem::CPU core to define is due to naming conflicts. I wanted the core to say `in(addr)` and have it take the four clocks. But I also wanted a version of the function that didn't consume time when called. One way to do that would be for the core to call `Z80::in(addr)`, which then calls the regular `in(addr)` that goes to `MasterSystem::CPU::in(addr)`. But I don't want to put the `Z80::` prefix on all of the opcodes. Very easy to forget it, and then end up not consuming any time. Another is to use uglier names in the `MasterSystem::CPU` core, like `read_`, `write_`, `in_`, `out_`, etc. But, yuck. So ... yeah, this is an experiment. We'll see how it goes.
2016-09-03 11:26:04 +00:00
return s;
Update to v101r13 release. byuu says: Changelog: - MS: added ms/bus - Z80: implemented JP/JR/CP/DI/IM/IN instructions - MD/VDP: added window layer emulation - MD/controller/gamepad: fixed d2,d3 bits (Altered Beast requires this) The Z80 is definitely a lot nastier than the LR35902. There's a lot of table duplication with HL→IX→IY; and two of them nest two levels deep (eg FD CB xx xx), so the design may change as I implement more.
2016-08-27 04:48:21 +00:00
}
Update to v101r15 release. byuu says: Changelog: - added (poorly-named) castable<To, With> template - Z80 debugger rewritten to make declaring instructions much simpler - Z80 has more instructions implemented; supports displacement on (IX), (IY) now - added `Processor::M68K::Bus` to mirror `Processor::Z80::Bus` - it does add a pointer indirection; so I'm not sure if I want to do this for all of my emulator cores ...
2016-09-04 13:51:27 +00:00
#define op(id, name, ...) case id: return {name, " ", string_vector{__VA_ARGS__}.merge(",")};
#define N string{"$", hex(byte(), 2L)}
#define IN string{"(", N, ")"}
#define NN string{"$", hex(word(), 4L)}
#define INN string{"(", NN, ")"}
Update to v101r22 release. byuu says: Changelog: - Z80: all 25 remaining instructions implemented Now onto the debugging ... :/
2016-11-01 11:42:25 +00:00
#define REL string{"$", hex(branch(), 4L)}
Update to v101r16 release. byuu says: Changelog: - Z80: implemented 113 new instructions (all the easy LD/ADC/ADD/AND/OR/SBC/SUB/XOR ones) - Z80: used alternative to castable<To, With> type (manual cast inside instruction() register macros) - Z80: debugger: used register macros to reduce typing and increase readability - Z80: debugger: smarter way of handling multiple DD/FD prefixes (using gotos, yay!) - ruby: fixed crash with Windows input driver on exit (from SuperMikeMan) I have no idea how the P/V flag is supposed to work on AND/OR/XOR, so that's probably wrong for now. HALT is also mostly a dummy function for now. But I typically implement those inside instruction(), so it probably won't need to be changed? We'll see.
2016-09-06 00:09:33 +00:00
#define A "a"
#define F "f"
#define B "b"
#define C "c"
#define D "d"
#define E "e"
#define H prefix == 0xdd ? "ixh" : prefix == 0xfd ? "iyh" : "h"
#define L prefix == 0xdd ? "ixl" : prefix == 0xfd ? "iyl" : "l"
Update to v101r17 release. byuu says: Changelog: - Z80: added most opcodes between 0x00 and 0x3f (two or three hard ones missing still) - Z80: redid register declaration *again* to handle AF', BC', DE', HL' (ugggggh, the fuck? Alternate registers??) - basically, using `#define <register name>` values to get around horrendously awful naming syntax - Z80: improved handling of displace() so that it won't ever trigger on (BC) or (DE)
2016-09-06 13:53:14 +00:00
#define _H "h"
#define _L "l"
#define _HL "hl"
Update to v101r16 release. byuu says: Changelog: - Z80: implemented 113 new instructions (all the easy LD/ADC/ADD/AND/OR/SBC/SUB/XOR ones) - Z80: used alternative to castable<To, With> type (manual cast inside instruction() register macros) - Z80: debugger: used register macros to reduce typing and increase readability - Z80: debugger: smarter way of handling multiple DD/FD prefixes (using gotos, yay!) - ruby: fixed crash with Windows input driver on exit (from SuperMikeMan) I have no idea how the P/V flag is supposed to work on AND/OR/XOR, so that's probably wrong for now. HALT is also mostly a dummy function for now. But I typically implement those inside instruction(), so it probably won't need to be changed? We'll see.
2016-09-06 00:09:33 +00:00
#define AF "af"
#define BC "bc"
#define DE "de"
#define HL prefix == 0xdd ? "ix" : prefix == 0xfd ? "iy" : "hl"
Update to v101r17 release. byuu says: Changelog: - Z80: added most opcodes between 0x00 and 0x3f (two or three hard ones missing still) - Z80: redid register declaration *again* to handle AF', BC', DE', HL' (ugggggh, the fuck? Alternate registers??) - basically, using `#define <register name>` values to get around horrendously awful naming syntax - Z80: improved handling of displace() so that it won't ever trigger on (BC) or (DE)
2016-09-06 13:53:14 +00:00
#define AF_ "af'"
#define BC_ "bc'"
#define DE_ "de'"
#define HL_ "hl'"
Update to v101r16 release. byuu says: Changelog: - Z80: implemented 113 new instructions (all the easy LD/ADC/ADD/AND/OR/SBC/SUB/XOR ones) - Z80: used alternative to castable<To, With> type (manual cast inside instruction() register macros) - Z80: debugger: used register macros to reduce typing and increase readability - Z80: debugger: smarter way of handling multiple DD/FD prefixes (using gotos, yay!) - ruby: fixed crash with Windows input driver on exit (from SuperMikeMan) I have no idea how the P/V flag is supposed to work on AND/OR/XOR, so that's probably wrong for now. HALT is also mostly a dummy function for now. But I typically implement those inside instruction(), so it probably won't need to be changed? We'll see.
2016-09-06 00:09:33 +00:00
#define SP "sp"
Update to v101r17 release. byuu says: Changelog: - Z80: added most opcodes between 0x00 and 0x3f (two or three hard ones missing still) - Z80: redid register declaration *again* to handle AF', BC', DE', HL' (ugggggh, the fuck? Alternate registers??) - basically, using `#define <register name>` values to get around horrendously awful naming syntax - Z80: improved handling of displace() so that it won't ever trigger on (BC) or (DE)
2016-09-06 13:53:14 +00:00
#define PC "pc"
Update to v101r15 release. byuu says: Changelog: - added (poorly-named) castable<To, With> template - Z80 debugger rewritten to make declaring instructions much simpler - Z80 has more instructions implemented; supports displacement on (IX), (IY) now - added `Processor::M68K::Bus` to mirror `Processor::Z80::Bus` - it does add a pointer indirection; so I'm not sure if I want to do this for all of my emulator cores ...
2016-09-04 13:51:27 +00:00
Update to v101r22 release. byuu says: Changelog: - Z80: all 25 remaining instructions implemented Now onto the debugging ... :/
2016-11-01 11:42:25 +00:00
#define I "i"
#define R "r"
Update to v101r21 release. byuu says: Changelog: - Z80: emulated 83 new instructions - Z80: timing improvements DAA is a skeleton implementation to complete the normal opcode set. Also worth noting that I don't know exactly what the hell RETI is doing, so for now it acts like RET. RETN probably needs some special handling besides just setting IFF1=IFF2 as well. I'm now missing 24 ED-prefix instructions, plus DAA, for a total of 25 opcodes remaining. And then, of course, several weeks worth of debugging all of the inevitable bugs in the core.
2016-10-31 21:10:33 +00:00
#define IC "(c)"
Update to v101r17 release. byuu says: Changelog: - Z80: added most opcodes between 0x00 and 0x3f (two or three hard ones missing still) - Z80: redid register declaration *again* to handle AF', BC', DE', HL' (ugggggh, the fuck? Alternate registers??) - basically, using `#define <register name>` values to get around horrendously awful naming syntax - Z80: improved handling of displace() so that it won't ever trigger on (BC) or (DE)
2016-09-06 13:53:14 +00:00
#define IBC "(bc)"
#define IDE "(de)"
Update to v101r15 release. byuu says: Changelog: - added (poorly-named) castable<To, With> template - Z80 debugger rewritten to make declaring instructions much simpler - Z80 has more instructions implemented; supports displacement on (IX), (IY) now - added `Processor::M68K::Bus` to mirror `Processor::Z80::Bus` - it does add a pointer indirection; so I'm not sure if I want to do this for all of my emulator cores ...
2016-09-04 13:51:27 +00:00
#define IHL string{"(", HL, displace(), ")"}
Update to v101r17 release. byuu says: Changelog: - Z80: added most opcodes between 0x00 and 0x3f (two or three hard ones missing still) - Z80: redid register declaration *again* to handle AF', BC', DE', HL' (ugggggh, the fuck? Alternate registers??) - basically, using `#define <register name>` values to get around horrendously awful naming syntax - Z80: improved handling of displace() so that it won't ever trigger on (BC) or (DE)
2016-09-06 13:53:14 +00:00
#define ISP "(sp)"
Update to v101r14 release. byuu says: Changelog: - rewrote the Z80 core to properly handle 0xDD (IX0 and 0xFD (IY) prefixes - added Processor::Z80::Bus as a new type of abstraction - all of the instructions implemented have their proper T-cycle counts now - added nall/certificates for my public keys The goal of `Processor::Z80::Bus` is to simulate the opcode fetches being 2-read + 2-wait states; operand+regular reads/writes being 3-read. For now, this puts the cycle counts inside the CPU core. At the moment, I can't think of any CPU core where this wouldn't be appropriate. But it's certainly possible that such a case exists. So this may not be the perfect solution. The reason for having it be a subclass of Processor::Z80 instead of virtual functions for the MasterSystem::CPU core to define is due to naming conflicts. I wanted the core to say `in(addr)` and have it take the four clocks. But I also wanted a version of the function that didn't consume time when called. One way to do that would be for the core to call `Z80::in(addr)`, which then calls the regular `in(addr)` that goes to `MasterSystem::CPU::in(addr)`. But I don't want to put the `Z80::` prefix on all of the opcodes. Very easy to forget it, and then end up not consuming any time. Another is to use uglier names in the `MasterSystem::CPU` core, like `read_`, `write_`, `in_`, `out_`, etc. But, yuck. So ... yeah, this is an experiment. We'll see how it goes.
2016-09-03 11:26:04 +00:00
Update to v101r27 release. byuu says: Changelog: - SMS: emulated the generic Sega memory mapper (none of the more limited forms of it yet) - (missing ROM shift, ROM write enable emulation -- no commercial games use either, though) - SMS: bus I/O returns 0xff instead of 0x00 so games don't think every key is being pressed at once - (this is a hack until I implement proper controller pad reading) - SMS: very limited protection against reading/writing past the end of ROM/RAM (todo: should mirror) - SMS: VDP background HSCROLL subtracts, rather than adds, to the offset (unlike VSCROLL) - SMS: VDP VSCROLL is 9-bit, modulates voffset+vscroll to 224 in 192-line mode (32x28 tilemap) - SMS: VDP tiledata for backgrounds and sprites use `7-(x&7)` rather than `(x&7)` - SMS: fix output color to be 6-bit rather than 5-bit - SMS: left clip uses register `#7`, not palette color `#7` - (todo: do we want `color[reg7]` or `color[16 + reg7]`?) - SMS: refined handling of 0xcb, 0xed prefixes in the Z80 core and its disassembler - SMS: emulated (0xfd, 0xdd) 0xcb opcodes 0x00-0x0f (still missing 0x10-0xff) - SMS: fixed 0xcb 0b-----110 opcodes to use direct HL and never allow (IX,IY)+d - SMS: fixed major logic bug in (IX,IY)+d displacement - (was using `read(x)` instead of `operand()` for the displacement byte fetch before) - icarus: fake there always being 32KiB of RAM in all SMS cartridges for the time being - (not sure how to detect this stuff yet; although I've read it's not even really possible `>_>`) TODO: remove processor/z80/dissassembler.cpp code block at line 396 (as it's unnecessary.) Lots of commercial games are starting to show trashed graphical output now.
2017-01-06 08:11:38 +00:00
auto Z80::disassemble(uint16 pc, uint8 prefix, uint8 code) -> string {
Update to v101r15 release. byuu says: Changelog: - added (poorly-named) castable<To, With> template - Z80 debugger rewritten to make declaring instructions much simpler - Z80 has more instructions implemented; supports displacement on (IX), (IY) now - added `Processor::M68K::Bus` to mirror `Processor::Z80::Bus` - it does add a pointer indirection; so I'm not sure if I want to do this for all of my emulator cores ...
2016-09-04 13:51:27 +00:00
auto byte = [&] {
return bus->read(pc++);
};
auto word = [&] {
uint16 data = byte() << 0;
return data | byte() << 8;
};
auto branch = [&] {
auto d = byte();
return pc + (int8)d;
};
auto displace = [&] {
if(!prefix) return string{};
auto d = (int8)byte();
return d >= 0 ? string{"+$", hex(d, 2L)} : string{"-$", hex(-d, 2L)};
};
Update to v101r14 release. byuu says: Changelog: - rewrote the Z80 core to properly handle 0xDD (IX0 and 0xFD (IY) prefixes - added Processor::Z80::Bus as a new type of abstraction - all of the instructions implemented have their proper T-cycle counts now - added nall/certificates for my public keys The goal of `Processor::Z80::Bus` is to simulate the opcode fetches being 2-read + 2-wait states; operand+regular reads/writes being 3-read. For now, this puts the cycle counts inside the CPU core. At the moment, I can't think of any CPU core where this wouldn't be appropriate. But it's certainly possible that such a case exists. So this may not be the perfect solution. The reason for having it be a subclass of Processor::Z80 instead of virtual functions for the MasterSystem::CPU core to define is due to naming conflicts. I wanted the core to say `in(addr)` and have it take the four clocks. But I also wanted a version of the function that didn't consume time when called. One way to do that would be for the core to call `Z80::in(addr)`, which then calls the regular `in(addr)` that goes to `MasterSystem::CPU::in(addr)`. But I don't want to put the `Z80::` prefix on all of the opcodes. Very easy to forget it, and then end up not consuming any time. Another is to use uglier names in the `MasterSystem::CPU` core, like `read_`, `write_`, `in_`, `out_`, etc. But, yuck. So ... yeah, this is an experiment. We'll see how it goes.
2016-09-03 11:26:04 +00:00
switch(code) {
Update to v101r15 release. byuu says: Changelog: - added (poorly-named) castable<To, With> template - Z80 debugger rewritten to make declaring instructions much simpler - Z80 has more instructions implemented; supports displacement on (IX), (IY) now - added `Processor::M68K::Bus` to mirror `Processor::Z80::Bus` - it does add a pointer indirection; so I'm not sure if I want to do this for all of my emulator cores ...
2016-09-04 13:51:27 +00:00
op(0x00, "nop ")
Update to v101r16 release. byuu says: Changelog: - Z80: implemented 113 new instructions (all the easy LD/ADC/ADD/AND/OR/SBC/SUB/XOR ones) - Z80: used alternative to castable<To, With> type (manual cast inside instruction() register macros) - Z80: debugger: used register macros to reduce typing and increase readability - Z80: debugger: smarter way of handling multiple DD/FD prefixes (using gotos, yay!) - ruby: fixed crash with Windows input driver on exit (from SuperMikeMan) I have no idea how the P/V flag is supposed to work on AND/OR/XOR, so that's probably wrong for now. HALT is also mostly a dummy function for now. But I typically implement those inside instruction(), so it probably won't need to be changed? We'll see.
2016-09-06 00:09:33 +00:00
op(0x01, "ld ", BC, NN)
Update to v101r17 release. byuu says: Changelog: - Z80: added most opcodes between 0x00 and 0x3f (two or three hard ones missing still) - Z80: redid register declaration *again* to handle AF', BC', DE', HL' (ugggggh, the fuck? Alternate registers??) - basically, using `#define <register name>` values to get around horrendously awful naming syntax - Z80: improved handling of displace() so that it won't ever trigger on (BC) or (DE)
2016-09-06 13:53:14 +00:00
op(0x02, "ld ", IBC, A)
op(0x03, "inc ", BC)
op(0x04, "inc ", B)
op(0x05, "dec ", B)
Update to v101r16 release. byuu says: Changelog: - Z80: implemented 113 new instructions (all the easy LD/ADC/ADD/AND/OR/SBC/SUB/XOR ones) - Z80: used alternative to castable<To, With> type (manual cast inside instruction() register macros) - Z80: debugger: used register macros to reduce typing and increase readability - Z80: debugger: smarter way of handling multiple DD/FD prefixes (using gotos, yay!) - ruby: fixed crash with Windows input driver on exit (from SuperMikeMan) I have no idea how the P/V flag is supposed to work on AND/OR/XOR, so that's probably wrong for now. HALT is also mostly a dummy function for now. But I typically implement those inside instruction(), so it probably won't need to be changed? We'll see.
2016-09-06 00:09:33 +00:00
op(0x06, "ld ", B, N)
Update to v101r17 release. byuu says: Changelog: - Z80: added most opcodes between 0x00 and 0x3f (two or three hard ones missing still) - Z80: redid register declaration *again* to handle AF', BC', DE', HL' (ugggggh, the fuck? Alternate registers??) - basically, using `#define <register name>` values to get around horrendously awful naming syntax - Z80: improved handling of displace() so that it won't ever trigger on (BC) or (DE)
2016-09-06 13:53:14 +00:00
op(0x07, "rlca")
op(0x08, "ex ", AF, AF_)
op(0x09, "add ", HL, BC)
op(0x0a, "ld ", A, IBC)
op(0x0b, "dec ", BC)
op(0x0c, "inc ", C)
op(0x0d, "dec ", C)
Update to v101r16 release. byuu says: Changelog: - Z80: implemented 113 new instructions (all the easy LD/ADC/ADD/AND/OR/SBC/SUB/XOR ones) - Z80: used alternative to castable<To, With> type (manual cast inside instruction() register macros) - Z80: debugger: used register macros to reduce typing and increase readability - Z80: debugger: smarter way of handling multiple DD/FD prefixes (using gotos, yay!) - ruby: fixed crash with Windows input driver on exit (from SuperMikeMan) I have no idea how the P/V flag is supposed to work on AND/OR/XOR, so that's probably wrong for now. HALT is also mostly a dummy function for now. But I typically implement those inside instruction(), so it probably won't need to be changed? We'll see.
2016-09-06 00:09:33 +00:00
op(0x0e, "ld ", C, N)
Update to v101r17 release. byuu says: Changelog: - Z80: added most opcodes between 0x00 and 0x3f (two or three hard ones missing still) - Z80: redid register declaration *again* to handle AF', BC', DE', HL' (ugggggh, the fuck? Alternate registers??) - basically, using `#define <register name>` values to get around horrendously awful naming syntax - Z80: improved handling of displace() so that it won't ever trigger on (BC) or (DE)
2016-09-06 13:53:14 +00:00
op(0x0f, "rrca")
Update to v101r22 release. byuu says: Changelog: - Z80: all 25 remaining instructions implemented Now onto the debugging ... :/
2016-11-01 11:42:25 +00:00
op(0x10, "djnz", REL)
Update to v101r16 release. byuu says: Changelog: - Z80: implemented 113 new instructions (all the easy LD/ADC/ADD/AND/OR/SBC/SUB/XOR ones) - Z80: used alternative to castable<To, With> type (manual cast inside instruction() register macros) - Z80: debugger: used register macros to reduce typing and increase readability - Z80: debugger: smarter way of handling multiple DD/FD prefixes (using gotos, yay!) - ruby: fixed crash with Windows input driver on exit (from SuperMikeMan) I have no idea how the P/V flag is supposed to work on AND/OR/XOR, so that's probably wrong for now. HALT is also mostly a dummy function for now. But I typically implement those inside instruction(), so it probably won't need to be changed? We'll see.
2016-09-06 00:09:33 +00:00
op(0x11, "ld ", DE, NN)
Update to v101r17 release. byuu says: Changelog: - Z80: added most opcodes between 0x00 and 0x3f (two or three hard ones missing still) - Z80: redid register declaration *again* to handle AF', BC', DE', HL' (ugggggh, the fuck? Alternate registers??) - basically, using `#define <register name>` values to get around horrendously awful naming syntax - Z80: improved handling of displace() so that it won't ever trigger on (BC) or (DE)
2016-09-06 13:53:14 +00:00
op(0x12, "ld ", IDE, A)
op(0x13, "inc ", DE)
op(0x14, "inc ", D)
op(0x15, "dec ", D)
Update to v101r16 release. byuu says: Changelog: - Z80: implemented 113 new instructions (all the easy LD/ADC/ADD/AND/OR/SBC/SUB/XOR ones) - Z80: used alternative to castable<To, With> type (manual cast inside instruction() register macros) - Z80: debugger: used register macros to reduce typing and increase readability - Z80: debugger: smarter way of handling multiple DD/FD prefixes (using gotos, yay!) - ruby: fixed crash with Windows input driver on exit (from SuperMikeMan) I have no idea how the P/V flag is supposed to work on AND/OR/XOR, so that's probably wrong for now. HALT is also mostly a dummy function for now. But I typically implement those inside instruction(), so it probably won't need to be changed? We'll see.
2016-09-06 00:09:33 +00:00
op(0x16, "ld ", E, N)
Update to v101r17 release. byuu says: Changelog: - Z80: added most opcodes between 0x00 and 0x3f (two or three hard ones missing still) - Z80: redid register declaration *again* to handle AF', BC', DE', HL' (ugggggh, the fuck? Alternate registers??) - basically, using `#define <register name>` values to get around horrendously awful naming syntax - Z80: improved handling of displace() so that it won't ever trigger on (BC) or (DE)
2016-09-06 13:53:14 +00:00
op(0x17, "rla ")
Update to v101r22 release. byuu says: Changelog: - Z80: all 25 remaining instructions implemented Now onto the debugging ... :/
2016-11-01 11:42:25 +00:00
op(0x18, "jr ", REL)
Update to v101r17 release. byuu says: Changelog: - Z80: added most opcodes between 0x00 and 0x3f (two or three hard ones missing still) - Z80: redid register declaration *again* to handle AF', BC', DE', HL' (ugggggh, the fuck? Alternate registers??) - basically, using `#define <register name>` values to get around horrendously awful naming syntax - Z80: improved handling of displace() so that it won't ever trigger on (BC) or (DE)
2016-09-06 13:53:14 +00:00
op(0x19, "add ", HL, DE)
op(0x1a, "ld ", A, IDE)
op(0x1b, "dec ", DE)
op(0x1c, "inc ", E)
op(0x1d, "dec ", E)
Update to v101r16 release. byuu says: Changelog: - Z80: implemented 113 new instructions (all the easy LD/ADC/ADD/AND/OR/SBC/SUB/XOR ones) - Z80: used alternative to castable<To, With> type (manual cast inside instruction() register macros) - Z80: debugger: used register macros to reduce typing and increase readability - Z80: debugger: smarter way of handling multiple DD/FD prefixes (using gotos, yay!) - ruby: fixed crash with Windows input driver on exit (from SuperMikeMan) I have no idea how the P/V flag is supposed to work on AND/OR/XOR, so that's probably wrong for now. HALT is also mostly a dummy function for now. But I typically implement those inside instruction(), so it probably won't need to be changed? We'll see.
2016-09-06 00:09:33 +00:00
op(0x1e, "ld ", E, N)
Update to v101r17 release. byuu says: Changelog: - Z80: added most opcodes between 0x00 and 0x3f (two or three hard ones missing still) - Z80: redid register declaration *again* to handle AF', BC', DE', HL' (ugggggh, the fuck? Alternate registers??) - basically, using `#define <register name>` values to get around horrendously awful naming syntax - Z80: improved handling of displace() so that it won't ever trigger on (BC) or (DE)
2016-09-06 13:53:14 +00:00
op(0x1f, "rra ")
Update to v101r22 release. byuu says: Changelog: - Z80: all 25 remaining instructions implemented Now onto the debugging ... :/
2016-11-01 11:42:25 +00:00
op(0x20, "jr ", "nz", REL)
Update to v101r15 release. byuu says: Changelog: - added (poorly-named) castable<To, With> template - Z80 debugger rewritten to make declaring instructions much simpler - Z80 has more instructions implemented; supports displacement on (IX), (IY) now - added `Processor::M68K::Bus` to mirror `Processor::Z80::Bus` - it does add a pointer indirection; so I'm not sure if I want to do this for all of my emulator cores ...
2016-09-04 13:51:27 +00:00
op(0x21, "ld ", HL, NN)
Update to v101r17 release. byuu says: Changelog: - Z80: added most opcodes between 0x00 and 0x3f (two or three hard ones missing still) - Z80: redid register declaration *again* to handle AF', BC', DE', HL' (ugggggh, the fuck? Alternate registers??) - basically, using `#define <register name>` values to get around horrendously awful naming syntax - Z80: improved handling of displace() so that it won't ever trigger on (BC) or (DE)
2016-09-06 13:53:14 +00:00
op(0x22, "ld ", INN, HL)
op(0x23, "inc ", HL)
op(0x24, "inc ", H)
op(0x25, "dec ", H)
Update to v101r15 release. byuu says: Changelog: - added (poorly-named) castable<To, With> template - Z80 debugger rewritten to make declaring instructions much simpler - Z80 has more instructions implemented; supports displacement on (IX), (IY) now - added `Processor::M68K::Bus` to mirror `Processor::Z80::Bus` - it does add a pointer indirection; so I'm not sure if I want to do this for all of my emulator cores ...
2016-09-04 13:51:27 +00:00
op(0x26, "ld ", H, N)
Update to v101r21 release. byuu says: Changelog: - Z80: emulated 83 new instructions - Z80: timing improvements DAA is a skeleton implementation to complete the normal opcode set. Also worth noting that I don't know exactly what the hell RETI is doing, so for now it acts like RET. RETN probably needs some special handling besides just setting IFF1=IFF2 as well. I'm now missing 24 ED-prefix instructions, plus DAA, for a total of 25 opcodes remaining. And then, of course, several weeks worth of debugging all of the inevitable bugs in the core.
2016-10-31 21:10:33 +00:00
op(0x27, "daa ")
Update to v101r22 release. byuu says: Changelog: - Z80: all 25 remaining instructions implemented Now onto the debugging ... :/
2016-11-01 11:42:25 +00:00
op(0x28, "jr ", "z", REL)
Update to v101r17 release. byuu says: Changelog: - Z80: added most opcodes between 0x00 and 0x3f (two or three hard ones missing still) - Z80: redid register declaration *again* to handle AF', BC', DE', HL' (ugggggh, the fuck? Alternate registers??) - basically, using `#define <register name>` values to get around horrendously awful naming syntax - Z80: improved handling of displace() so that it won't ever trigger on (BC) or (DE)
2016-09-06 13:53:14 +00:00
op(0x29, "add ", HL, HL)
op(0x2a, "ld ", HL, INN)
op(0x2b, "dec ", HL)
op(0x2c, "inc ", L)
op(0x2d, "dec ", L)
Update to v101r15 release. byuu says: Changelog: - added (poorly-named) castable<To, With> template - Z80 debugger rewritten to make declaring instructions much simpler - Z80 has more instructions implemented; supports displacement on (IX), (IY) now - added `Processor::M68K::Bus` to mirror `Processor::Z80::Bus` - it does add a pointer indirection; so I'm not sure if I want to do this for all of my emulator cores ...
2016-09-04 13:51:27 +00:00
op(0x2e, "ld ", L, N)
Update to v101r17 release. byuu says: Changelog: - Z80: added most opcodes between 0x00 and 0x3f (two or three hard ones missing still) - Z80: redid register declaration *again* to handle AF', BC', DE', HL' (ugggggh, the fuck? Alternate registers??) - basically, using `#define <register name>` values to get around horrendously awful naming syntax - Z80: improved handling of displace() so that it won't ever trigger on (BC) or (DE)
2016-09-06 13:53:14 +00:00
op(0x2f, "cpl ")
Update to v101r22 release. byuu says: Changelog: - Z80: all 25 remaining instructions implemented Now onto the debugging ... :/
2016-11-01 11:42:25 +00:00
op(0x30, "jr ", "nc", REL)
Update to v101r16 release. byuu says: Changelog: - Z80: implemented 113 new instructions (all the easy LD/ADC/ADD/AND/OR/SBC/SUB/XOR ones) - Z80: used alternative to castable<To, With> type (manual cast inside instruction() register macros) - Z80: debugger: used register macros to reduce typing and increase readability - Z80: debugger: smarter way of handling multiple DD/FD prefixes (using gotos, yay!) - ruby: fixed crash with Windows input driver on exit (from SuperMikeMan) I have no idea how the P/V flag is supposed to work on AND/OR/XOR, so that's probably wrong for now. HALT is also mostly a dummy function for now. But I typically implement those inside instruction(), so it probably won't need to be changed? We'll see.
2016-09-06 00:09:33 +00:00
op(0x31, "ld ", SP, NN)
op(0x32, "ld ", INN, A)
Update to v101r17 release. byuu says: Changelog: - Z80: added most opcodes between 0x00 and 0x3f (two or three hard ones missing still) - Z80: redid register declaration *again* to handle AF', BC', DE', HL' (ugggggh, the fuck? Alternate registers??) - basically, using `#define <register name>` values to get around horrendously awful naming syntax - Z80: improved handling of displace() so that it won't ever trigger on (BC) or (DE)
2016-09-06 13:53:14 +00:00
op(0x33, "inc ", SP)
op(0x34, "inc ", IHL)
op(0x35, "dec ", IHL)
Update to v101r15 release. byuu says: Changelog: - added (poorly-named) castable<To, With> template - Z80 debugger rewritten to make declaring instructions much simpler - Z80 has more instructions implemented; supports displacement on (IX), (IY) now - added `Processor::M68K::Bus` to mirror `Processor::Z80::Bus` - it does add a pointer indirection; so I'm not sure if I want to do this for all of my emulator cores ...
2016-09-04 13:51:27 +00:00
op(0x36, "ld ", IHL, N)
Update to v101r17 release. byuu says: Changelog: - Z80: added most opcodes between 0x00 and 0x3f (two or three hard ones missing still) - Z80: redid register declaration *again* to handle AF', BC', DE', HL' (ugggggh, the fuck? Alternate registers??) - basically, using `#define <register name>` values to get around horrendously awful naming syntax - Z80: improved handling of displace() so that it won't ever trigger on (BC) or (DE)
2016-09-06 13:53:14 +00:00
op(0x37, "scf ")
Update to v101r22 release. byuu says: Changelog: - Z80: all 25 remaining instructions implemented Now onto the debugging ... :/
2016-11-01 11:42:25 +00:00
op(0x38, "jr ", "c", REL)
Update to v101r17 release. byuu says: Changelog: - Z80: added most opcodes between 0x00 and 0x3f (two or three hard ones missing still) - Z80: redid register declaration *again* to handle AF', BC', DE', HL' (ugggggh, the fuck? Alternate registers??) - basically, using `#define <register name>` values to get around horrendously awful naming syntax - Z80: improved handling of displace() so that it won't ever trigger on (BC) or (DE)
2016-09-06 13:53:14 +00:00
op(0x39, "add ", HL, SP)
op(0x3a, "ld ", A, INN)
op(0x3b, "dec ", SP)
op(0x3c, "inc ", A)
op(0x3d, "dec ", A)
Update to v101r16 release. byuu says: Changelog: - Z80: implemented 113 new instructions (all the easy LD/ADC/ADD/AND/OR/SBC/SUB/XOR ones) - Z80: used alternative to castable<To, With> type (manual cast inside instruction() register macros) - Z80: debugger: used register macros to reduce typing and increase readability - Z80: debugger: smarter way of handling multiple DD/FD prefixes (using gotos, yay!) - ruby: fixed crash with Windows input driver on exit (from SuperMikeMan) I have no idea how the P/V flag is supposed to work on AND/OR/XOR, so that's probably wrong for now. HALT is also mostly a dummy function for now. But I typically implement those inside instruction(), so it probably won't need to be changed? We'll see.
2016-09-06 00:09:33 +00:00
op(0x3e, "ld ", A, N)
Update to v101r17 release. byuu says: Changelog: - Z80: added most opcodes between 0x00 and 0x3f (two or three hard ones missing still) - Z80: redid register declaration *again* to handle AF', BC', DE', HL' (ugggggh, the fuck? Alternate registers??) - basically, using `#define <register name>` values to get around horrendously awful naming syntax - Z80: improved handling of displace() so that it won't ever trigger on (BC) or (DE)
2016-09-06 13:53:14 +00:00
op(0x3f, "ccf ")
Update to v101r16 release. byuu says: Changelog: - Z80: implemented 113 new instructions (all the easy LD/ADC/ADD/AND/OR/SBC/SUB/XOR ones) - Z80: used alternative to castable<To, With> type (manual cast inside instruction() register macros) - Z80: debugger: used register macros to reduce typing and increase readability - Z80: debugger: smarter way of handling multiple DD/FD prefixes (using gotos, yay!) - ruby: fixed crash with Windows input driver on exit (from SuperMikeMan) I have no idea how the P/V flag is supposed to work on AND/OR/XOR, so that's probably wrong for now. HALT is also mostly a dummy function for now. But I typically implement those inside instruction(), so it probably won't need to be changed? We'll see.
2016-09-06 00:09:33 +00:00
op(0x40, "ld ", B, B)
op(0x41, "ld ", B, C)
op(0x42, "ld ", B, D)
op(0x43, "ld ", B, E)
op(0x44, "ld ", B, H)
op(0x45, "ld ", B, L)
op(0x46, "ld ", B, IHL)
op(0x47, "ld ", B, A)
op(0x48, "ld ", C, B)
op(0x49, "ld ", C, C)
op(0x4a, "ld ", C, D)
op(0x4b, "ld ", C, E)
op(0x4c, "ld ", C, H)
op(0x4d, "ld ", C, L)
op(0x4e, "ld ", C, IHL)
op(0x4f, "ld ", C, A)
op(0x50, "ld ", D, B)
op(0x51, "ld ", D, C)
op(0x52, "ld ", D, D)
op(0x53, "ld ", D, E)
op(0x54, "ld ", D, H)
op(0x55, "ld ", D, L)
op(0x56, "ld ", D, IHL)
op(0x57, "ld ", D, A)
op(0x58, "ld ", E, B)
op(0x59, "ld ", E, C)
op(0x5a, "ld ", E, D)
op(0x5b, "ld ", E, E)
op(0x5c, "ld ", E, H)
op(0x5d, "ld ", E, L)
op(0x5e, "ld ", E, IHL)
op(0x5f, "ld ", E, A)
op(0x60, "ld ", H, B)
op(0x61, "ld ", H, C)
op(0x62, "ld ", H, D)
op(0x63, "ld ", H, E)
op(0x64, "ld ", H, H)
op(0x65, "ld ", H, L)
Update to v101r17 release. byuu says: Changelog: - Z80: added most opcodes between 0x00 and 0x3f (two or three hard ones missing still) - Z80: redid register declaration *again* to handle AF', BC', DE', HL' (ugggggh, the fuck? Alternate registers??) - basically, using `#define <register name>` values to get around horrendously awful naming syntax - Z80: improved handling of displace() so that it won't ever trigger on (BC) or (DE)
2016-09-06 13:53:14 +00:00
op(0x66, "ld ", _H, IHL)
Update to v101r16 release. byuu says: Changelog: - Z80: implemented 113 new instructions (all the easy LD/ADC/ADD/AND/OR/SBC/SUB/XOR ones) - Z80: used alternative to castable<To, With> type (manual cast inside instruction() register macros) - Z80: debugger: used register macros to reduce typing and increase readability - Z80: debugger: smarter way of handling multiple DD/FD prefixes (using gotos, yay!) - ruby: fixed crash with Windows input driver on exit (from SuperMikeMan) I have no idea how the P/V flag is supposed to work on AND/OR/XOR, so that's probably wrong for now. HALT is also mostly a dummy function for now. But I typically implement those inside instruction(), so it probably won't need to be changed? We'll see.
2016-09-06 00:09:33 +00:00
op(0x67, "ld ", H, A)
op(0x68, "ld ", L, B)
op(0x69, "ld ", L, C)
op(0x6a, "ld ", L, D)
op(0x6b, "ld ", L, E)
op(0x6c, "ld ", L, H)
op(0x6d, "ld ", L, L)
Update to v101r17 release. byuu says: Changelog: - Z80: added most opcodes between 0x00 and 0x3f (two or three hard ones missing still) - Z80: redid register declaration *again* to handle AF', BC', DE', HL' (ugggggh, the fuck? Alternate registers??) - basically, using `#define <register name>` values to get around horrendously awful naming syntax - Z80: improved handling of displace() so that it won't ever trigger on (BC) or (DE)
2016-09-06 13:53:14 +00:00
op(0x6e, "ld ", _L, IHL)
Update to v101r16 release. byuu says: Changelog: - Z80: implemented 113 new instructions (all the easy LD/ADC/ADD/AND/OR/SBC/SUB/XOR ones) - Z80: used alternative to castable<To, With> type (manual cast inside instruction() register macros) - Z80: debugger: used register macros to reduce typing and increase readability - Z80: debugger: smarter way of handling multiple DD/FD prefixes (using gotos, yay!) - ruby: fixed crash with Windows input driver on exit (from SuperMikeMan) I have no idea how the P/V flag is supposed to work on AND/OR/XOR, so that's probably wrong for now. HALT is also mostly a dummy function for now. But I typically implement those inside instruction(), so it probably won't need to be changed? We'll see.
2016-09-06 00:09:33 +00:00
op(0x6f, "ld ", L, A)
op(0x70, "ld ", IHL, B)
op(0x71, "ld ", IHL, C)
op(0x72, "ld ", IHL, D)
op(0x73, "ld ", IHL, E)
Update to v101r17 release. byuu says: Changelog: - Z80: added most opcodes between 0x00 and 0x3f (two or three hard ones missing still) - Z80: redid register declaration *again* to handle AF', BC', DE', HL' (ugggggh, the fuck? Alternate registers??) - basically, using `#define <register name>` values to get around horrendously awful naming syntax - Z80: improved handling of displace() so that it won't ever trigger on (BC) or (DE)
2016-09-06 13:53:14 +00:00
op(0x74, "ld ", IHL, _H)
op(0x75, "ld ", IHL, _L)
Update to v101r16 release. byuu says: Changelog: - Z80: implemented 113 new instructions (all the easy LD/ADC/ADD/AND/OR/SBC/SUB/XOR ones) - Z80: used alternative to castable<To, With> type (manual cast inside instruction() register macros) - Z80: debugger: used register macros to reduce typing and increase readability - Z80: debugger: smarter way of handling multiple DD/FD prefixes (using gotos, yay!) - ruby: fixed crash with Windows input driver on exit (from SuperMikeMan) I have no idea how the P/V flag is supposed to work on AND/OR/XOR, so that's probably wrong for now. HALT is also mostly a dummy function for now. But I typically implement those inside instruction(), so it probably won't need to be changed? We'll see.
2016-09-06 00:09:33 +00:00
op(0x76, "halt")
op(0x77, "ld ", IHL, A)
op(0x78, "ld ", A, B)
op(0x79, "ld ", A, C)
op(0x7a, "ld ", A, D)
op(0x7b, "ld ", A, E)
op(0x7c, "ld ", A, H)
op(0x7d, "ld ", A, L)
op(0x7e, "ld ", A, IHL)
op(0x7f, "ld ", A, A)
op(0x80, "add ", A, B)
op(0x81, "add ", A, C)
op(0x82, "add ", A, D)
op(0x83, "add ", A, E)
op(0x84, "add ", A, H)
op(0x85, "add ", A, L)
op(0x86, "add ", A, IHL)
op(0x87, "add ", A, A)
op(0x88, "adc ", A, B)
op(0x89, "adc ", A, C)
op(0x8a, "adc ", A, D)
op(0x8b, "adc ", A, E)
op(0x8c, "adc ", A, H)
op(0x8d, "adc ", A, L)
op(0x8e, "adc ", A, IHL)
op(0x8f, "adc ", A, A)
op(0x90, "sub ", A, B)
op(0x91, "sub ", A, C)
op(0x92, "sub ", A, D)
op(0x93, "sub ", A, E)
op(0x94, "sub ", A, H)
op(0x95, "sub ", A, L)
op(0x96, "sub ", A, IHL)
op(0x97, "sub ", A, A)
op(0x98, "sbc ", A, B)
op(0x99, "sbc ", A, C)
op(0x9a, "sbc ", A, D)
op(0x9b, "sbc ", A, E)
op(0x9c, "sbc ", A, H)
op(0x9d, "sbc ", A, L)
op(0x9e, "sbc ", A, IHL)
op(0x9f, "sbc ", A, A)
op(0xa0, "and ", A, B)
op(0xa1, "and ", A, C)
op(0xa2, "and ", A, D)
op(0xa3, "and ", A, E)
op(0xa4, "and ", A, H)
op(0xa5, "and ", A, L)
op(0xa6, "and ", A, IHL)
op(0xa7, "and ", A, A)
op(0xa8, "xor ", A, B)
op(0xa9, "xor ", A, C)
op(0xaa, "xor ", A, D)
op(0xab, "xor ", A, E)
op(0xac, "xor ", A, H)
op(0xad, "xor ", A, L)
op(0xae, "xor ", A, HL)
op(0xaf, "xor ", A, A)
op(0xb0, "or ", A, B)
op(0xb1, "or ", A, C)
op(0xb2, "or ", A, D)
op(0xb3, "or ", A, E)
op(0xb4, "or ", A, H)
op(0xb5, "or ", A, L)
op(0xb6, "or ", A, IHL)
op(0xb7, "or ", A, A)
op(0xb8, "cp ", A, B)
op(0xb9, "cp ", A, C)
op(0xba, "cp ", A, D)
op(0xbb, "cp ", A, E)
op(0xbc, "cp ", A, H)
op(0xbd, "cp ", A, L)
op(0xbe, "cp ", A, IHL)
op(0xbf, "cp ", A, A)
Update to v101r21 release. byuu says: Changelog: - Z80: emulated 83 new instructions - Z80: timing improvements DAA is a skeleton implementation to complete the normal opcode set. Also worth noting that I don't know exactly what the hell RETI is doing, so for now it acts like RET. RETN probably needs some special handling besides just setting IFF1=IFF2 as well. I'm now missing 24 ED-prefix instructions, plus DAA, for a total of 25 opcodes remaining. And then, of course, several weeks worth of debugging all of the inevitable bugs in the core.
2016-10-31 21:10:33 +00:00
op(0xc0, "ret ", "nz")
op(0xc1, "pop ", BC)
Update to v101r15 release. byuu says: Changelog: - added (poorly-named) castable<To, With> template - Z80 debugger rewritten to make declaring instructions much simpler - Z80 has more instructions implemented; supports displacement on (IX), (IY) now - added `Processor::M68K::Bus` to mirror `Processor::Z80::Bus` - it does add a pointer indirection; so I'm not sure if I want to do this for all of my emulator cores ...
2016-09-04 13:51:27 +00:00
op(0xc2, "jp ", "nz", NN)
op(0xc3, "jp ", NN)
Update to v101r21 release. byuu says: Changelog: - Z80: emulated 83 new instructions - Z80: timing improvements DAA is a skeleton implementation to complete the normal opcode set. Also worth noting that I don't know exactly what the hell RETI is doing, so for now it acts like RET. RETN probably needs some special handling besides just setting IFF1=IFF2 as well. I'm now missing 24 ED-prefix instructions, plus DAA, for a total of 25 opcodes remaining. And then, of course, several weeks worth of debugging all of the inevitable bugs in the core.
2016-10-31 21:10:33 +00:00
op(0xc4, "call", "nz", NN)
op(0xc5, "push", BC)
op(0xc6, "add ", A, N)
op(0xc7, "rst ", "0")
op(0xc8, "ret ", "z")
op(0xc9, "ret ")
Update to v101r15 release. byuu says: Changelog: - added (poorly-named) castable<To, With> template - Z80 debugger rewritten to make declaring instructions much simpler - Z80 has more instructions implemented; supports displacement on (IX), (IY) now - added `Processor::M68K::Bus` to mirror `Processor::Z80::Bus` - it does add a pointer indirection; so I'm not sure if I want to do this for all of my emulator cores ...
2016-09-04 13:51:27 +00:00
op(0xca, "jp ", "z", NN)
op(0xcb, "cb: ")
Update to v101r21 release. byuu says: Changelog: - Z80: emulated 83 new instructions - Z80: timing improvements DAA is a skeleton implementation to complete the normal opcode set. Also worth noting that I don't know exactly what the hell RETI is doing, so for now it acts like RET. RETN probably needs some special handling besides just setting IFF1=IFF2 as well. I'm now missing 24 ED-prefix instructions, plus DAA, for a total of 25 opcodes remaining. And then, of course, several weeks worth of debugging all of the inevitable bugs in the core.
2016-10-31 21:10:33 +00:00
op(0xcc, "call", "z", NN)
op(0xcd, "call", NN)
op(0xce, "adc ", A, N)
op(0xcf, "rst ", "1")
op(0xd0, "ret ", "nc")
op(0xd1, "pop ", DE)
Update to v101r15 release. byuu says: Changelog: - added (poorly-named) castable<To, With> template - Z80 debugger rewritten to make declaring instructions much simpler - Z80 has more instructions implemented; supports displacement on (IX), (IY) now - added `Processor::M68K::Bus` to mirror `Processor::Z80::Bus` - it does add a pointer indirection; so I'm not sure if I want to do this for all of my emulator cores ...
2016-09-04 13:51:27 +00:00
op(0xd2, "jp ", "nc", NN)
Update to v101r21 release. byuu says: Changelog: - Z80: emulated 83 new instructions - Z80: timing improvements DAA is a skeleton implementation to complete the normal opcode set. Also worth noting that I don't know exactly what the hell RETI is doing, so for now it acts like RET. RETN probably needs some special handling besides just setting IFF1=IFF2 as well. I'm now missing 24 ED-prefix instructions, plus DAA, for a total of 25 opcodes remaining. And then, of course, several weeks worth of debugging all of the inevitable bugs in the core.
2016-10-31 21:10:33 +00:00
op(0xd3, "out ", IN, A)
op(0xd4, "call", "nc", NN)
op(0xd5, "push", DE)
op(0xd6, "sub ", A, N)
op(0xd7, "rst ", "2")
op(0xd8, "ret ", "c")
op(0xd9, "exx ")
Update to v101r15 release. byuu says: Changelog: - added (poorly-named) castable<To, With> template - Z80 debugger rewritten to make declaring instructions much simpler - Z80 has more instructions implemented; supports displacement on (IX), (IY) now - added `Processor::M68K::Bus` to mirror `Processor::Z80::Bus` - it does add a pointer indirection; so I'm not sure if I want to do this for all of my emulator cores ...
2016-09-04 13:51:27 +00:00
op(0xda, "jp ", "c", NN)
Update to v101r16 release. byuu says: Changelog: - Z80: implemented 113 new instructions (all the easy LD/ADC/ADD/AND/OR/SBC/SUB/XOR ones) - Z80: used alternative to castable<To, With> type (manual cast inside instruction() register macros) - Z80: debugger: used register macros to reduce typing and increase readability - Z80: debugger: smarter way of handling multiple DD/FD prefixes (using gotos, yay!) - ruby: fixed crash with Windows input driver on exit (from SuperMikeMan) I have no idea how the P/V flag is supposed to work on AND/OR/XOR, so that's probably wrong for now. HALT is also mostly a dummy function for now. But I typically implement those inside instruction(), so it probably won't need to be changed? We'll see.
2016-09-06 00:09:33 +00:00
op(0xdb, "in ", A, IN)
Update to v101r21 release. byuu says: Changelog: - Z80: emulated 83 new instructions - Z80: timing improvements DAA is a skeleton implementation to complete the normal opcode set. Also worth noting that I don't know exactly what the hell RETI is doing, so for now it acts like RET. RETN probably needs some special handling besides just setting IFF1=IFF2 as well. I'm now missing 24 ED-prefix instructions, plus DAA, for a total of 25 opcodes remaining. And then, of course, several weeks worth of debugging all of the inevitable bugs in the core.
2016-10-31 21:10:33 +00:00
op(0xdc, "call", "c", NN)
op(0xdd, "ix: ")
op(0xde, "sbc ", A, N)
op(0xdf, "rst ", "3")
op(0xe0, "ret ", "po")
op(0xe1, "pop ", HL)
Update to v101r15 release. byuu says: Changelog: - added (poorly-named) castable<To, With> template - Z80 debugger rewritten to make declaring instructions much simpler - Z80 has more instructions implemented; supports displacement on (IX), (IY) now - added `Processor::M68K::Bus` to mirror `Processor::Z80::Bus` - it does add a pointer indirection; so I'm not sure if I want to do this for all of my emulator cores ...
2016-09-04 13:51:27 +00:00
op(0xe2, "jp ", "po", NN)
Update to v101r30 release. byuu says: Changelog: - SMS: added cartridge ROM/RAM mirroring (fixes Alex Kidd) - SMS: fixed 8x16 sprite mode (fixes Wonder Boy, Ys graphics) - Z80: emulated "ex (sp),hl" instruction - Z80: fixed INx NF (should be set instead of cleared) - Z80: fixed loop condition check for CPxR, INxR, LDxR, OTxR (fixes walking in Wonder Boy) - SFC: removed Debugger and sfc/debugger.hpp - icarus: connected MS, GG, MD importing to the scan dialog - PCE: added emulation skeleton to higan and icarus At this point, Master System games are fairly highly compatible, sans audio. Game Gear games are running, but I need to crop the resolution and support the higher color palette that they can utilize. It's really something else the way they handled the resolution shrink on that thing. The last change is obviously going to be the biggest news. I'm very well aware it's not an ideal time to start on a new emulation core, with the MS and MD cores only just now coming to life with no audio support. But, for whatever reason, my heart's really set on working on the PC Engine. I wanted to write the final higan skeleton core, and get things ready so that whenever I'm in the mood to work on the PCE, I can do so. The skeleton is far and away the most tedious and obnoxious part of the emulator development, because it's basically all just lots of boilerplate templated code, lots of new files to create, etc. I really don't know how things are going to proceed ... but I can say with 99.9% certainty that this will be the final brand new core ever added to higan -- at least one written by me, that is. This was basically the last system from my childhood that I ever cared about. It's the last 2D system with games that I really enjoy playing. No other system is worth dividing my efforts and reducing the quality and amount of time to work on the systems I have. In the future, there will be potential for FDS, Mega CD and PCE-CD support. But those will all be add-ons, and they'll all be really difficult and challenge the entire design of higan's UI (it's entirely cartridge-driven at this time.) None of them will be entirely new cores like this one.
2017-01-11 20:27:30 +00:00
op(0xe3, "ex ", ISP, HL)
Update to v101r21 release. byuu says: Changelog: - Z80: emulated 83 new instructions - Z80: timing improvements DAA is a skeleton implementation to complete the normal opcode set. Also worth noting that I don't know exactly what the hell RETI is doing, so for now it acts like RET. RETN probably needs some special handling besides just setting IFF1=IFF2 as well. I'm now missing 24 ED-prefix instructions, plus DAA, for a total of 25 opcodes remaining. And then, of course, several weeks worth of debugging all of the inevitable bugs in the core.
2016-10-31 21:10:33 +00:00
op(0xe4, "call", "po", NN)
op(0xe5, "push", HL)
op(0xe6, "and ", A, N)
op(0xe7, "rst ", "4")
op(0xe8, "ret ", "pe")
op(0xe9, "jp ", HL) //officially jp (hl); but as read is not indirect, use jp hl
Update to v101r15 release. byuu says: Changelog: - added (poorly-named) castable<To, With> template - Z80 debugger rewritten to make declaring instructions much simpler - Z80 has more instructions implemented; supports displacement on (IX), (IY) now - added `Processor::M68K::Bus` to mirror `Processor::Z80::Bus` - it does add a pointer indirection; so I'm not sure if I want to do this for all of my emulator cores ...
2016-09-04 13:51:27 +00:00
op(0xea, "jp ", "pe", NN)
Update to v101r17 release. byuu says: Changelog: - Z80: added most opcodes between 0x00 and 0x3f (two or three hard ones missing still) - Z80: redid register declaration *again* to handle AF', BC', DE', HL' (ugggggh, the fuck? Alternate registers??) - basically, using `#define <register name>` values to get around horrendously awful naming syntax - Z80: improved handling of displace() so that it won't ever trigger on (BC) or (DE)
2016-09-06 13:53:14 +00:00
op(0xeb, "ex ", DE, _HL)
Update to v101r21 release. byuu says: Changelog: - Z80: emulated 83 new instructions - Z80: timing improvements DAA is a skeleton implementation to complete the normal opcode set. Also worth noting that I don't know exactly what the hell RETI is doing, so for now it acts like RET. RETN probably needs some special handling besides just setting IFF1=IFF2 as well. I'm now missing 24 ED-prefix instructions, plus DAA, for a total of 25 opcodes remaining. And then, of course, several weeks worth of debugging all of the inevitable bugs in the core.
2016-10-31 21:10:33 +00:00
op(0xec, "call", "pe", NN)
Update to v101r15 release. byuu says: Changelog: - added (poorly-named) castable<To, With> template - Z80 debugger rewritten to make declaring instructions much simpler - Z80 has more instructions implemented; supports displacement on (IX), (IY) now - added `Processor::M68K::Bus` to mirror `Processor::Z80::Bus` - it does add a pointer indirection; so I'm not sure if I want to do this for all of my emulator cores ...
2016-09-04 13:51:27 +00:00
op(0xed, "ed: ")
Update to v101r21 release. byuu says: Changelog: - Z80: emulated 83 new instructions - Z80: timing improvements DAA is a skeleton implementation to complete the normal opcode set. Also worth noting that I don't know exactly what the hell RETI is doing, so for now it acts like RET. RETN probably needs some special handling besides just setting IFF1=IFF2 as well. I'm now missing 24 ED-prefix instructions, plus DAA, for a total of 25 opcodes remaining. And then, of course, several weeks worth of debugging all of the inevitable bugs in the core.
2016-10-31 21:10:33 +00:00
op(0xee, "xor ", A, N)
op(0xef, "rst ", "5")
op(0xf0, "ret ", "p")
op(0xf1, "pop ", AF)
Update to v101r15 release. byuu says: Changelog: - added (poorly-named) castable<To, With> template - Z80 debugger rewritten to make declaring instructions much simpler - Z80 has more instructions implemented; supports displacement on (IX), (IY) now - added `Processor::M68K::Bus` to mirror `Processor::Z80::Bus` - it does add a pointer indirection; so I'm not sure if I want to do this for all of my emulator cores ...
2016-09-04 13:51:27 +00:00
op(0xf2, "jp ", "p", NN)
op(0xf3, "di ")
Update to v101r21 release. byuu says: Changelog: - Z80: emulated 83 new instructions - Z80: timing improvements DAA is a skeleton implementation to complete the normal opcode set. Also worth noting that I don't know exactly what the hell RETI is doing, so for now it acts like RET. RETN probably needs some special handling besides just setting IFF1=IFF2 as well. I'm now missing 24 ED-prefix instructions, plus DAA, for a total of 25 opcodes remaining. And then, of course, several weeks worth of debugging all of the inevitable bugs in the core.
2016-10-31 21:10:33 +00:00
op(0xf4, "call", "p", NN)
op(0xf5, "push", AF)
op(0xf6, "or ", A, N)
op(0xf7, "rst ", "6")
op(0xf8, "ret ", "m")
op(0xf9, "ld ", SP, HL)
Update to v101r15 release. byuu says: Changelog: - added (poorly-named) castable<To, With> template - Z80 debugger rewritten to make declaring instructions much simpler - Z80 has more instructions implemented; supports displacement on (IX), (IY) now - added `Processor::M68K::Bus` to mirror `Processor::Z80::Bus` - it does add a pointer indirection; so I'm not sure if I want to do this for all of my emulator cores ...
2016-09-04 13:51:27 +00:00
op(0xfa, "jp ", "m", NN)
op(0xfb, "ei ")
Update to v101r21 release. byuu says: Changelog: - Z80: emulated 83 new instructions - Z80: timing improvements DAA is a skeleton implementation to complete the normal opcode set. Also worth noting that I don't know exactly what the hell RETI is doing, so for now it acts like RET. RETN probably needs some special handling besides just setting IFF1=IFF2 as well. I'm now missing 24 ED-prefix instructions, plus DAA, for a total of 25 opcodes remaining. And then, of course, several weeks worth of debugging all of the inevitable bugs in the core.
2016-10-31 21:10:33 +00:00
op(0xfc, "call", "m", NN)
op(0xfd, "iy: ")
Update to v101r16 release. byuu says: Changelog: - Z80: implemented 113 new instructions (all the easy LD/ADC/ADD/AND/OR/SBC/SUB/XOR ones) - Z80: used alternative to castable<To, With> type (manual cast inside instruction() register macros) - Z80: debugger: used register macros to reduce typing and increase readability - Z80: debugger: smarter way of handling multiple DD/FD prefixes (using gotos, yay!) - ruby: fixed crash with Windows input driver on exit (from SuperMikeMan) I have no idea how the P/V flag is supposed to work on AND/OR/XOR, so that's probably wrong for now. HALT is also mostly a dummy function for now. But I typically implement those inside instruction(), so it probably won't need to be changed? We'll see.
2016-09-06 00:09:33 +00:00
op(0xfe, "cp ", A, N)
Update to v101r21 release. byuu says: Changelog: - Z80: emulated 83 new instructions - Z80: timing improvements DAA is a skeleton implementation to complete the normal opcode set. Also worth noting that I don't know exactly what the hell RETI is doing, so for now it acts like RET. RETN probably needs some special handling besides just setting IFF1=IFF2 as well. I'm now missing 24 ED-prefix instructions, plus DAA, for a total of 25 opcodes remaining. And then, of course, several weeks worth of debugging all of the inevitable bugs in the core.
2016-10-31 21:10:33 +00:00
op(0xff, "rst ", "7")
Update to v101r13 release. byuu says: Changelog: - MS: added ms/bus - Z80: implemented JP/JR/CP/DI/IM/IN instructions - MD/VDP: added window layer emulation - MD/controller/gamepad: fixed d2,d3 bits (Altered Beast requires this) The Z80 is definitely a lot nastier than the LR35902. There's a lot of table duplication with HL→IX→IY; and two of them nest two levels deep (eg FD CB xx xx), so the design may change as I implement more.
2016-08-27 04:48:21 +00:00
}
Update to v101r21 release. byuu says: Changelog: - Z80: emulated 83 new instructions - Z80: timing improvements DAA is a skeleton implementation to complete the normal opcode set. Also worth noting that I don't know exactly what the hell RETI is doing, so for now it acts like RET. RETN probably needs some special handling besides just setting IFF1=IFF2 as well. I'm now missing 24 ED-prefix instructions, plus DAA, for a total of 25 opcodes remaining. And then, of course, several weeks worth of debugging all of the inevitable bugs in the core.
2016-10-31 21:10:33 +00:00
unreachable;
Update to v101r13 release. byuu says: Changelog: - MS: added ms/bus - Z80: implemented JP/JR/CP/DI/IM/IN instructions - MD/VDP: added window layer emulation - MD/controller/gamepad: fixed d2,d3 bits (Altered Beast requires this) The Z80 is definitely a lot nastier than the LR35902. There's a lot of table duplication with HL→IX→IY; and two of them nest two levels deep (eg FD CB xx xx), so the design may change as I implement more.
2016-08-27 04:48:21 +00:00
}
Update to v101r14 release. byuu says: Changelog: - rewrote the Z80 core to properly handle 0xDD (IX0 and 0xFD (IY) prefixes - added Processor::Z80::Bus as a new type of abstraction - all of the instructions implemented have their proper T-cycle counts now - added nall/certificates for my public keys The goal of `Processor::Z80::Bus` is to simulate the opcode fetches being 2-read + 2-wait states; operand+regular reads/writes being 3-read. For now, this puts the cycle counts inside the CPU core. At the moment, I can't think of any CPU core where this wouldn't be appropriate. But it's certainly possible that such a case exists. So this may not be the perfect solution. The reason for having it be a subclass of Processor::Z80 instead of virtual functions for the MasterSystem::CPU core to define is due to naming conflicts. I wanted the core to say `in(addr)` and have it take the four clocks. But I also wanted a version of the function that didn't consume time when called. One way to do that would be for the core to call `Z80::in(addr)`, which then calls the regular `in(addr)` that goes to `MasterSystem::CPU::in(addr)`. But I don't want to put the `Z80::` prefix on all of the opcodes. Very easy to forget it, and then end up not consuming any time. Another is to use uglier names in the `MasterSystem::CPU` core, like `read_`, `write_`, `in_`, `out_`, etc. But, yuck. So ... yeah, this is an experiment. We'll see how it goes.
2016-09-03 11:26:04 +00:00
auto Z80::disassembleCB(uint16 pc, uint8 prefix, uint8 code) -> string {
Update to v101r20 release. byuu says: Changelog: - Z80: emulated 272 new instructions - hiro/GTK: fixed v101r19 Linux regression [thanks, SuperMikeMan!]
2016-10-29 00:33:30 +00:00
auto byte = [&] {
return bus->read(pc++);
};
auto word = [&] {
uint16 data = byte() << 0;
return data | byte() << 8;
};
auto branch = [&] {
auto d = byte();
return pc + (int8)d;
};
auto displace = [&] {
if(!prefix) return string{};
auto d = (int8)byte();
return d >= 0 ? string{"+$", hex(d, 2L)} : string{"-$", hex(-d, 2L)};
};
Update to v101r13 release. byuu says: Changelog: - MS: added ms/bus - Z80: implemented JP/JR/CP/DI/IM/IN instructions - MD/VDP: added window layer emulation - MD/controller/gamepad: fixed d2,d3 bits (Altered Beast requires this) The Z80 is definitely a lot nastier than the LR35902. There's a lot of table duplication with HL→IX→IY; and two of them nest two levels deep (eg FD CB xx xx), so the design may change as I implement more.
2016-08-27 04:48:21 +00:00
Update to v101r27 release. byuu says: Changelog: - SMS: emulated the generic Sega memory mapper (none of the more limited forms of it yet) - (missing ROM shift, ROM write enable emulation -- no commercial games use either, though) - SMS: bus I/O returns 0xff instead of 0x00 so games don't think every key is being pressed at once - (this is a hack until I implement proper controller pad reading) - SMS: very limited protection against reading/writing past the end of ROM/RAM (todo: should mirror) - SMS: VDP background HSCROLL subtracts, rather than adds, to the offset (unlike VSCROLL) - SMS: VDP VSCROLL is 9-bit, modulates voffset+vscroll to 224 in 192-line mode (32x28 tilemap) - SMS: VDP tiledata for backgrounds and sprites use `7-(x&7)` rather than `(x&7)` - SMS: fix output color to be 6-bit rather than 5-bit - SMS: left clip uses register `#7`, not palette color `#7` - (todo: do we want `color[reg7]` or `color[16 + reg7]`?) - SMS: refined handling of 0xcb, 0xed prefixes in the Z80 core and its disassembler - SMS: emulated (0xfd, 0xdd) 0xcb opcodes 0x00-0x0f (still missing 0x10-0xff) - SMS: fixed 0xcb 0b-----110 opcodes to use direct HL and never allow (IX,IY)+d - SMS: fixed major logic bug in (IX,IY)+d displacement - (was using `read(x)` instead of `operand()` for the displacement byte fetch before) - icarus: fake there always being 32KiB of RAM in all SMS cartridges for the time being - (not sure how to detect this stuff yet; although I've read it's not even really possible `>_>`) TODO: remove processor/z80/dissassembler.cpp code block at line 396 (as it's unnecessary.) Lots of commercial games are starting to show trashed graphical output now.
2017-01-06 08:11:38 +00:00
if(prefix) {
auto d = (int8)code;
string ds = d >= 0 ? string{"+$", hex(d, 2L)} : string{"-$", hex(-d, 2L)};
return {"rlc (", HL, ds, ")"};
}
Update to v101r14 release. byuu says: Changelog: - rewrote the Z80 core to properly handle 0xDD (IX0 and 0xFD (IY) prefixes - added Processor::Z80::Bus as a new type of abstraction - all of the instructions implemented have their proper T-cycle counts now - added nall/certificates for my public keys The goal of `Processor::Z80::Bus` is to simulate the opcode fetches being 2-read + 2-wait states; operand+regular reads/writes being 3-read. For now, this puts the cycle counts inside the CPU core. At the moment, I can't think of any CPU core where this wouldn't be appropriate. But it's certainly possible that such a case exists. So this may not be the perfect solution. The reason for having it be a subclass of Processor::Z80 instead of virtual functions for the MasterSystem::CPU core to define is due to naming conflicts. I wanted the core to say `in(addr)` and have it take the four clocks. But I also wanted a version of the function that didn't consume time when called. One way to do that would be for the core to call `Z80::in(addr)`, which then calls the regular `in(addr)` that goes to `MasterSystem::CPU::in(addr)`. But I don't want to put the `Z80::` prefix on all of the opcodes. Very easy to forget it, and then end up not consuming any time. Another is to use uglier names in the `MasterSystem::CPU` core, like `read_`, `write_`, `in_`, `out_`, etc. But, yuck. So ... yeah, this is an experiment. We'll see how it goes.
2016-09-03 11:26:04 +00:00
switch(code) {
Update to v101r20 release. byuu says: Changelog: - Z80: emulated 272 new instructions - hiro/GTK: fixed v101r19 Linux regression [thanks, SuperMikeMan!]
2016-10-29 00:33:30 +00:00
op(0x00, "rlc ", B)
op(0x01, "rlc ", C)
op(0x02, "rlc ", D)
op(0x03, "rlc ", E)
op(0x04, "rlc ", H)
op(0x05, "rlc ", L)
op(0x06, "rlc ", IHL)
op(0x07, "rlc ", A)
op(0x08, "rrc ", B)
op(0x09, "rrc ", C)
op(0x0a, "rrc ", D)
op(0x0b, "rrc ", E)
op(0x0c, "rrc ", H)
op(0x0d, "rrc ", L)
op(0x0e, "rrc ", IHL)
op(0x0f, "rrc ", A)
op(0x10, "rl ", B)
op(0x11, "rl ", C)
op(0x12, "rl ", D)
op(0x13, "rl ", E)
op(0x14, "rl ", H)
op(0x15, "rl ", L)
op(0x16, "rl ", IHL)
op(0x17, "rl ", A)
op(0x18, "rr ", B)
op(0x19, "rr ", C)
op(0x1a, "rr ", D)
op(0x1b, "rr ", E)
op(0x1c, "rr ", H)
op(0x1d, "rr ", L)
op(0x1e, "rr ", IHL)
op(0x1f, "rr ", A)
op(0x20, "sla ", B)
op(0x21, "sla ", C)
op(0x22, "sla ", D)
op(0x23, "sla ", E)
op(0x24, "sla ", H)
op(0x25, "sla ", L)
op(0x26, "sla ", IHL)
op(0x27, "sla ", A)
op(0x28, "sra ", B)
op(0x29, "sra ", C)
op(0x2a, "sra ", D)
op(0x2b, "sra ", E)
op(0x2c, "sra ", H)
op(0x2d, "sra ", L)
op(0x2e, "sra ", IHL)
op(0x2f, "sra ", A)
op(0x30, "sll ", B)
op(0x31, "sll ", C)
op(0x32, "sll ", D)
op(0x33, "sll ", E)
op(0x34, "sll ", H)
op(0x35, "sll ", L)
op(0x36, "sll ", IHL)
op(0x37, "sll ", A)
op(0x38, "srl ", B)
op(0x39, "srl ", C)
op(0x3a, "srl ", D)
op(0x3b, "srl ", E)
op(0x3c, "srl ", H)
op(0x3d, "srl ", L)
op(0x3e, "srl ", IHL)
op(0x3f, "srl ", A)
Update to v101r28 release. byuu says: Changelog: - SMS: emulated the remaining 240 instructions in the (0xfd, 0xdd) 0xcb (displacement) (opcode) set - 1/8th of these were "legal" instructions, and apparently games use them a lot - SMS: emulated the standard gamepad controllers - reset button not emulated yet The reset button is tricky. In every other case, reset is a hardware thing that instantly reboots the entire machine. But on the SMS, it's more like a gamepad button that's attached to the front of the device. When you press it, it fires off a reset vector interrupt and the gamepad polling routine lets you query the status of the button. Just having a reset option in the "Master System" hardware menu is not sufficient to fully emulate the behavior. Even more annoying is that the Game Gear doesn't have such a button, yet the core information structs aren't flexible enough for the Master System to have it, and the Game Gear to not have it, in the main menu. But that doesn't matter anyway, since it won't work having it in the menu for the Master System. So as a result, I'm going to have to have a new "input device" called "Hardware" that has the "Reset" button listed under there. And for the sake of consistency, I'm not sure if we should treat the other systems the same way or not :/
2017-01-08 20:55:02 +00:00
op(0x40, "bit ", "0", B)
op(0x41, "bit ", "0", C)
op(0x42, "bit ", "0", D)
op(0x43, "bit ", "0", E)
op(0x44, "bit ", "0", H)
op(0x45, "bit ", "0", L)
op(0x46, "bit ", "0", IHL)
op(0x47, "bit ", "0", A)
op(0x48, "bit ", "1", B)
op(0x49, "bit ", "1", C)
op(0x4a, "bit ", "1", D)
op(0x4b, "bit ", "1", E)
op(0x4c, "bit ", "1", H)
op(0x4d, "bit ", "1", L)
op(0x4e, "bit ", "1", IHL)
op(0x4f, "bit ", "1", A)
op(0x50, "bit ", "2", B)
op(0x51, "bit ", "2", C)
op(0x52, "bit ", "2", D)
op(0x53, "bit ", "2", E)
op(0x54, "bit ", "2", H)
op(0x55, "bit ", "2", L)
op(0x56, "bit ", "2", IHL)
op(0x57, "bit ", "2", A)
op(0x58, "bit ", "3", B)
op(0x59, "bit ", "3", C)
op(0x5a, "bit ", "3", D)
op(0x5b, "bit ", "3", E)
op(0x5c, "bit ", "3", H)
op(0x5d, "bit ", "3", L)
op(0x5e, "bit ", "3", IHL)
op(0x5f, "bit ", "3", A)
op(0x60, "bit ", "4", B)
op(0x61, "bit ", "4", C)
op(0x62, "bit ", "4", D)
op(0x63, "bit ", "4", E)
op(0x64, "bit ", "4", H)
op(0x65, "bit ", "4", L)
op(0x66, "bit ", "4", IHL)
op(0x67, "bit ", "4", A)
op(0x68, "bit ", "5", B)
op(0x69, "bit ", "5", C)
op(0x6a, "bit ", "5", D)
op(0x6b, "bit ", "5", E)
op(0x6c, "bit ", "5", H)
op(0x6d, "bit ", "5", L)
op(0x6e, "bit ", "5", IHL)
op(0x6f, "bit ", "5", A)
op(0x70, "bit ", "6", B)
op(0x71, "bit ", "6", C)
op(0x72, "bit ", "6", D)
op(0x73, "bit ", "6", E)
op(0x74, "bit ", "6", H)
op(0x75, "bit ", "6", L)
op(0x76, "bit ", "6", IHL)
op(0x77, "bit ", "6", A)
op(0x78, "bit ", "7", B)
op(0x79, "bit ", "7", C)
op(0x7a, "bit ", "7", D)
op(0x7b, "bit ", "7", E)
op(0x7c, "bit ", "7", H)
op(0x7d, "bit ", "7", L)
op(0x7e, "bit ", "7", IHL)
op(0x7f, "bit ", "7", A)
op(0x80, "res ", "0", B)
op(0x81, "res ", "0", C)
op(0x82, "res ", "0", D)
op(0x83, "res ", "0", E)
op(0x84, "res ", "0", H)
op(0x85, "res ", "0", L)
op(0x86, "res ", "0", IHL)
op(0x87, "res ", "0", A)
op(0x88, "res ", "1", B)
op(0x89, "res ", "1", C)
op(0x8a, "res ", "1", D)
op(0x8b, "res ", "1", E)
op(0x8c, "res ", "1", H)
op(0x8d, "res ", "1", L)
op(0x8e, "res ", "1", IHL)
op(0x8f, "res ", "1", A)
op(0x90, "res ", "2", B)
op(0x91, "res ", "2", C)
op(0x92, "res ", "2", D)
op(0x93, "res ", "2", E)
op(0x94, "res ", "2", H)
op(0x95, "res ", "2", L)
op(0x96, "res ", "2", IHL)
op(0x97, "res ", "2", A)
op(0x98, "res ", "3", B)
op(0x99, "res ", "3", C)
op(0x9a, "res ", "3", D)
op(0x9b, "res ", "3", E)
op(0x9c, "res ", "3", H)
op(0x9d, "res ", "3", L)
op(0x9e, "res ", "3", IHL)
op(0x9f, "res ", "3", A)
op(0xa0, "res ", "4", B)
op(0xa1, "res ", "4", C)
op(0xa2, "res ", "4", D)
op(0xa3, "res ", "4", E)
op(0xa4, "res ", "4", H)
op(0xa5, "res ", "4", L)
op(0xa6, "res ", "4", IHL)
op(0xa7, "res ", "4", A)
op(0xa8, "res ", "5", B)
op(0xa9, "res ", "5", C)
op(0xaa, "res ", "5", D)
op(0xab, "res ", "5", E)
op(0xac, "res ", "5", H)
op(0xad, "res ", "5", L)
op(0xae, "res ", "5", IHL)
op(0xaf, "res ", "5", A)
op(0xb0, "res ", "6", B)
op(0xb1, "res ", "6", C)
op(0xb2, "res ", "6", D)
op(0xb3, "res ", "6", E)
op(0xb4, "res ", "6", H)
op(0xb5, "res ", "6", L)
op(0xb6, "res ", "6", IHL)
op(0xb7, "res ", "6", A)
op(0xb8, "res ", "7", B)
op(0xb9, "res ", "7", C)
op(0xba, "res ", "7", D)
op(0xbb, "res ", "7", E)
op(0xbc, "res ", "7", H)
op(0xbd, "res ", "7", L)
op(0xbe, "res ", "7", IHL)
op(0xbf, "res ", "7", A)
op(0xc0, "set ", "0", B)
op(0xc1, "set ", "0", C)
op(0xc2, "set ", "0", D)
op(0xc3, "set ", "0", E)
op(0xc4, "set ", "0", H)
op(0xc5, "set ", "0", L)
op(0xc6, "set ", "0", IHL)
op(0xc7, "set ", "0", A)
op(0xc8, "set ", "1", B)
op(0xc9, "set ", "1", C)
op(0xca, "set ", "1", D)
op(0xcb, "set ", "1", E)
op(0xcc, "set ", "1", H)
op(0xcd, "set ", "1", L)
op(0xce, "set ", "1", IHL)
op(0xcf, "set ", "1", A)
op(0xd0, "set ", "2", B)
op(0xd1, "set ", "2", C)
op(0xd2, "set ", "2", D)
op(0xd3, "set ", "2", E)
op(0xd4, "set ", "2", H)
op(0xd5, "set ", "2", L)
op(0xd6, "set ", "2", IHL)
op(0xd7, "set ", "2", A)
op(0xd8, "set ", "3", B)
op(0xd9, "set ", "3", C)
op(0xda, "set ", "3", D)
op(0xdb, "set ", "3", E)
op(0xdc, "set ", "3", H)
op(0xdd, "set ", "3", L)
op(0xde, "set ", "3", IHL)
op(0xdf, "set ", "3", A)
op(0xe0, "set ", "4", B)
op(0xe1, "set ", "4", C)
op(0xe2, "set ", "4", D)
op(0xe3, "set ", "4", E)
op(0xe4, "set ", "4", H)
op(0xe5, "set ", "4", L)
op(0xe6, "set ", "4", IHL)
op(0xe7, "set ", "4", A)
op(0xe8, "set ", "5", B)
op(0xe9, "set ", "5", C)
op(0xea, "set ", "5", D)
op(0xeb, "set ", "5", E)
op(0xec, "set ", "5", H)
op(0xed, "set ", "5", L)
op(0xee, "set ", "5", IHL)
op(0xef, "set ", "5", A)
op(0xf0, "set ", "6", B)
op(0xf1, "set ", "6", C)
op(0xf2, "set ", "6", D)
op(0xf3, "set ", "6", E)
op(0xf4, "set ", "6", H)
op(0xf5, "set ", "6", L)
op(0xf6, "set ", "6", IHL)
op(0xf7, "set ", "6", A)
op(0xf8, "set ", "7", B)
op(0xf9, "set ", "7", C)
op(0xfa, "set ", "7", D)
op(0xfb, "set ", "7", E)
op(0xfc, "set ", "7", H)
op(0xfd, "set ", "7", L)
op(0xfe, "set ", "7", IHL)
op(0xff, "set ", "7", A)
Update to v101r13 release. byuu says: Changelog: - MS: added ms/bus - Z80: implemented JP/JR/CP/DI/IM/IN instructions - MD/VDP: added window layer emulation - MD/controller/gamepad: fixed d2,d3 bits (Altered Beast requires this) The Z80 is definitely a lot nastier than the LR35902. There's a lot of table duplication with HL→IX→IY; and two of them nest two levels deep (eg FD CB xx xx), so the design may change as I implement more.
2016-08-27 04:48:21 +00:00
}
Update to v101r21 release. byuu says: Changelog: - Z80: emulated 83 new instructions - Z80: timing improvements DAA is a skeleton implementation to complete the normal opcode set. Also worth noting that I don't know exactly what the hell RETI is doing, so for now it acts like RET. RETN probably needs some special handling besides just setting IFF1=IFF2 as well. I'm now missing 24 ED-prefix instructions, plus DAA, for a total of 25 opcodes remaining. And then, of course, several weeks worth of debugging all of the inevitable bugs in the core.
2016-10-31 21:10:33 +00:00
Update to v101r20 release. byuu says: Changelog: - Z80: emulated 272 new instructions - hiro/GTK: fixed v101r19 Linux regression [thanks, SuperMikeMan!]
2016-10-29 00:33:30 +00:00
unreachable;
Update to v101r13 release. byuu says: Changelog: - MS: added ms/bus - Z80: implemented JP/JR/CP/DI/IM/IN instructions - MD/VDP: added window layer emulation - MD/controller/gamepad: fixed d2,d3 bits (Altered Beast requires this) The Z80 is definitely a lot nastier than the LR35902. There's a lot of table duplication with HL→IX→IY; and two of them nest two levels deep (eg FD CB xx xx), so the design may change as I implement more.
2016-08-27 04:48:21 +00:00
}
Update to v101r27 release. byuu says: Changelog: - SMS: emulated the generic Sega memory mapper (none of the more limited forms of it yet) - (missing ROM shift, ROM write enable emulation -- no commercial games use either, though) - SMS: bus I/O returns 0xff instead of 0x00 so games don't think every key is being pressed at once - (this is a hack until I implement proper controller pad reading) - SMS: very limited protection against reading/writing past the end of ROM/RAM (todo: should mirror) - SMS: VDP background HSCROLL subtracts, rather than adds, to the offset (unlike VSCROLL) - SMS: VDP VSCROLL is 9-bit, modulates voffset+vscroll to 224 in 192-line mode (32x28 tilemap) - SMS: VDP tiledata for backgrounds and sprites use `7-(x&7)` rather than `(x&7)` - SMS: fix output color to be 6-bit rather than 5-bit - SMS: left clip uses register `#7`, not palette color `#7` - (todo: do we want `color[reg7]` or `color[16 + reg7]`?) - SMS: refined handling of 0xcb, 0xed prefixes in the Z80 core and its disassembler - SMS: emulated (0xfd, 0xdd) 0xcb opcodes 0x00-0x0f (still missing 0x10-0xff) - SMS: fixed 0xcb 0b-----110 opcodes to use direct HL and never allow (IX,IY)+d - SMS: fixed major logic bug in (IX,IY)+d displacement - (was using `read(x)` instead of `operand()` for the displacement byte fetch before) - icarus: fake there always being 32KiB of RAM in all SMS cartridges for the time being - (not sure how to detect this stuff yet; although I've read it's not even really possible `>_>`) TODO: remove processor/z80/dissassembler.cpp code block at line 396 (as it's unnecessary.) Lots of commercial games are starting to show trashed graphical output now.
2017-01-06 08:11:38 +00:00
auto Z80::disassembleCBd(uint16 pc, uint8 prefix, int8 d, uint8 code) -> string {
auto displace = [&] {
return d >= 0 ? string{"+$", hex(d, 2L)} : string{"-$", hex(-d, 2L)};
};
switch(code) {
op(0x00, "rlc ", IHL, B)
op(0x01, "rlc ", IHL, C)
op(0x02, "rlc ", IHL, D)
op(0x03, "rlc ", IHL, E)
op(0x04, "rlc ", IHL, H)
op(0x05, "rlc ", IHL, L)
op(0x06, "rlc ", IHL)
op(0x07, "rlc ", IHL, A)
op(0x08, "rrc ", IHL, B)
op(0x09, "rrc ", IHL, C)
op(0x0a, "rrc ", IHL, D)
op(0x0b, "rrc ", IHL, E)
op(0x0c, "rrc ", IHL, H)
op(0x0d, "rrc ", IHL, L)
op(0x0e, "rrc ", IHL)
op(0x0f, "rrc ", IHL, A)
Update to v101r28 release. byuu says: Changelog: - SMS: emulated the remaining 240 instructions in the (0xfd, 0xdd) 0xcb (displacement) (opcode) set - 1/8th of these were "legal" instructions, and apparently games use them a lot - SMS: emulated the standard gamepad controllers - reset button not emulated yet The reset button is tricky. In every other case, reset is a hardware thing that instantly reboots the entire machine. But on the SMS, it's more like a gamepad button that's attached to the front of the device. When you press it, it fires off a reset vector interrupt and the gamepad polling routine lets you query the status of the button. Just having a reset option in the "Master System" hardware menu is not sufficient to fully emulate the behavior. Even more annoying is that the Game Gear doesn't have such a button, yet the core information structs aren't flexible enough for the Master System to have it, and the Game Gear to not have it, in the main menu. But that doesn't matter anyway, since it won't work having it in the menu for the Master System. So as a result, I'm going to have to have a new "input device" called "Hardware" that has the "Reset" button listed under there. And for the sake of consistency, I'm not sure if we should treat the other systems the same way or not :/
2017-01-08 20:55:02 +00:00
op(0x10, "rl ", IHL, B)
op(0x11, "rl ", IHL, C)
op(0x12, "rl ", IHL, D)
op(0x13, "rl ", IHL, E)
op(0x14, "rl ", IHL, H)
op(0x15, "rl ", IHL, L)
op(0x16, "rl ", IHL)
op(0x17, "rl ", IHL, A)
op(0x18, "rr ", IHL, B)
op(0x19, "rr ", IHL, C)
op(0x1a, "rr ", IHL, D)
op(0x1b, "rr ", IHL, E)
op(0x1c, "rr ", IHL, H)
op(0x1d, "rr ", IHL, L)
op(0x1e, "rr ", IHL)
op(0x1f, "rr ", IHL, A)
op(0x20, "sla ", IHL, B)
op(0x21, "sla ", IHL, C)
op(0x22, "sla ", IHL, D)
op(0x23, "sla ", IHL, E)
op(0x24, "sla ", IHL, H)
op(0x25, "sla ", IHL, L)
op(0x26, "sla ", IHL)
op(0x27, "sla ", IHL, A)
op(0x28, "sra ", IHL, B)
op(0x29, "sra ", IHL, C)
op(0x2a, "sra ", IHL, D)
op(0x2b, "sra ", IHL, E)
op(0x2c, "sra ", IHL, H)
op(0x2d, "sra ", IHL, L)
op(0x2e, "sra ", IHL)
op(0x2f, "sra ", IHL, A)
op(0x30, "sll ", IHL, B)
op(0x31, "sll ", IHL, C)
op(0x32, "sll ", IHL, D)
op(0x33, "sll ", IHL, E)
op(0x34, "sll ", IHL, H)
op(0x35, "sll ", IHL, L)
op(0x36, "sll ", IHL)
op(0x37, "sll ", IHL, A)
op(0x38, "srl ", IHL, B)
op(0x39, "srl ", IHL, C)
op(0x3a, "srl ", IHL, D)
op(0x3b, "srl ", IHL, E)
op(0x3c, "srl ", IHL, H)
op(0x3d, "srl ", IHL, L)
op(0x3e, "srl ", IHL)
op(0x3f, "srl ", IHL, A)
op(0x40, "bit ", "0", IHL, B)
op(0x41, "bit ", "0", IHL, C)
op(0x42, "bit ", "0", IHL, D)
op(0x43, "bit ", "0", IHL, E)
op(0x44, "bit ", "0", IHL, H)
op(0x45, "bit ", "0", IHL, L)
op(0x46, "bit ", "0", IHL)
op(0x47, "bit ", "0", IHL, A)
op(0x48, "bit ", "1", IHL, B)
op(0x49, "bit ", "1", IHL, C)
op(0x4a, "bit ", "1", IHL, D)
op(0x4b, "bit ", "1", IHL, E)
op(0x4c, "bit ", "1", IHL, H)
op(0x4d, "bit ", "1", IHL, L)
op(0x4e, "bit ", "1", IHL)
op(0x4f, "bit ", "1", IHL, A)
op(0x50, "bit ", "2", IHL, B)
op(0x51, "bit ", "2", IHL, C)
op(0x52, "bit ", "2", IHL, D)
op(0x53, "bit ", "2", IHL, E)
op(0x54, "bit ", "2", IHL, H)
op(0x55, "bit ", "2", IHL, L)
op(0x56, "bit ", "2", IHL)
op(0x57, "bit ", "2", IHL, A)
op(0x58, "bit ", "3", IHL, B)
op(0x59, "bit ", "3", IHL, C)
op(0x5a, "bit ", "3", IHL, D)
op(0x5b, "bit ", "3", IHL, E)
op(0x5c, "bit ", "3", IHL, H)
op(0x5d, "bit ", "3", IHL, L)
op(0x5e, "bit ", "3", IHL)
op(0x5f, "bit ", "3", IHL, A)
op(0x60, "bit ", "4", IHL, B)
op(0x61, "bit ", "4", IHL, C)
op(0x62, "bit ", "4", IHL, D)
op(0x63, "bit ", "4", IHL, E)
op(0x64, "bit ", "4", IHL, H)
op(0x65, "bit ", "4", IHL, L)
op(0x66, "bit ", "4", IHL)
op(0x67, "bit ", "4", IHL, A)
op(0x68, "bit ", "5", IHL, B)
op(0x69, "bit ", "5", IHL, C)
op(0x6a, "bit ", "5", IHL, D)
op(0x6b, "bit ", "5", IHL, E)
op(0x6c, "bit ", "5", IHL, H)
op(0x6d, "bit ", "5", IHL, L)
op(0x6e, "bit ", "5", IHL)
op(0x6f, "bit ", "5", IHL, A)
op(0x70, "bit ", "6", IHL, B)
op(0x71, "bit ", "6", IHL, C)
op(0x72, "bit ", "6", IHL, D)
op(0x73, "bit ", "6", IHL, E)
op(0x74, "bit ", "6", IHL, H)
op(0x75, "bit ", "6", IHL, L)
op(0x76, "bit ", "6", IHL)
op(0x77, "bit ", "6", IHL, A)
op(0x78, "bit ", "7", IHL, B)
op(0x79, "bit ", "7", IHL, C)
op(0x7a, "bit ", "7", IHL, D)
op(0x7b, "bit ", "7", IHL, E)
op(0x7c, "bit ", "7", IHL, H)
op(0x7d, "bit ", "7", IHL, L)
op(0x7e, "bit ", "7", IHL)
op(0x7f, "bit ", "7", IHL, A)
op(0x80, "res ", "0", IHL, B)
op(0x81, "res ", "0", IHL, C)
op(0x82, "res ", "0", IHL, D)
op(0x83, "res ", "0", IHL, E)
op(0x84, "res ", "0", IHL, H)
op(0x85, "res ", "0", IHL, L)
op(0x86, "res ", "0", IHL)
op(0x87, "res ", "0", IHL, A)
op(0x88, "res ", "1", IHL, B)
op(0x89, "res ", "1", IHL, C)
op(0x8a, "res ", "1", IHL, D)
op(0x8b, "res ", "1", IHL, E)
op(0x8c, "res ", "1", IHL, H)
op(0x8d, "res ", "1", IHL, L)
op(0x8e, "res ", "1", IHL)
op(0x8f, "res ", "1", IHL, A)
op(0x90, "res ", "2", IHL, B)
op(0x91, "res ", "2", IHL, C)
op(0x92, "res ", "2", IHL, D)
op(0x93, "res ", "2", IHL, E)
op(0x94, "res ", "2", IHL, H)
op(0x95, "res ", "2", IHL, L)
op(0x96, "res ", "2", IHL)
op(0x97, "res ", "2", IHL, A)
op(0x98, "res ", "3", IHL, B)
op(0x99, "res ", "3", IHL, C)
op(0x9a, "res ", "3", IHL, D)
op(0x9b, "res ", "3", IHL, E)
op(0x9c, "res ", "3", IHL, H)
op(0x9d, "res ", "3", IHL, L)
op(0x9e, "res ", "3", IHL)
op(0x9f, "res ", "3", IHL, A)
op(0xa0, "res ", "4", IHL, B)
op(0xa1, "res ", "4", IHL, C)
op(0xa2, "res ", "4", IHL, D)
op(0xa3, "res ", "4", IHL, E)
op(0xa4, "res ", "4", IHL, H)
op(0xa5, "res ", "4", IHL, L)
op(0xa6, "res ", "4", IHL)
op(0xa7, "res ", "4", IHL, A)
op(0xa8, "res ", "5", IHL, B)
op(0xa9, "res ", "5", IHL, C)
op(0xaa, "res ", "5", IHL, D)
op(0xab, "res ", "5", IHL, E)
op(0xac, "res ", "5", IHL, H)
op(0xad, "res ", "5", IHL, L)
op(0xae, "res ", "5", IHL)
op(0xaf, "res ", "5", IHL, A)
op(0xb0, "res ", "6", IHL, B)
op(0xb1, "res ", "6", IHL, C)
op(0xb2, "res ", "6", IHL, D)
op(0xb3, "res ", "6", IHL, E)
op(0xb4, "res ", "6", IHL, H)
op(0xb5, "res ", "6", IHL, L)
op(0xb6, "res ", "6", IHL)
op(0xb7, "res ", "6", IHL, A)
op(0xb8, "res ", "7", IHL, B)
op(0xb9, "res ", "7", IHL, C)
op(0xba, "res ", "7", IHL, D)
op(0xbb, "res ", "7", IHL, E)
op(0xbc, "res ", "7", IHL, H)
op(0xbd, "res ", "7", IHL, L)
op(0xbe, "res ", "7", IHL)
op(0xbf, "res ", "7", IHL, A)
op(0xc0, "set ", "0", IHL, B)
op(0xc1, "set ", "0", IHL, C)
op(0xc2, "set ", "0", IHL, D)
op(0xc3, "set ", "0", IHL, E)
op(0xc4, "set ", "0", IHL, H)
op(0xc5, "set ", "0", IHL, L)
op(0xc6, "set ", "0", IHL)
op(0xc7, "set ", "0", IHL, A)
op(0xc8, "set ", "1", IHL, B)
op(0xc9, "set ", "1", IHL, C)
op(0xca, "set ", "1", IHL, D)
op(0xcb, "set ", "1", IHL, E)
op(0xcc, "set ", "1", IHL, H)
op(0xcd, "set ", "1", IHL, L)
op(0xce, "set ", "1", IHL)
op(0xcf, "set ", "1", IHL, A)
op(0xd0, "set ", "2", IHL, B)
op(0xd1, "set ", "2", IHL, C)
op(0xd2, "set ", "2", IHL, D)
op(0xd3, "set ", "2", IHL, E)
op(0xd4, "set ", "2", IHL, H)
op(0xd5, "set ", "2", IHL, L)
op(0xd6, "set ", "2", IHL)
op(0xd7, "set ", "2", IHL, A)
op(0xd8, "set ", "3", IHL, B)
op(0xd9, "set ", "3", IHL, C)
op(0xda, "set ", "3", IHL, D)
op(0xdb, "set ", "3", IHL, E)
op(0xdc, "set ", "3", IHL, H)
op(0xdd, "set ", "3", IHL, L)
op(0xde, "set ", "3", IHL)
op(0xdf, "set ", "3", IHL, A)
op(0xe0, "set ", "4", IHL, B)
op(0xe1, "set ", "4", IHL, C)
op(0xe2, "set ", "4", IHL, D)
op(0xe3, "set ", "4", IHL, E)
op(0xe4, "set ", "4", IHL, H)
op(0xe5, "set ", "4", IHL, L)
op(0xe6, "set ", "4", IHL)
op(0xe7, "set ", "4", IHL, A)
op(0xe8, "set ", "5", IHL, B)
op(0xe9, "set ", "5", IHL, C)
op(0xea, "set ", "5", IHL, D)
op(0xeb, "set ", "5", IHL, E)
op(0xec, "set ", "5", IHL, H)
op(0xed, "set ", "5", IHL, L)
op(0xee, "set ", "5", IHL)
op(0xef, "set ", "5", IHL, A)
op(0xf0, "set ", "6", IHL, B)
op(0xf1, "set ", "6", IHL, C)
op(0xf2, "set ", "6", IHL, D)
op(0xf3, "set ", "6", IHL, E)
op(0xf4, "set ", "6", IHL, H)
op(0xf5, "set ", "6", IHL, L)
op(0xf6, "set ", "6", IHL)
op(0xf7, "set ", "6", IHL, A)
op(0xf8, "set ", "7", IHL, B)
op(0xf9, "set ", "7", IHL, C)
op(0xfa, "set ", "7", IHL, D)
op(0xfb, "set ", "7", IHL, E)
op(0xfc, "set ", "7", IHL, H)
op(0xfd, "set ", "7", IHL, L)
op(0xfe, "set ", "7", IHL)
op(0xff, "set ", "7", IHL, A)
Update to v101r27 release. byuu says: Changelog: - SMS: emulated the generic Sega memory mapper (none of the more limited forms of it yet) - (missing ROM shift, ROM write enable emulation -- no commercial games use either, though) - SMS: bus I/O returns 0xff instead of 0x00 so games don't think every key is being pressed at once - (this is a hack until I implement proper controller pad reading) - SMS: very limited protection against reading/writing past the end of ROM/RAM (todo: should mirror) - SMS: VDP background HSCROLL subtracts, rather than adds, to the offset (unlike VSCROLL) - SMS: VDP VSCROLL is 9-bit, modulates voffset+vscroll to 224 in 192-line mode (32x28 tilemap) - SMS: VDP tiledata for backgrounds and sprites use `7-(x&7)` rather than `(x&7)` - SMS: fix output color to be 6-bit rather than 5-bit - SMS: left clip uses register `#7`, not palette color `#7` - (todo: do we want `color[reg7]` or `color[16 + reg7]`?) - SMS: refined handling of 0xcb, 0xed prefixes in the Z80 core and its disassembler - SMS: emulated (0xfd, 0xdd) 0xcb opcodes 0x00-0x0f (still missing 0x10-0xff) - SMS: fixed 0xcb 0b-----110 opcodes to use direct HL and never allow (IX,IY)+d - SMS: fixed major logic bug in (IX,IY)+d displacement - (was using `read(x)` instead of `operand()` for the displacement byte fetch before) - icarus: fake there always being 32KiB of RAM in all SMS cartridges for the time being - (not sure how to detect this stuff yet; although I've read it's not even really possible `>_>`) TODO: remove processor/z80/dissassembler.cpp code block at line 396 (as it's unnecessary.) Lots of commercial games are starting to show trashed graphical output now.
2017-01-06 08:11:38 +00:00
}
Update to v101r28 release. byuu says: Changelog: - SMS: emulated the remaining 240 instructions in the (0xfd, 0xdd) 0xcb (displacement) (opcode) set - 1/8th of these were "legal" instructions, and apparently games use them a lot - SMS: emulated the standard gamepad controllers - reset button not emulated yet The reset button is tricky. In every other case, reset is a hardware thing that instantly reboots the entire machine. But on the SMS, it's more like a gamepad button that's attached to the front of the device. When you press it, it fires off a reset vector interrupt and the gamepad polling routine lets you query the status of the button. Just having a reset option in the "Master System" hardware menu is not sufficient to fully emulate the behavior. Even more annoying is that the Game Gear doesn't have such a button, yet the core information structs aren't flexible enough for the Master System to have it, and the Game Gear to not have it, in the main menu. But that doesn't matter anyway, since it won't work having it in the menu for the Master System. So as a result, I'm going to have to have a new "input device" called "Hardware" that has the "Reset" button listed under there. And for the sake of consistency, I'm not sure if we should treat the other systems the same way or not :/
2017-01-08 20:55:02 +00:00
unreachable;
Update to v101r27 release. byuu says: Changelog: - SMS: emulated the generic Sega memory mapper (none of the more limited forms of it yet) - (missing ROM shift, ROM write enable emulation -- no commercial games use either, though) - SMS: bus I/O returns 0xff instead of 0x00 so games don't think every key is being pressed at once - (this is a hack until I implement proper controller pad reading) - SMS: very limited protection against reading/writing past the end of ROM/RAM (todo: should mirror) - SMS: VDP background HSCROLL subtracts, rather than adds, to the offset (unlike VSCROLL) - SMS: VDP VSCROLL is 9-bit, modulates voffset+vscroll to 224 in 192-line mode (32x28 tilemap) - SMS: VDP tiledata for backgrounds and sprites use `7-(x&7)` rather than `(x&7)` - SMS: fix output color to be 6-bit rather than 5-bit - SMS: left clip uses register `#7`, not palette color `#7` - (todo: do we want `color[reg7]` or `color[16 + reg7]`?) - SMS: refined handling of 0xcb, 0xed prefixes in the Z80 core and its disassembler - SMS: emulated (0xfd, 0xdd) 0xcb opcodes 0x00-0x0f (still missing 0x10-0xff) - SMS: fixed 0xcb 0b-----110 opcodes to use direct HL and never allow (IX,IY)+d - SMS: fixed major logic bug in (IX,IY)+d displacement - (was using `read(x)` instead of `operand()` for the displacement byte fetch before) - icarus: fake there always being 32KiB of RAM in all SMS cartridges for the time being - (not sure how to detect this stuff yet; although I've read it's not even really possible `>_>`) TODO: remove processor/z80/dissassembler.cpp code block at line 396 (as it's unnecessary.) Lots of commercial games are starting to show trashed graphical output now.
2017-01-06 08:11:38 +00:00
}
Update to v101r14 release. byuu says: Changelog: - rewrote the Z80 core to properly handle 0xDD (IX0 and 0xFD (IY) prefixes - added Processor::Z80::Bus as a new type of abstraction - all of the instructions implemented have their proper T-cycle counts now - added nall/certificates for my public keys The goal of `Processor::Z80::Bus` is to simulate the opcode fetches being 2-read + 2-wait states; operand+regular reads/writes being 3-read. For now, this puts the cycle counts inside the CPU core. At the moment, I can't think of any CPU core where this wouldn't be appropriate. But it's certainly possible that such a case exists. So this may not be the perfect solution. The reason for having it be a subclass of Processor::Z80 instead of virtual functions for the MasterSystem::CPU core to define is due to naming conflicts. I wanted the core to say `in(addr)` and have it take the four clocks. But I also wanted a version of the function that didn't consume time when called. One way to do that would be for the core to call `Z80::in(addr)`, which then calls the regular `in(addr)` that goes to `MasterSystem::CPU::in(addr)`. But I don't want to put the `Z80::` prefix on all of the opcodes. Very easy to forget it, and then end up not consuming any time. Another is to use uglier names in the `MasterSystem::CPU` core, like `read_`, `write_`, `in_`, `out_`, etc. But, yuck. So ... yeah, this is an experiment. We'll see how it goes.
2016-09-03 11:26:04 +00:00
auto Z80::disassembleED(uint16 pc, uint8 prefix, uint8 code) -> string {
Update to v101r20 release. byuu says: Changelog: - Z80: emulated 272 new instructions - hiro/GTK: fixed v101r19 Linux regression [thanks, SuperMikeMan!]
2016-10-29 00:33:30 +00:00
auto byte = [&] {
return bus->read(pc++);
};
auto word = [&] {
uint16 data = byte() << 0;
return data | byte() << 8;
};
auto branch = [&] {
auto d = byte();
return pc + (int8)d;
};
auto displace = [&] {
if(!prefix) return string{};
auto d = (int8)byte();
return d >= 0 ? string{"+$", hex(d, 2L)} : string{"-$", hex(-d, 2L)};
};
Update to v101r13 release. byuu says: Changelog: - MS: added ms/bus - Z80: implemented JP/JR/CP/DI/IM/IN instructions - MD/VDP: added window layer emulation - MD/controller/gamepad: fixed d2,d3 bits (Altered Beast requires this) The Z80 is definitely a lot nastier than the LR35902. There's a lot of table duplication with HL→IX→IY; and two of them nest two levels deep (eg FD CB xx xx), so the design may change as I implement more.
2016-08-27 04:48:21 +00:00
Update to v101r14 release. byuu says: Changelog: - rewrote the Z80 core to properly handle 0xDD (IX0 and 0xFD (IY) prefixes - added Processor::Z80::Bus as a new type of abstraction - all of the instructions implemented have their proper T-cycle counts now - added nall/certificates for my public keys The goal of `Processor::Z80::Bus` is to simulate the opcode fetches being 2-read + 2-wait states; operand+regular reads/writes being 3-read. For now, this puts the cycle counts inside the CPU core. At the moment, I can't think of any CPU core where this wouldn't be appropriate. But it's certainly possible that such a case exists. So this may not be the perfect solution. The reason for having it be a subclass of Processor::Z80 instead of virtual functions for the MasterSystem::CPU core to define is due to naming conflicts. I wanted the core to say `in(addr)` and have it take the four clocks. But I also wanted a version of the function that didn't consume time when called. One way to do that would be for the core to call `Z80::in(addr)`, which then calls the regular `in(addr)` that goes to `MasterSystem::CPU::in(addr)`. But I don't want to put the `Z80::` prefix on all of the opcodes. Very easy to forget it, and then end up not consuming any time. Another is to use uglier names in the `MasterSystem::CPU` core, like `read_`, `write_`, `in_`, `out_`, etc. But, yuck. So ... yeah, this is an experiment. We'll see how it goes.
2016-09-03 11:26:04 +00:00
switch(code) {
Update to v101r21 release. byuu says: Changelog: - Z80: emulated 83 new instructions - Z80: timing improvements DAA is a skeleton implementation to complete the normal opcode set. Also worth noting that I don't know exactly what the hell RETI is doing, so for now it acts like RET. RETN probably needs some special handling besides just setting IFF1=IFF2 as well. I'm now missing 24 ED-prefix instructions, plus DAA, for a total of 25 opcodes remaining. And then, of course, several weeks worth of debugging all of the inevitable bugs in the core.
2016-10-31 21:10:33 +00:00
op(0x40, "in ", B, IC)
op(0x41, "out ", IC, B)
Update to v101r22 release. byuu says: Changelog: - Z80: all 25 remaining instructions implemented Now onto the debugging ... :/
2016-11-01 11:42:25 +00:00
op(0x42, "sbc ", HL, BC)
op(0x43, "ld ", INN, BC)
Update to v101r21 release. byuu says: Changelog: - Z80: emulated 83 new instructions - Z80: timing improvements DAA is a skeleton implementation to complete the normal opcode set. Also worth noting that I don't know exactly what the hell RETI is doing, so for now it acts like RET. RETN probably needs some special handling besides just setting IFF1=IFF2 as well. I'm now missing 24 ED-prefix instructions, plus DAA, for a total of 25 opcodes remaining. And then, of course, several weeks worth of debugging all of the inevitable bugs in the core.
2016-10-31 21:10:33 +00:00
op(0x44, "neg ")
op(0x45, "retn")
Update to v101r15 release. byuu says: Changelog: - added (poorly-named) castable<To, With> template - Z80 debugger rewritten to make declaring instructions much simpler - Z80 has more instructions implemented; supports displacement on (IX), (IY) now - added `Processor::M68K::Bus` to mirror `Processor::Z80::Bus` - it does add a pointer indirection; so I'm not sure if I want to do this for all of my emulator cores ...
2016-09-04 13:51:27 +00:00
op(0x46, "im ", "0")
Update to v101r22 release. byuu says: Changelog: - Z80: all 25 remaining instructions implemented Now onto the debugging ... :/
2016-11-01 11:42:25 +00:00
op(0x47, "ld ", I, A)
Update to v101r21 release. byuu says: Changelog: - Z80: emulated 83 new instructions - Z80: timing improvements DAA is a skeleton implementation to complete the normal opcode set. Also worth noting that I don't know exactly what the hell RETI is doing, so for now it acts like RET. RETN probably needs some special handling besides just setting IFF1=IFF2 as well. I'm now missing 24 ED-prefix instructions, plus DAA, for a total of 25 opcodes remaining. And then, of course, several weeks worth of debugging all of the inevitable bugs in the core.
2016-10-31 21:10:33 +00:00
op(0x48, "in ", C, IC)
op(0x49, "out ", IC, C)
Update to v101r22 release. byuu says: Changelog: - Z80: all 25 remaining instructions implemented Now onto the debugging ... :/
2016-11-01 11:42:25 +00:00
op(0x4a, "adc ", HL, BC)
op(0x4b, "ld ", BC, INN)
Update to v101r21 release. byuu says: Changelog: - Z80: emulated 83 new instructions - Z80: timing improvements DAA is a skeleton implementation to complete the normal opcode set. Also worth noting that I don't know exactly what the hell RETI is doing, so for now it acts like RET. RETN probably needs some special handling besides just setting IFF1=IFF2 as well. I'm now missing 24 ED-prefix instructions, plus DAA, for a total of 25 opcodes remaining. And then, of course, several weeks worth of debugging all of the inevitable bugs in the core.
2016-10-31 21:10:33 +00:00
op(0x4c, "neg ")
op(0x4d, "reti")
op(0x4e, "im ", "0")
Update to v101r22 release. byuu says: Changelog: - Z80: all 25 remaining instructions implemented Now onto the debugging ... :/
2016-11-01 11:42:25 +00:00
op(0x4f, "ld ", R, A)
Update to v101r21 release. byuu says: Changelog: - Z80: emulated 83 new instructions - Z80: timing improvements DAA is a skeleton implementation to complete the normal opcode set. Also worth noting that I don't know exactly what the hell RETI is doing, so for now it acts like RET. RETN probably needs some special handling besides just setting IFF1=IFF2 as well. I'm now missing 24 ED-prefix instructions, plus DAA, for a total of 25 opcodes remaining. And then, of course, several weeks worth of debugging all of the inevitable bugs in the core.
2016-10-31 21:10:33 +00:00
op(0x50, "in ", D, IC)
op(0x51, "out ", IC, D)
Update to v101r22 release. byuu says: Changelog: - Z80: all 25 remaining instructions implemented Now onto the debugging ... :/
2016-11-01 11:42:25 +00:00
op(0x52, "sbc ", HL, DE)
op(0x53, "ld ", INN, DE)
Update to v101r21 release. byuu says: Changelog: - Z80: emulated 83 new instructions - Z80: timing improvements DAA is a skeleton implementation to complete the normal opcode set. Also worth noting that I don't know exactly what the hell RETI is doing, so for now it acts like RET. RETN probably needs some special handling besides just setting IFF1=IFF2 as well. I'm now missing 24 ED-prefix instructions, plus DAA, for a total of 25 opcodes remaining. And then, of course, several weeks worth of debugging all of the inevitable bugs in the core.
2016-10-31 21:10:33 +00:00
op(0x54, "neg ")
op(0x55, "retn")
Update to v101r15 release. byuu says: Changelog: - added (poorly-named) castable<To, With> template - Z80 debugger rewritten to make declaring instructions much simpler - Z80 has more instructions implemented; supports displacement on (IX), (IY) now - added `Processor::M68K::Bus` to mirror `Processor::Z80::Bus` - it does add a pointer indirection; so I'm not sure if I want to do this for all of my emulator cores ...
2016-09-04 13:51:27 +00:00
op(0x56, "im ", "1")
Update to v101r22 release. byuu says: Changelog: - Z80: all 25 remaining instructions implemented Now onto the debugging ... :/
2016-11-01 11:42:25 +00:00
op(0x57, "ld ", A, I)
Update to v101r21 release. byuu says: Changelog: - Z80: emulated 83 new instructions - Z80: timing improvements DAA is a skeleton implementation to complete the normal opcode set. Also worth noting that I don't know exactly what the hell RETI is doing, so for now it acts like RET. RETN probably needs some special handling besides just setting IFF1=IFF2 as well. I'm now missing 24 ED-prefix instructions, plus DAA, for a total of 25 opcodes remaining. And then, of course, several weeks worth of debugging all of the inevitable bugs in the core.
2016-10-31 21:10:33 +00:00
op(0x58, "in ", E, IC)
op(0x59, "out ", IC, E)
Update to v101r22 release. byuu says: Changelog: - Z80: all 25 remaining instructions implemented Now onto the debugging ... :/
2016-11-01 11:42:25 +00:00
op(0x5a, "adc ", HL, DE)
op(0x5b, "ld ", DE, INN)
Update to v101r21 release. byuu says: Changelog: - Z80: emulated 83 new instructions - Z80: timing improvements DAA is a skeleton implementation to complete the normal opcode set. Also worth noting that I don't know exactly what the hell RETI is doing, so for now it acts like RET. RETN probably needs some special handling besides just setting IFF1=IFF2 as well. I'm now missing 24 ED-prefix instructions, plus DAA, for a total of 25 opcodes remaining. And then, of course, several weeks worth of debugging all of the inevitable bugs in the core.
2016-10-31 21:10:33 +00:00
op(0x5c, "neg ")
op(0x5d, "reti")
Update to v101r15 release. byuu says: Changelog: - added (poorly-named) castable<To, With> template - Z80 debugger rewritten to make declaring instructions much simpler - Z80 has more instructions implemented; supports displacement on (IX), (IY) now - added `Processor::M68K::Bus` to mirror `Processor::Z80::Bus` - it does add a pointer indirection; so I'm not sure if I want to do this for all of my emulator cores ...
2016-09-04 13:51:27 +00:00
op(0x5e, "im ", "2")
Update to v101r22 release. byuu says: Changelog: - Z80: all 25 remaining instructions implemented Now onto the debugging ... :/
2016-11-01 11:42:25 +00:00
op(0x5f, "ld ", A, R)
Update to v101r21 release. byuu says: Changelog: - Z80: emulated 83 new instructions - Z80: timing improvements DAA is a skeleton implementation to complete the normal opcode set. Also worth noting that I don't know exactly what the hell RETI is doing, so for now it acts like RET. RETN probably needs some special handling besides just setting IFF1=IFF2 as well. I'm now missing 24 ED-prefix instructions, plus DAA, for a total of 25 opcodes remaining. And then, of course, several weeks worth of debugging all of the inevitable bugs in the core.
2016-10-31 21:10:33 +00:00
op(0x60, "in ", H, IC)
op(0x61, "out ", IC, H)
Update to v101r22 release. byuu says: Changelog: - Z80: all 25 remaining instructions implemented Now onto the debugging ... :/
2016-11-01 11:42:25 +00:00
op(0x62, "sbc ", HL, HL)
op(0x63, "ld ", INN, HL)
Update to v101r21 release. byuu says: Changelog: - Z80: emulated 83 new instructions - Z80: timing improvements DAA is a skeleton implementation to complete the normal opcode set. Also worth noting that I don't know exactly what the hell RETI is doing, so for now it acts like RET. RETN probably needs some special handling besides just setting IFF1=IFF2 as well. I'm now missing 24 ED-prefix instructions, plus DAA, for a total of 25 opcodes remaining. And then, of course, several weeks worth of debugging all of the inevitable bugs in the core.
2016-10-31 21:10:33 +00:00
op(0x64, "neg ")
op(0x65, "retn")
op(0x66, "im ", "0")
Update to v101r22 release. byuu says: Changelog: - Z80: all 25 remaining instructions implemented Now onto the debugging ... :/
2016-11-01 11:42:25 +00:00
op(0x67, "rrd ")
Update to v101r21 release. byuu says: Changelog: - Z80: emulated 83 new instructions - Z80: timing improvements DAA is a skeleton implementation to complete the normal opcode set. Also worth noting that I don't know exactly what the hell RETI is doing, so for now it acts like RET. RETN probably needs some special handling besides just setting IFF1=IFF2 as well. I'm now missing 24 ED-prefix instructions, plus DAA, for a total of 25 opcodes remaining. And then, of course, several weeks worth of debugging all of the inevitable bugs in the core.
2016-10-31 21:10:33 +00:00
op(0x68, "in ", L, IC)
op(0x69, "out ", IC, L)
Update to v101r22 release. byuu says: Changelog: - Z80: all 25 remaining instructions implemented Now onto the debugging ... :/
2016-11-01 11:42:25 +00:00
op(0x6a, "adc ", HL, HL)
op(0x6b, "ld ", HL, INN)
Update to v101r21 release. byuu says: Changelog: - Z80: emulated 83 new instructions - Z80: timing improvements DAA is a skeleton implementation to complete the normal opcode set. Also worth noting that I don't know exactly what the hell RETI is doing, so for now it acts like RET. RETN probably needs some special handling besides just setting IFF1=IFF2 as well. I'm now missing 24 ED-prefix instructions, plus DAA, for a total of 25 opcodes remaining. And then, of course, several weeks worth of debugging all of the inevitable bugs in the core.
2016-10-31 21:10:33 +00:00
op(0x6c, "neg ")
op(0x6d, "reti")
op(0x6e, "im ", "0")
Update to v101r22 release. byuu says: Changelog: - Z80: all 25 remaining instructions implemented Now onto the debugging ... :/
2016-11-01 11:42:25 +00:00
op(0x6f, "rld ")
Update to v101r21 release. byuu says: Changelog: - Z80: emulated 83 new instructions - Z80: timing improvements DAA is a skeleton implementation to complete the normal opcode set. Also worth noting that I don't know exactly what the hell RETI is doing, so for now it acts like RET. RETN probably needs some special handling besides just setting IFF1=IFF2 as well. I'm now missing 24 ED-prefix instructions, plus DAA, for a total of 25 opcodes remaining. And then, of course, several weeks worth of debugging all of the inevitable bugs in the core.
2016-10-31 21:10:33 +00:00
op(0x70, "in ", F, IC)
op(0x71, "out ", IC, F)
Update to v101r22 release. byuu says: Changelog: - Z80: all 25 remaining instructions implemented Now onto the debugging ... :/
2016-11-01 11:42:25 +00:00
op(0x72, "sbc ", HL, SP)
op(0x73, "ld ", INN, SP)
Update to v101r21 release. byuu says: Changelog: - Z80: emulated 83 new instructions - Z80: timing improvements DAA is a skeleton implementation to complete the normal opcode set. Also worth noting that I don't know exactly what the hell RETI is doing, so for now it acts like RET. RETN probably needs some special handling besides just setting IFF1=IFF2 as well. I'm now missing 24 ED-prefix instructions, plus DAA, for a total of 25 opcodes remaining. And then, of course, several weeks worth of debugging all of the inevitable bugs in the core.
2016-10-31 21:10:33 +00:00
op(0x74, "neg ")
op(0x75, "retn")
op(0x76, "im ", "1")
Update to v101r22 release. byuu says: Changelog: - Z80: all 25 remaining instructions implemented Now onto the debugging ... :/
2016-11-01 11:42:25 +00:00
op(0x77, "nop ")
Update to v101r21 release. byuu says: Changelog: - Z80: emulated 83 new instructions - Z80: timing improvements DAA is a skeleton implementation to complete the normal opcode set. Also worth noting that I don't know exactly what the hell RETI is doing, so for now it acts like RET. RETN probably needs some special handling besides just setting IFF1=IFF2 as well. I'm now missing 24 ED-prefix instructions, plus DAA, for a total of 25 opcodes remaining. And then, of course, several weeks worth of debugging all of the inevitable bugs in the core.
2016-10-31 21:10:33 +00:00
op(0x78, "in ", A, IC)
op(0x79, "out ", IC, A)
Update to v101r22 release. byuu says: Changelog: - Z80: all 25 remaining instructions implemented Now onto the debugging ... :/
2016-11-01 11:42:25 +00:00
op(0x7a, "adc ", HL, SP)
op(0x7b, "ld ", SP, INN)
Update to v101r21 release. byuu says: Changelog: - Z80: emulated 83 new instructions - Z80: timing improvements DAA is a skeleton implementation to complete the normal opcode set. Also worth noting that I don't know exactly what the hell RETI is doing, so for now it acts like RET. RETN probably needs some special handling besides just setting IFF1=IFF2 as well. I'm now missing 24 ED-prefix instructions, plus DAA, for a total of 25 opcodes remaining. And then, of course, several weeks worth of debugging all of the inevitable bugs in the core.
2016-10-31 21:10:33 +00:00
op(0x7c, "neg ")
op(0x7d, "reti")
op(0x7e, "im ", "2")
Update to v101r22 release. byuu says: Changelog: - Z80: all 25 remaining instructions implemented Now onto the debugging ... :/
2016-11-01 11:42:25 +00:00
op(0x7f, "nop ")
Update to v101r20 release. byuu says: Changelog: - Z80: emulated 272 new instructions - hiro/GTK: fixed v101r19 Linux regression [thanks, SuperMikeMan!]
2016-10-29 00:33:30 +00:00
op(0xa0, "ldi ")
op(0xa1, "cpi ")
op(0xa2, "ini ")
op(0xa3, "outi")
op(0xa8, "ldd ")
op(0xa9, "cpd ")
op(0xaa, "ind ")
op(0xab, "outd")
op(0xb0, "ldir")
op(0xb1, "cpir")
op(0xb2, "inir")
op(0xb3, "otir")
op(0xb8, "lddr")
op(0xb9, "cpdr")
op(0xba, "indr")
op(0xbb, "otdr")
Update to v101r13 release. byuu says: Changelog: - MS: added ms/bus - Z80: implemented JP/JR/CP/DI/IM/IN instructions - MD/VDP: added window layer emulation - MD/controller/gamepad: fixed d2,d3 bits (Altered Beast requires this) The Z80 is definitely a lot nastier than the LR35902. There's a lot of table duplication with HL→IX→IY; and two of them nest two levels deep (eg FD CB xx xx), so the design may change as I implement more.
2016-08-27 04:48:21 +00:00
}
Update to v101r22 release. byuu says: Changelog: - Z80: all 25 remaining instructions implemented Now onto the debugging ... :/
2016-11-01 11:42:25 +00:00
return {"nop ", "(ed ", hex(code, 2L), ")"};
Update to v101r13 release. byuu says: Changelog: - MS: added ms/bus - Z80: implemented JP/JR/CP/DI/IM/IN instructions - MD/VDP: added window layer emulation - MD/controller/gamepad: fixed d2,d3 bits (Altered Beast requires this) The Z80 is definitely a lot nastier than the LR35902. There's a lot of table duplication with HL→IX→IY; and two of them nest two levels deep (eg FD CB xx xx), so the design may change as I implement more.
2016-08-27 04:48:21 +00:00
}
Update to v101r15 release. byuu says: Changelog: - added (poorly-named) castable<To, With> template - Z80 debugger rewritten to make declaring instructions much simpler - Z80 has more instructions implemented; supports displacement on (IX), (IY) now - added `Processor::M68K::Bus` to mirror `Processor::Z80::Bus` - it does add a pointer indirection; so I'm not sure if I want to do this for all of my emulator cores ...
2016-09-04 13:51:27 +00:00
#undef op
#undef N
#undef IN
#undef NN
#undef INN
Update to v101r22 release. byuu says: Changelog: - Z80: all 25 remaining instructions implemented Now onto the debugging ... :/
2016-11-01 11:42:25 +00:00
#undef REL
Update to v101r15 release. byuu says: Changelog: - added (poorly-named) castable<To, With> template - Z80 debugger rewritten to make declaring instructions much simpler - Z80 has more instructions implemented; supports displacement on (IX), (IY) now - added `Processor::M68K::Bus` to mirror `Processor::Z80::Bus` - it does add a pointer indirection; so I'm not sure if I want to do this for all of my emulator cores ...
2016-09-04 13:51:27 +00:00
Update to v101r16 release. byuu says: Changelog: - Z80: implemented 113 new instructions (all the easy LD/ADC/ADD/AND/OR/SBC/SUB/XOR ones) - Z80: used alternative to castable<To, With> type (manual cast inside instruction() register macros) - Z80: debugger: used register macros to reduce typing and increase readability - Z80: debugger: smarter way of handling multiple DD/FD prefixes (using gotos, yay!) - ruby: fixed crash with Windows input driver on exit (from SuperMikeMan) I have no idea how the P/V flag is supposed to work on AND/OR/XOR, so that's probably wrong for now. HALT is also mostly a dummy function for now. But I typically implement those inside instruction(), so it probably won't need to be changed? We'll see.
2016-09-06 00:09:33 +00:00
#undef A
#undef F
#undef B
#undef C
#undef D
#undef E
Update to v101r14 release. byuu says: Changelog: - rewrote the Z80 core to properly handle 0xDD (IX0 and 0xFD (IY) prefixes - added Processor::Z80::Bus as a new type of abstraction - all of the instructions implemented have their proper T-cycle counts now - added nall/certificates for my public keys The goal of `Processor::Z80::Bus` is to simulate the opcode fetches being 2-read + 2-wait states; operand+regular reads/writes being 3-read. For now, this puts the cycle counts inside the CPU core. At the moment, I can't think of any CPU core where this wouldn't be appropriate. But it's certainly possible that such a case exists. So this may not be the perfect solution. The reason for having it be a subclass of Processor::Z80 instead of virtual functions for the MasterSystem::CPU core to define is due to naming conflicts. I wanted the core to say `in(addr)` and have it take the four clocks. But I also wanted a version of the function that didn't consume time when called. One way to do that would be for the core to call `Z80::in(addr)`, which then calls the regular `in(addr)` that goes to `MasterSystem::CPU::in(addr)`. But I don't want to put the `Z80::` prefix on all of the opcodes. Very easy to forget it, and then end up not consuming any time. Another is to use uglier names in the `MasterSystem::CPU` core, like `read_`, `write_`, `in_`, `out_`, etc. But, yuck. So ... yeah, this is an experiment. We'll see how it goes.
2016-09-03 11:26:04 +00:00
#undef H
#undef L
Update to v101r17 release. byuu says: Changelog: - Z80: added most opcodes between 0x00 and 0x3f (two or three hard ones missing still) - Z80: redid register declaration *again* to handle AF', BC', DE', HL' (ugggggh, the fuck? Alternate registers??) - basically, using `#define <register name>` values to get around horrendously awful naming syntax - Z80: improved handling of displace() so that it won't ever trigger on (BC) or (DE)
2016-09-06 13:53:14 +00:00
#undef _H
#undef _L
#undef _HL
Update to v101r16 release. byuu says: Changelog: - Z80: implemented 113 new instructions (all the easy LD/ADC/ADD/AND/OR/SBC/SUB/XOR ones) - Z80: used alternative to castable<To, With> type (manual cast inside instruction() register macros) - Z80: debugger: used register macros to reduce typing and increase readability - Z80: debugger: smarter way of handling multiple DD/FD prefixes (using gotos, yay!) - ruby: fixed crash with Windows input driver on exit (from SuperMikeMan) I have no idea how the P/V flag is supposed to work on AND/OR/XOR, so that's probably wrong for now. HALT is also mostly a dummy function for now. But I typically implement those inside instruction(), so it probably won't need to be changed? We'll see.
2016-09-06 00:09:33 +00:00
#undef AF
#undef BC
#undef DE
Update to v101r14 release. byuu says: Changelog: - rewrote the Z80 core to properly handle 0xDD (IX0 and 0xFD (IY) prefixes - added Processor::Z80::Bus as a new type of abstraction - all of the instructions implemented have their proper T-cycle counts now - added nall/certificates for my public keys The goal of `Processor::Z80::Bus` is to simulate the opcode fetches being 2-read + 2-wait states; operand+regular reads/writes being 3-read. For now, this puts the cycle counts inside the CPU core. At the moment, I can't think of any CPU core where this wouldn't be appropriate. But it's certainly possible that such a case exists. So this may not be the perfect solution. The reason for having it be a subclass of Processor::Z80 instead of virtual functions for the MasterSystem::CPU core to define is due to naming conflicts. I wanted the core to say `in(addr)` and have it take the four clocks. But I also wanted a version of the function that didn't consume time when called. One way to do that would be for the core to call `Z80::in(addr)`, which then calls the regular `in(addr)` that goes to `MasterSystem::CPU::in(addr)`. But I don't want to put the `Z80::` prefix on all of the opcodes. Very easy to forget it, and then end up not consuming any time. Another is to use uglier names in the `MasterSystem::CPU` core, like `read_`, `write_`, `in_`, `out_`, etc. But, yuck. So ... yeah, this is an experiment. We'll see how it goes.
2016-09-03 11:26:04 +00:00
#undef HL
Update to v101r17 release. byuu says: Changelog: - Z80: added most opcodes between 0x00 and 0x3f (two or three hard ones missing still) - Z80: redid register declaration *again* to handle AF', BC', DE', HL' (ugggggh, the fuck? Alternate registers??) - basically, using `#define <register name>` values to get around horrendously awful naming syntax - Z80: improved handling of displace() so that it won't ever trigger on (BC) or (DE)
2016-09-06 13:53:14 +00:00
#undef AF_
#undef BC_
#undef DE_
#undef HL_
Update to v101r16 release. byuu says: Changelog: - Z80: implemented 113 new instructions (all the easy LD/ADC/ADD/AND/OR/SBC/SUB/XOR ones) - Z80: used alternative to castable<To, With> type (manual cast inside instruction() register macros) - Z80: debugger: used register macros to reduce typing and increase readability - Z80: debugger: smarter way of handling multiple DD/FD prefixes (using gotos, yay!) - ruby: fixed crash with Windows input driver on exit (from SuperMikeMan) I have no idea how the P/V flag is supposed to work on AND/OR/XOR, so that's probably wrong for now. HALT is also mostly a dummy function for now. But I typically implement those inside instruction(), so it probably won't need to be changed? We'll see.
2016-09-06 00:09:33 +00:00
#undef SP
Update to v101r17 release. byuu says: Changelog: - Z80: added most opcodes between 0x00 and 0x3f (two or three hard ones missing still) - Z80: redid register declaration *again* to handle AF', BC', DE', HL' (ugggggh, the fuck? Alternate registers??) - basically, using `#define <register name>` values to get around horrendously awful naming syntax - Z80: improved handling of displace() so that it won't ever trigger on (BC) or (DE)
2016-09-06 13:53:14 +00:00
#undef PC
Update to v101r16 release. byuu says: Changelog: - Z80: implemented 113 new instructions (all the easy LD/ADC/ADD/AND/OR/SBC/SUB/XOR ones) - Z80: used alternative to castable<To, With> type (manual cast inside instruction() register macros) - Z80: debugger: used register macros to reduce typing and increase readability - Z80: debugger: smarter way of handling multiple DD/FD prefixes (using gotos, yay!) - ruby: fixed crash with Windows input driver on exit (from SuperMikeMan) I have no idea how the P/V flag is supposed to work on AND/OR/XOR, so that's probably wrong for now. HALT is also mostly a dummy function for now. But I typically implement those inside instruction(), so it probably won't need to be changed? We'll see.
2016-09-06 00:09:33 +00:00
Update to v101r22 release. byuu says: Changelog: - Z80: all 25 remaining instructions implemented Now onto the debugging ... :/
2016-11-01 11:42:25 +00:00
#undef I
#undef R
Update to v101r21 release. byuu says: Changelog: - Z80: emulated 83 new instructions - Z80: timing improvements DAA is a skeleton implementation to complete the normal opcode set. Also worth noting that I don't know exactly what the hell RETI is doing, so for now it acts like RET. RETN probably needs some special handling besides just setting IFF1=IFF2 as well. I'm now missing 24 ED-prefix instructions, plus DAA, for a total of 25 opcodes remaining. And then, of course, several weeks worth of debugging all of the inevitable bugs in the core.
2016-10-31 21:10:33 +00:00
#undef IC
Update to v101r17 release. byuu says: Changelog: - Z80: added most opcodes between 0x00 and 0x3f (two or three hard ones missing still) - Z80: redid register declaration *again* to handle AF', BC', DE', HL' (ugggggh, the fuck? Alternate registers??) - basically, using `#define <register name>` values to get around horrendously awful naming syntax - Z80: improved handling of displace() so that it won't ever trigger on (BC) or (DE)
2016-09-06 13:53:14 +00:00
#undef IBC
#undef IDE
Update to v101r15 release. byuu says: Changelog: - added (poorly-named) castable<To, With> template - Z80 debugger rewritten to make declaring instructions much simpler - Z80 has more instructions implemented; supports displacement on (IX), (IY) now - added `Processor::M68K::Bus` to mirror `Processor::Z80::Bus` - it does add a pointer indirection; so I'm not sure if I want to do this for all of my emulator cores ...
2016-09-04 13:51:27 +00:00
#undef IHL
Update to v101r17 release. byuu says: Changelog: - Z80: added most opcodes between 0x00 and 0x3f (two or three hard ones missing still) - Z80: redid register declaration *again* to handle AF', BC', DE', HL' (ugggggh, the fuck? Alternate registers??) - basically, using `#define <register name>` values to get around horrendously awful naming syntax - Z80: improved handling of displace() so that it won't ever trigger on (BC) or (DE)
2016-09-06 13:53:14 +00:00
#undef ISP