mirror of https://github.com/bsnes-emu/bsnes.git
Update to v101r27 release.
byuu says:
Changelog:
- SMS: emulated the generic Sega memory mapper (none of the more
limited forms of it yet)
- (missing ROM shift, ROM write enable emulation -- no commercial
games use either, though)
- SMS: bus I/O returns 0xff instead of 0x00 so games don't think every
key is being pressed at once
- (this is a hack until I implement proper controller pad reading)
- SMS: very limited protection against reading/writing past the end of
ROM/RAM (todo: should mirror)
- SMS: VDP background HSCROLL subtracts, rather than adds, to the
offset (unlike VSCROLL)
- SMS: VDP VSCROLL is 9-bit, modulates voffset+vscroll to 224 in
192-line mode (32x28 tilemap)
- SMS: VDP tiledata for backgrounds and sprites use `7-(x&7)` rather
than `(x&7)`
- SMS: fix output color to be 6-bit rather than 5-bit
- SMS: left clip uses register `#7`, not palette color `#7`
- (todo: do we want `color[reg7]` or `color[16 + reg7]`?)
- SMS: refined handling of 0xcb, 0xed prefixes in the Z80 core and its
disassembler
- SMS: emulated (0xfd, 0xdd) 0xcb opcodes 0x00-0x0f (still missing
0x10-0xff)
- SMS: fixed 0xcb 0b-----110 opcodes to use direct HL and never allow
(IX,IY)+d
- SMS: fixed major logic bug in (IX,IY)+d displacement
- (was using `read(x)` instead of `operand()` for the displacement
byte fetch before)
- icarus: fake there always being 32KiB of RAM in all SMS cartridges
for the time being
- (not sure how to detect this stuff yet; although I've read it's
not even really possible `>_>`)
TODO: remove processor/z80/dissassembler.cpp code block at line 396 (as it's unnecessary.)
Lots of commercial games are starting to show trashed graphical output now.
This commit is contained in:
Tim Allen
parent
5bdf55f08f
commit
569f5abc28
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@ -12,7 +12,7 @@ using namespace nall;
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namespace Emulator {
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static const string Name = "higan";
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static const string Version = "101.26";
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static const string Version = "101.27";
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static const string Author = "byuu";
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static const string License = "GPLv3";
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static const string Website = "http://byuu.org/";
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@ -5,13 +5,14 @@ namespace MasterSystem {
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Bus bus;
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auto Bus::read(uint16 addr) -> uint8 {
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if(addr < 0xc000) return cartridge.read(addr);
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return ram[addr & 0x1fff];
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if(auto data = cartridge.read(addr)) return data();
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if(addr >= 0xc000) return ram[addr & 0x1fff];
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return 0x00;
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}
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auto Bus::write(uint16 addr, uint8 data) -> void {
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if(addr < 0xc000) return cartridge.write(addr, data);
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ram[addr & 0x1fff] = data;
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if(cartridge.write(addr, data)) return;
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if(addr >= 0xc000) ram[addr & 0x1fff] = data;
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}
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auto Bus::in(uint8 addr) -> uint8 {
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@ -31,7 +32,7 @@ auto Bus::in(uint8 addr) -> uint8 {
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}
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return 0x00;
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return 0xff;
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}
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auto Bus::out(uint8 addr, uint8 data) -> void {
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@ -3,6 +3,7 @@
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namespace MasterSystem {
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Cartridge cartridge;
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#include "mapper.cpp"
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auto Cartridge::load() -> bool {
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information = {};
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@ -73,17 +74,23 @@ auto Cartridge::unload() -> void {
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ram = {};
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}
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auto Cartridge::read(uint16 addr) -> uint8 {
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return rom.data[addr & rom.mask];
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}
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auto Cartridge::write(uint16 addr, uint8 data) -> void {
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}
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auto Cartridge::power() -> void {
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}
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auto Cartridge::reset() -> void {
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memory::fill(&mapper, sizeof(Mapper));
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mapper.romPage0 = 0;
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mapper.romPage1 = 1;
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mapper.romPage2 = 2;
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}
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auto Cartridge::Memory::read(uint addr) -> uint8 {
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if(addr < this->size) return this->data[addr];
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return 0x00;
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}
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auto Cartridge::Memory::write(uint addr, uint8 data) -> void {
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if(addr < this->size) this->data[addr] = data;
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}
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}
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@ -8,12 +8,13 @@ struct Cartridge {
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auto save() -> void;
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auto unload() -> void;
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auto read(uint16 addr) -> uint8;
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auto write(uint16 addr, uint8 data) -> void;
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auto power() -> void;
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auto reset() -> void;
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//mapper.cpp
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auto read(uint16 addr) -> maybe<uint8>;
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auto write(uint16 addr, uint8 data) -> bool;
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private:
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struct Information {
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uint pathID = 0;
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@ -26,10 +27,31 @@ private:
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uint8* data = nullptr;
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uint size = 0;
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uint mask = 0;
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auto read(uint addr) -> uint8;
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auto write(uint addr, uint8 data) -> void;
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};
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Memory rom;
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Memory ram;
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struct Mapper {
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//$fffc
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uint2 shift;
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uint1 ramPage2;
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uint1 ramEnablePage2;
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uint1 ramEnablePage3;
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uint1 romWriteEnable;
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//$fffd
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uint8 romPage0;
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//$fffe
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uint8 romPage1;
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//$ffff
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uint8 romPage2;
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} mapper;
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};
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extern Cartridge cartridge;
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@ -0,0 +1,92 @@
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auto Cartridge::read(uint16 addr) -> maybe<uint8> {
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uint2 page = addr >> 14;
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addr &= 0x3fff;
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switch(page) {
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case 0: {
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if(addr <= 0x03ff) return rom.read(addr);
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return rom.read(mapper.romPage0 << 14 | addr);
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}
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case 1: {
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return rom.read(mapper.romPage1 << 14 | addr);
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}
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case 2: {
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if(mapper.ramEnablePage2) {
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return ram.read(mapper.ramPage2 << 14 | addr);
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}
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return rom.read(mapper.romPage2 << 14 | addr);
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}
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case 3: {
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if(mapper.ramEnablePage3) {
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return ram.read(addr);
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}
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return nothing;
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}
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}
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unreachable;
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}
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auto Cartridge::write(uint16 addr, uint8 data) -> bool {
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if(addr == 0xfffc) {
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mapper.shift = data.bits(0,1);
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mapper.ramPage2 = data.bit(2);
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mapper.ramEnablePage2 = data.bit(3);
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mapper.ramEnablePage3 = data.bit(4);
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mapper.romWriteEnable = data.bit(7);
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}
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if(addr == 0xfffd) {
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mapper.romPage0 = data;
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}
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if(addr == 0xfffe) {
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mapper.romPage1 = data;
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}
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if(addr == 0xffff) {
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mapper.romPage2 = data;
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}
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uint2 page = addr >> 14;
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addr &= 0x3fff;
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switch(page) {
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case 0: {
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return false;
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}
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case 1: {
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return false;
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}
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case 2: {
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if(mapper.ramEnablePage2) {
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ram.write(mapper.ramPage2 << 14 | addr, data);
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return true;
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}
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return false;
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}
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case 3: {
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if(mapper.ramEnablePage3) {
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ram.write(addr, data);
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return true;
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}
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return false;
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}
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}
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unreachable;
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}
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@ -12,15 +12,17 @@ auto VDP::Background::run() -> void {
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}
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uint8 hoffset = state.x;
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if(!vdp.io.horizontalScrollLock || hoffset >= 16) hoffset += vdp.io.hscroll;
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if(!vdp.io.horizontalScrollLock || hoffset >= 16) hoffset -= vdp.io.hscroll;
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uint8 voffset = state.y;
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uint9 voffset = state.y;
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if(!vdp.io.verticalScrollLock || hoffset <= 191) voffset += vdp.io.vscroll;
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uint14 nameTableAddress;
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if(vdp.vlines() == 192) {
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if(voffset >= 224) voffset -= 224;
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nameTableAddress = vdp.io.nameTableAddress << 11;
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} else {
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voffset &= 255;
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nameTableAddress = (vdp.io.nameTableAddress & ~1) << 11 | 0x700;
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}
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nameTableAddress += ((voffset >> 3) << 6) + ((hoffset >> 3) << 1);
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output.palette = tiledata.bit(11);
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output.priority = tiledata.bit(12);
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auto index = hoffset & 7;
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auto index = 7 - (hoffset & 7);
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patternAddress += (voffset & 7) << 2;
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output.color.bit(0) = vdp.vram[patternAddress + 0].bit(index);
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output.color.bit(1) = vdp.vram[patternAddress + 1].bit(index);
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@ -43,11 +43,12 @@ auto VDP::Sprite::run() -> void {
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address += o.pattern << 5;
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address += (y & (large ? 15 : 7)) << 2;
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auto index = 7 - (x & 7);
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uint4 color;
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color.bit(0) = vdp.vram[address + 0].bit(x & 7);
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color.bit(1) = vdp.vram[address + 1].bit(x & 7);
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color.bit(2) = vdp.vram[address + 2].bit(x & 7);
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color.bit(3) = vdp.vram[address + 3].bit(x & 7);
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color.bit(0) = vdp.vram[address + 0].bit(index);
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color.bit(1) = vdp.vram[address + 1].bit(index);
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color.bit(2) = vdp.vram[address + 2].bit(index);
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color.bit(3) = vdp.vram[address + 3].bit(index);
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if(color == 0) continue;
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if(output.color) {
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sprite.run();
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step(2);
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uint5 color = cram[16 | io.backdropColor];
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uint6 color = cram[io.backdropColor];
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if(background.output.color && (background.output.priority || !sprite.output.color)) {
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color = cram[background.output.palette << 4 | background.output.color];
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} else if(sprite.output.color) {
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color = cram[16 | sprite.output.color];
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}
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if(x <= 7 && io.leftClip) color = cram[7];
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if(x <= 7 && io.leftClip) color = cram[io.backdropColor];
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if(!io.displayEnable) color = 0;
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buffer[io.vcounter * 256 + x] = color;
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}
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@ -1,5 +1,5 @@
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auto Z80::disassemble(uint16 pc) -> string {
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string s;
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string s, output;
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s.append(hex(pc, 4L), " ");
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uint8 prefix = 0x00;
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}
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}
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s.append(pad(disassemble__(pc, prefix, code), -18L, ' '));
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if(code == 0xcb && prefix) {
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auto d = (int8)code;
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code = bus->read(pc++);
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output = disassembleCBd(pc, prefix, d, code);
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} else if(code == 0xcb) {
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code = bus->read(pc++);
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output = disassembleCB(pc, prefix, code);
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} else if(code == 0xed) {
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code = bus->read(pc++);
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output = disassembleED(pc, prefix, code);
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} else {
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output = disassemble(pc, prefix, code);
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}
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s.append(pad(output, -18L, ' '));
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finish:
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s.append(" AF:", hex(r.af.word, 4L));
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@ -76,7 +90,7 @@ auto Z80::disassemble(uint16 pc) -> string {
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#define IHL string{"(", HL, displace(), ")"}
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#define ISP "(sp)"
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auto Z80::disassemble__(uint16 pc, uint8 prefix, uint8 code) -> string {
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auto Z80::disassemble(uint16 pc, uint8 prefix, uint8 code) -> string {
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auto byte = [&] {
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return bus->read(pc++);
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};
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@ -97,9 +111,6 @@ auto Z80::disassemble__(uint16 pc, uint8 prefix, uint8 code) -> string {
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return d >= 0 ? string{"+$", hex(d, 2L)} : string{"-$", hex(-d, 2L)};
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};
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if(code == 0xcb) return code = byte(), disassembleCB(pc, prefix, code);
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if(code == 0xed) return code = byte(), disassembleED(pc, prefix, code);
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switch(code) {
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op(0x00, "nop ")
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op(0x01, "ld ", BC, NN)
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@ -382,6 +393,12 @@ auto Z80::disassembleCB(uint16 pc, uint8 prefix, uint8 code) -> string {
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return d >= 0 ? string{"+$", hex(d, 2L)} : string{"-$", hex(-d, 2L)};
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};
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if(prefix) {
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auto d = (int8)code;
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string ds = d >= 0 ? string{"+$", hex(d, 2L)} : string{"-$", hex(-d, 2L)};
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return {"rlc (", HL, ds, ")"};
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}
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switch(code) {
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op(0x00, "rlc ", B)
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op(0x01, "rlc ", C)
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@ -644,6 +661,33 @@ auto Z80::disassembleCB(uint16 pc, uint8 prefix, uint8 code) -> string {
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unreachable;
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}
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auto Z80::disassembleCBd(uint16 pc, uint8 prefix, int8 d, uint8 code) -> string {
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auto displace = [&] {
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return d >= 0 ? string{"+$", hex(d, 2L)} : string{"-$", hex(-d, 2L)};
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};
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switch(code) {
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op(0x00, "rlc ", IHL, B)
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op(0x01, "rlc ", IHL, C)
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op(0x02, "rlc ", IHL, D)
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op(0x03, "rlc ", IHL, E)
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op(0x04, "rlc ", IHL, H)
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op(0x05, "rlc ", IHL, L)
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op(0x06, "rlc ", IHL)
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op(0x07, "rlc ", IHL, A)
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op(0x08, "rrc ", IHL, B)
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op(0x09, "rrc ", IHL, C)
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op(0x0a, "rrc ", IHL, D)
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op(0x0b, "rrc ", IHL, E)
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op(0x0c, "rrc ", IHL, H)
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op(0x0d, "rrc ", IHL, L)
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op(0x0e, "rrc ", IHL)
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op(0x0f, "rrc ", IHL, A)
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}
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return {"???"};
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}
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auto Z80::disassembleED(uint16 pc, uint8 prefix, uint8 code) -> string {
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auto byte = [&] {
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return bus->read(pc++);
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@ -9,13 +9,24 @@ auto Z80::instruction() -> void {
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r.iff2 = 1;
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}
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instruction__(code);
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if(code == 0xcb && r.hlp != &r.hl) {
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uint16 addr = HL + (int8)operand();
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wait(1);
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instructionCBd(addr, opcode());
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} else if(code == 0xcb) {
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instructionCB(opcode());
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} else if(code == 0xed) {
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instructionED(opcode());
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} else {
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instruction(code);
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}
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r.hlp = &r.hl;
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}
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#define op(id, name, ...) case id: return instruction##name(__VA_ARGS__);
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auto Z80::instruction__(uint8 code) -> void {
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auto Z80::instruction(uint8 code) -> void {
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switch(code) {
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op(0x00, NOP)
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op(0x01, LD_rr_nn, BC)
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@ -220,7 +231,7 @@ auto Z80::instruction__(uint8 code) -> void {
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op(0xc8, RET_c, ZF == 1)
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op(0xc9, RET)
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op(0xca, JP_c_nn, ZF == 1)
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op(0xcb, CB, opcode())
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//op(0xcb, cb:)
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op(0xcc, CALL_c_nn, ZF == 1)
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op(0xcd, CALL_nn)
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op(0xce, ADC_a_n)
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@ -253,7 +264,7 @@ auto Z80::instruction__(uint8 code) -> void {
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op(0xea, JP_c_nn, PF == 1)
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op(0xeb, EX_rr_rr, DE, _HL)
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op(0xec, CALL_c_nn, PF == 1)
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op(0xed, ED, opcode())
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//op(0xed, ed:)
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op(0xee, XOR_a_n)
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op(0xef, RST_o, 5)
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op(0xf0, RET_c, SF == 0)
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@ -283,7 +294,7 @@ auto Z80::instructionCB(uint8 code) -> void {
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op(0x03, RLC_r, E)
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op(0x04, RLC_r, H)
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op(0x05, RLC_r, L)
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op(0x06, RLC_irr, HL)
|
||||
op(0x06, RLC_irr, _HL)
|
||||
op(0x07, RLC_r, A)
|
||||
op(0x08, RRC_r, B)
|
||||
op(0x09, RRC_r, C)
|
||||
|
|
@ -291,7 +302,7 @@ auto Z80::instructionCB(uint8 code) -> void {
|
|||
op(0x0b, RRC_r, E)
|
||||
op(0x0c, RRC_r, H)
|
||||
op(0x0d, RRC_r, L)
|
||||
op(0x0e, RRC_irr, HL)
|
||||
op(0x0e, RRC_irr, _HL)
|
||||
op(0x0f, RRC_r, A)
|
||||
op(0x10, RL_r, B)
|
||||
op(0x11, RL_r, C)
|
||||
|
|
@ -299,7 +310,7 @@ auto Z80::instructionCB(uint8 code) -> void {
|
|||
op(0x13, RL_r, E)
|
||||
op(0x14, RL_r, H)
|
||||
op(0x15, RL_r, L)
|
||||
op(0x16, RL_irr, HL)
|
||||
op(0x16, RL_irr, _HL)
|
||||
op(0x17, RL_r, A)
|
||||
op(0x18, RR_r, B)
|
||||
op(0x19, RR_r, C)
|
||||
|
|
@ -307,7 +318,7 @@ auto Z80::instructionCB(uint8 code) -> void {
|
|||
op(0x1b, RR_r, E)
|
||||
op(0x1c, RR_r, H)
|
||||
op(0x1d, RR_r, L)
|
||||
op(0x1e, RR_irr, HL)
|
||||
op(0x1e, RR_irr, _HL)
|
||||
op(0x1f, RR_r, A)
|
||||
op(0x20, SLA_r, B)
|
||||
op(0x21, SLA_r, C)
|
||||
|
|
@ -315,7 +326,7 @@ auto Z80::instructionCB(uint8 code) -> void {
|
|||
op(0x23, SLA_r, E)
|
||||
op(0x24, SLA_r, H)
|
||||
op(0x25, SLA_r, L)
|
||||
op(0x26, SLA_irr, HL)
|
||||
op(0x26, SLA_irr, _HL)
|
||||
op(0x27, SLA_r, A)
|
||||
op(0x28, SRA_r, B)
|
||||
op(0x29, SRA_r, C)
|
||||
|
|
@ -323,7 +334,7 @@ auto Z80::instructionCB(uint8 code) -> void {
|
|||
op(0x2b, SRA_r, E)
|
||||
op(0x2c, SRA_r, H)
|
||||
op(0x2d, SRA_r, L)
|
||||
op(0x2e, SRA_irr, HL)
|
||||
op(0x2e, SRA_irr, _HL)
|
||||
op(0x2f, SRA_r, A)
|
||||
op(0x30, SLL_r, B)
|
||||
op(0x31, SLL_r, C)
|
||||
|
|
@ -331,7 +342,7 @@ auto Z80::instructionCB(uint8 code) -> void {
|
|||
op(0x33, SLL_r, E)
|
||||
op(0x34, SLL_r, H)
|
||||
op(0x35, SLL_r, L)
|
||||
op(0x36, SLL_irr, HL)
|
||||
op(0x36, SLL_irr, _HL)
|
||||
op(0x37, SLL_r, A)
|
||||
op(0x38, SRL_r, B)
|
||||
op(0x39, SRL_r, C)
|
||||
|
|
@ -339,7 +350,7 @@ auto Z80::instructionCB(uint8 code) -> void {
|
|||
op(0x3b, SRL_r, E)
|
||||
op(0x3c, SRL_r, H)
|
||||
op(0x3d, SRL_r, L)
|
||||
op(0x3e, SRL_irr, HL)
|
||||
op(0x3e, SRL_irr, _HL)
|
||||
op(0x3f, SRL_r, A)
|
||||
op(0x40, BIT_o_r, 0, B)
|
||||
op(0x41, BIT_o_r, 0, C)
|
||||
|
|
@ -347,7 +358,7 @@ auto Z80::instructionCB(uint8 code) -> void {
|
|||
op(0x43, BIT_o_r, 0, E)
|
||||
op(0x44, BIT_o_r, 0, H)
|
||||
op(0x45, BIT_o_r, 0, L)
|
||||
op(0x46, BIT_o_irr, 0, HL)
|
||||
op(0x46, BIT_o_irr, 0, _HL)
|
||||
op(0x47, BIT_o_r, 0, A)
|
||||
op(0x48, BIT_o_r, 1, B)
|
||||
op(0x49, BIT_o_r, 1, C)
|
||||
|
|
@ -355,7 +366,7 @@ auto Z80::instructionCB(uint8 code) -> void {
|
|||
op(0x4b, BIT_o_r, 1, E)
|
||||
op(0x4c, BIT_o_r, 1, H)
|
||||
op(0x4d, BIT_o_r, 1, L)
|
||||
op(0x4e, BIT_o_irr, 1, HL)
|
||||
op(0x4e, BIT_o_irr, 1, _HL)
|
||||
op(0x4f, BIT_o_r, 1, A)
|
||||
op(0x50, BIT_o_r, 2, B)
|
||||
op(0x51, BIT_o_r, 2, C)
|
||||
|
|
@ -363,7 +374,7 @@ auto Z80::instructionCB(uint8 code) -> void {
|
|||
op(0x53, BIT_o_r, 2, E)
|
||||
op(0x54, BIT_o_r, 2, H)
|
||||
op(0x55, BIT_o_r, 2, L)
|
||||
op(0x56, BIT_o_irr, 2, HL)
|
||||
op(0x56, BIT_o_irr, 2, _HL)
|
||||
op(0x57, BIT_o_r, 2, A)
|
||||
op(0x58, BIT_o_r, 3, B)
|
||||
op(0x59, BIT_o_r, 3, C)
|
||||
|
|
@ -371,7 +382,7 @@ auto Z80::instructionCB(uint8 code) -> void {
|
|||
op(0x5b, BIT_o_r, 3, E)
|
||||
op(0x5c, BIT_o_r, 3, H)
|
||||
op(0x5d, BIT_o_r, 3, L)
|
||||
op(0x5e, BIT_o_irr, 3, HL)
|
||||
op(0x5e, BIT_o_irr, 3, _HL)
|
||||
op(0x5f, BIT_o_r, 3, A)
|
||||
op(0x60, BIT_o_r, 4, B)
|
||||
op(0x61, BIT_o_r, 4, C)
|
||||
|
|
@ -379,7 +390,7 @@ auto Z80::instructionCB(uint8 code) -> void {
|
|||
op(0x63, BIT_o_r, 4, E)
|
||||
op(0x64, BIT_o_r, 4, H)
|
||||
op(0x65, BIT_o_r, 4, L)
|
||||
op(0x66, BIT_o_irr, 4, HL)
|
||||
op(0x66, BIT_o_irr, 4, _HL)
|
||||
op(0x67, BIT_o_r, 4, A)
|
||||
op(0x68, BIT_o_r, 5, B)
|
||||
op(0x69, BIT_o_r, 5, C)
|
||||
|
|
@ -387,7 +398,7 @@ auto Z80::instructionCB(uint8 code) -> void {
|
|||
op(0x6b, BIT_o_r, 5, E)
|
||||
op(0x6c, BIT_o_r, 5, H)
|
||||
op(0x6d, BIT_o_r, 5, L)
|
||||
op(0x6e, BIT_o_irr, 5, HL)
|
||||
op(0x6e, BIT_o_irr, 5, _HL)
|
||||
op(0x6f, BIT_o_r, 5, A)
|
||||
op(0x70, BIT_o_r, 6, B)
|
||||
op(0x71, BIT_o_r, 6, C)
|
||||
|
|
@ -395,7 +406,7 @@ auto Z80::instructionCB(uint8 code) -> void {
|
|||
op(0x73, BIT_o_r, 6, E)
|
||||
op(0x74, BIT_o_r, 6, H)
|
||||
op(0x75, BIT_o_r, 6, L)
|
||||
op(0x76, BIT_o_irr, 6, HL)
|
||||
op(0x76, BIT_o_irr, 6, _HL)
|
||||
op(0x77, BIT_o_r, 6, A)
|
||||
op(0x78, BIT_o_r, 7, B)
|
||||
op(0x79, BIT_o_r, 7, C)
|
||||
|
|
@ -403,7 +414,7 @@ auto Z80::instructionCB(uint8 code) -> void {
|
|||
op(0x7b, BIT_o_r, 7, E)
|
||||
op(0x7c, BIT_o_r, 7, H)
|
||||
op(0x7d, BIT_o_r, 7, L)
|
||||
op(0x7e, BIT_o_irr, 7, HL)
|
||||
op(0x7e, BIT_o_irr, 7, _HL)
|
||||
op(0x7f, BIT_o_r, 7, A)
|
||||
op(0x80, RES_o_r, 0, B)
|
||||
op(0x81, RES_o_r, 0, C)
|
||||
|
|
@ -411,7 +422,7 @@ auto Z80::instructionCB(uint8 code) -> void {
|
|||
op(0x83, RES_o_r, 0, E)
|
||||
op(0x84, RES_o_r, 0, H)
|
||||
op(0x85, RES_o_r, 0, L)
|
||||
op(0x86, RES_o_irr, 0, HL)
|
||||
op(0x86, RES_o_irr, 0, _HL)
|
||||
op(0x87, RES_o_r, 0, A)
|
||||
op(0x88, RES_o_r, 1, B)
|
||||
op(0x89, RES_o_r, 1, C)
|
||||
|
|
@ -419,7 +430,7 @@ auto Z80::instructionCB(uint8 code) -> void {
|
|||
op(0x8b, RES_o_r, 1, E)
|
||||
op(0x8c, RES_o_r, 1, H)
|
||||
op(0x8d, RES_o_r, 1, L)
|
||||
op(0x8e, RES_o_irr, 1, HL)
|
||||
op(0x8e, RES_o_irr, 1, _HL)
|
||||
op(0x8f, RES_o_r, 1, A)
|
||||
op(0x90, RES_o_r, 2, B)
|
||||
op(0x91, RES_o_r, 2, C)
|
||||
|
|
@ -427,7 +438,7 @@ auto Z80::instructionCB(uint8 code) -> void {
|
|||
op(0x93, RES_o_r, 2, E)
|
||||
op(0x94, RES_o_r, 2, H)
|
||||
op(0x95, RES_o_r, 2, L)
|
||||
op(0x96, RES_o_irr, 2, HL)
|
||||
op(0x96, RES_o_irr, 2, _HL)
|
||||
op(0x97, RES_o_r, 2, A)
|
||||
op(0x98, RES_o_r, 3, B)
|
||||
op(0x99, RES_o_r, 3, C)
|
||||
|
|
@ -435,7 +446,7 @@ auto Z80::instructionCB(uint8 code) -> void {
|
|||
op(0x9b, RES_o_r, 3, E)
|
||||
op(0x9c, RES_o_r, 3, H)
|
||||
op(0x9d, RES_o_r, 3, L)
|
||||
op(0x9e, RES_o_irr, 3, HL)
|
||||
op(0x9e, RES_o_irr, 3, _HL)
|
||||
op(0x9f, RES_o_r, 3, A)
|
||||
op(0xa0, RES_o_r, 4, B)
|
||||
op(0xa1, RES_o_r, 4, C)
|
||||
|
|
@ -443,7 +454,7 @@ auto Z80::instructionCB(uint8 code) -> void {
|
|||
op(0xa3, RES_o_r, 4, E)
|
||||
op(0xa4, RES_o_r, 4, H)
|
||||
op(0xa5, RES_o_r, 4, L)
|
||||
op(0xa6, RES_o_irr, 4, HL)
|
||||
op(0xa6, RES_o_irr, 4, _HL)
|
||||
op(0xa7, RES_o_r, 4, A)
|
||||
op(0xa8, RES_o_r, 5, B)
|
||||
op(0xa9, RES_o_r, 5, C)
|
||||
|
|
@ -451,7 +462,7 @@ auto Z80::instructionCB(uint8 code) -> void {
|
|||
op(0xab, RES_o_r, 5, E)
|
||||
op(0xac, RES_o_r, 5, H)
|
||||
op(0xad, RES_o_r, 5, L)
|
||||
op(0xae, RES_o_irr, 5, HL)
|
||||
op(0xae, RES_o_irr, 5, _HL)
|
||||
op(0xaf, RES_o_r, 5, A)
|
||||
op(0xb0, RES_o_r, 6, B)
|
||||
op(0xb1, RES_o_r, 6, C)
|
||||
|
|
@ -459,7 +470,7 @@ auto Z80::instructionCB(uint8 code) -> void {
|
|||
op(0xb3, RES_o_r, 6, E)
|
||||
op(0xb4, RES_o_r, 6, H)
|
||||
op(0xb5, RES_o_r, 6, L)
|
||||
op(0xb6, RES_o_irr, 6, HL)
|
||||
op(0xb6, RES_o_irr, 6, _HL)
|
||||
op(0xb7, RES_o_r, 6, A)
|
||||
op(0xb8, RES_o_r, 7, B)
|
||||
op(0xb9, RES_o_r, 7, C)
|
||||
|
|
@ -467,7 +478,7 @@ auto Z80::instructionCB(uint8 code) -> void {
|
|||
op(0xbb, RES_o_r, 7, E)
|
||||
op(0xbc, RES_o_r, 7, H)
|
||||
op(0xbd, RES_o_r, 7, L)
|
||||
op(0xbe, RES_o_irr, 7, HL)
|
||||
op(0xbe, RES_o_irr, 7, _HL)
|
||||
op(0xbf, RES_o_r, 7, A)
|
||||
op(0xc0, SET_o_r, 0, B)
|
||||
op(0xc1, SET_o_r, 0, C)
|
||||
|
|
@ -475,7 +486,7 @@ auto Z80::instructionCB(uint8 code) -> void {
|
|||
op(0xc3, SET_o_r, 0, E)
|
||||
op(0xc4, SET_o_r, 0, H)
|
||||
op(0xc5, SET_o_r, 0, L)
|
||||
op(0xc6, SET_o_irr, 0, HL)
|
||||
op(0xc6, SET_o_irr, 0, _HL)
|
||||
op(0xc7, SET_o_r, 0, A)
|
||||
op(0xc8, SET_o_r, 1, B)
|
||||
op(0xc9, SET_o_r, 1, C)
|
||||
|
|
@ -483,7 +494,7 @@ auto Z80::instructionCB(uint8 code) -> void {
|
|||
op(0xcb, SET_o_r, 1, E)
|
||||
op(0xcc, SET_o_r, 1, H)
|
||||
op(0xcd, SET_o_r, 1, L)
|
||||
op(0xce, SET_o_irr, 1, HL)
|
||||
op(0xce, SET_o_irr, 1, _HL)
|
||||
op(0xcf, SET_o_r, 1, A)
|
||||
op(0xd0, SET_o_r, 2, B)
|
||||
op(0xd1, SET_o_r, 2, C)
|
||||
|
|
@ -491,7 +502,7 @@ auto Z80::instructionCB(uint8 code) -> void {
|
|||
op(0xd3, SET_o_r, 2, E)
|
||||
op(0xd4, SET_o_r, 2, H)
|
||||
op(0xd5, SET_o_r, 2, L)
|
||||
op(0xd6, SET_o_irr, 2, HL)
|
||||
op(0xd6, SET_o_irr, 2, _HL)
|
||||
op(0xd7, SET_o_r, 2, A)
|
||||
op(0xd8, SET_o_r, 3, B)
|
||||
op(0xd9, SET_o_r, 3, C)
|
||||
|
|
@ -499,7 +510,7 @@ auto Z80::instructionCB(uint8 code) -> void {
|
|||
op(0xdb, SET_o_r, 3, E)
|
||||
op(0xdc, SET_o_r, 3, H)
|
||||
op(0xdd, SET_o_r, 3, L)
|
||||
op(0xde, SET_o_irr, 3, HL)
|
||||
op(0xde, SET_o_irr, 3, _HL)
|
||||
op(0xdf, SET_o_r, 3, A)
|
||||
op(0xe0, SET_o_r, 4, B)
|
||||
op(0xe1, SET_o_r, 4, C)
|
||||
|
|
@ -507,7 +518,7 @@ auto Z80::instructionCB(uint8 code) -> void {
|
|||
op(0xe3, SET_o_r, 4, E)
|
||||
op(0xe4, SET_o_r, 4, H)
|
||||
op(0xe5, SET_o_r, 4, L)
|
||||
op(0xe6, SET_o_irr, 4, HL)
|
||||
op(0xe6, SET_o_irr, 4, _HL)
|
||||
op(0xe7, SET_o_r, 4, A)
|
||||
op(0xe8, SET_o_r, 5, B)
|
||||
op(0xe9, SET_o_r, 5, C)
|
||||
|
|
@ -515,7 +526,7 @@ auto Z80::instructionCB(uint8 code) -> void {
|
|||
op(0xeb, SET_o_r, 5, E)
|
||||
op(0xec, SET_o_r, 5, H)
|
||||
op(0xed, SET_o_r, 5, L)
|
||||
op(0xee, SET_o_irr, 5, HL)
|
||||
op(0xee, SET_o_irr, 5, _HL)
|
||||
op(0xef, SET_o_r, 5, A)
|
||||
op(0xf0, SET_o_r, 6, B)
|
||||
op(0xf1, SET_o_r, 6, C)
|
||||
|
|
@ -523,7 +534,7 @@ auto Z80::instructionCB(uint8 code) -> void {
|
|||
op(0xf3, SET_o_r, 6, E)
|
||||
op(0xf4, SET_o_r, 6, H)
|
||||
op(0xf5, SET_o_r, 6, L)
|
||||
op(0xf6, SET_o_irr, 6, HL)
|
||||
op(0xf6, SET_o_irr, 6, _HL)
|
||||
op(0xf7, SET_o_r, 6, A)
|
||||
op(0xf8, SET_o_r, 7, B)
|
||||
op(0xf9, SET_o_r, 7, C)
|
||||
|
|
@ -531,11 +542,34 @@ auto Z80::instructionCB(uint8 code) -> void {
|
|||
op(0xfb, SET_o_r, 7, E)
|
||||
op(0xfc, SET_o_r, 7, H)
|
||||
op(0xfd, SET_o_r, 7, L)
|
||||
op(0xfe, SET_o_irr, 7, HL)
|
||||
op(0xfe, SET_o_irr, 7, _HL)
|
||||
op(0xff, SET_o_r, 7, A)
|
||||
}
|
||||
}
|
||||
|
||||
auto Z80::instructionCBd(uint16 addr, uint8 code) -> void {
|
||||
uint8 _;
|
||||
|
||||
switch(code) {
|
||||
op(0x00, RLC_irr_r, addr, B)
|
||||
op(0x01, RLC_irr_r, addr, C)
|
||||
op(0x02, RLC_irr_r, addr, D)
|
||||
op(0x03, RLC_irr_r, addr, E)
|
||||
op(0x04, RLC_irr_r, addr, H)
|
||||
op(0x05, RLC_irr_r, addr, L)
|
||||
op(0x06, RLC_irr_r, addr, _)
|
||||
op(0x07, RLC_irr_r, addr, A)
|
||||
op(0x08, RRC_irr_r, addr, B)
|
||||
op(0x09, RRC_irr_r, addr, C)
|
||||
op(0x0a, RRC_irr_r, addr, D)
|
||||
op(0x0b, RRC_irr_r, addr, E)
|
||||
op(0x0c, RRC_irr_r, addr, H)
|
||||
op(0x0d, RRC_irr_r, addr, L)
|
||||
op(0x0e, RRC_irr_r, addr, _)
|
||||
op(0x0f, RRC_irr_r, addr, A)
|
||||
}
|
||||
}
|
||||
|
||||
auto Z80::instructionED(uint8 code) -> void {
|
||||
switch(code) {
|
||||
op(0x40, IN_r_ic, B)
|
||||
|
|
|
|||
|
|
@ -738,11 +738,14 @@ auto Z80::instructionRLA() -> void {
|
|||
YF = A.bit(5);
|
||||
}
|
||||
|
||||
auto Z80::instructionRLC_irr(uint16& x) -> void {
|
||||
auto addr = displace(x);
|
||||
auto Z80::instructionRLC_irr(uint16& addr) -> void {
|
||||
write(addr, RLC(read(addr)));
|
||||
}
|
||||
|
||||
auto Z80::instructionRLC_irr_r(uint16& addr, uint8& x) -> void {
|
||||
write(addr, x = RLC(read(addr)));
|
||||
}
|
||||
|
||||
auto Z80::instructionRLC_r(uint8& x) -> void {
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||||
x = RLC(x);
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||||
}
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||||
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|
@ -794,11 +797,14 @@ auto Z80::instructionRRA() -> void {
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|||
YF = A.bit(5);
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||||
}
|
||||
|
||||
auto Z80::instructionRRC_irr(uint16& x) -> void {
|
||||
auto addr = displace(x);
|
||||
auto Z80::instructionRRC_irr(uint16& addr) -> void {
|
||||
write(addr, RRC(read(addr)));
|
||||
}
|
||||
|
||||
auto Z80::instructionRRC_irr_r(uint16& addr, uint8& x) -> void {
|
||||
write(addr, x = RRC(read(addr)));
|
||||
}
|
||||
|
||||
auto Z80::instructionRRC_r(uint8& x) -> void {
|
||||
x = RRC(x);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -29,7 +29,7 @@ auto Z80::pop() -> uint16 {
|
|||
|
||||
auto Z80::displace(uint16& x) -> uint16 {
|
||||
if(&x != &r.ix.word && &x != &r.iy.word) return x;
|
||||
auto d = read(x);
|
||||
auto d = operand();
|
||||
wait(5);
|
||||
return x + (int8)d;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -36,8 +36,9 @@ struct Z80 {
|
|||
|
||||
//instruction.cpp
|
||||
auto instruction() -> void;
|
||||
auto instruction__(uint8 code) -> void;
|
||||
auto instruction(uint8 code) -> void;
|
||||
auto instructionCB(uint8 code) -> void;
|
||||
auto instructionCBd(uint16 addr, uint8 code) -> void;
|
||||
auto instructionED(uint8 code) -> void;
|
||||
|
||||
//instructions.cpp
|
||||
|
|
@ -148,6 +149,7 @@ struct Z80 {
|
|||
auto instructionRL_r(uint8&) -> void;
|
||||
auto instructionRLA() -> void;
|
||||
auto instructionRLC_irr(uint16&) -> void;
|
||||
auto instructionRLC_irr_r(uint16&, uint8&) -> void;
|
||||
auto instructionRLC_r(uint8&) -> void;
|
||||
auto instructionRLCA() -> void;
|
||||
auto instructionRLD() -> void;
|
||||
|
|
@ -155,6 +157,7 @@ struct Z80 {
|
|||
auto instructionRR_r(uint8&) -> void;
|
||||
auto instructionRRA() -> void;
|
||||
auto instructionRRC_irr(uint16&) -> void;
|
||||
auto instructionRRC_irr_r(uint16&, uint8&) -> void;
|
||||
auto instructionRRC_r(uint8&) -> void;
|
||||
auto instructionRRCA() -> void;
|
||||
auto instructionRRD() -> void;
|
||||
|
|
@ -183,8 +186,9 @@ struct Z80 {
|
|||
|
||||
//disassembler.cpp
|
||||
auto disassemble(uint16 pc) -> string;
|
||||
auto disassemble__(uint16 pc, uint8 prefix, uint8 code) -> string;
|
||||
auto disassemble(uint16 pc, uint8 prefix, uint8 code) -> string;
|
||||
auto disassembleCB(uint16 pc, uint8 prefix, uint8 code) -> string;
|
||||
auto disassembleCBd(uint16 pc, uint8 prefix, int8 d, uint8 code) -> string;
|
||||
auto disassembleED(uint16 pc, uint8 prefix, uint8 code) -> string;
|
||||
|
||||
struct Registers {
|
||||
|
|
|
|||
|
|
@ -11,6 +11,7 @@ struct MasterSystemCartridge {
|
|||
MasterSystemCartridge::MasterSystemCartridge(string location, uint8_t* data, uint size) {
|
||||
manifest.append("board\n");
|
||||
manifest.append(" rom name=program.rom size=0x", hex(size), "\n");
|
||||
manifest.append(" ram name=save.ram size=0x8000\n");
|
||||
manifest.append("\n");
|
||||
manifest.append("information\n");
|
||||
manifest.append(" title: ", Location::prefix(location), "\n");
|
||||
|
|
|
|||
Loading…
Reference in New Issue