mirror of https://github.com/bsnes-emu/bsnes.git
Update to v101r22 release.
byuu says: Changelog: - Z80: all 25 remaining instructions implemented Now onto the debugging ... :/
This commit is contained in:
Tim Allen
parent
8cf20dabbf
commit
c2c957a9da
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@ -12,7 +12,7 @@ using namespace nall;
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namespace Emulator {
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static const string Name = "higan";
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static const string Version = "101.21";
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static const string Version = "101.22";
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static const string Author = "byuu";
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static const string License = "GPLv3";
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static const string Website = "http://byuu.org/";
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@ -40,7 +40,7 @@ auto Z80::disassemble(uint16 pc) -> string {
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#define IN string{"(", N, ")"}
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#define NN string{"$", hex(word(), 4L)}
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#define INN string{"(", NN, ")"}
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#define R string{"$", hex(branch(), 4L)}
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#define REL string{"$", hex(branch(), 4L)}
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#define A "a"
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#define F "f"
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@ -67,6 +67,9 @@ auto Z80::disassemble(uint16 pc) -> string {
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#define SP "sp"
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#define PC "pc"
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#define I "i"
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#define R "r"
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#define IC "(c)"
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#define IBC "(bc)"
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#define IDE "(de)"
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@ -114,7 +117,7 @@ auto Z80::disassemble__(uint16 pc, uint8 prefix, uint8 code) -> string {
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op(0x0d, "dec ", C)
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op(0x0e, "ld ", C, N)
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op(0x0f, "rrca")
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op(0x10, "djnz", R)
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op(0x10, "djnz", REL)
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op(0x11, "ld ", DE, NN)
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op(0x12, "ld ", IDE, A)
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op(0x13, "inc ", DE)
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@ -122,7 +125,7 @@ auto Z80::disassemble__(uint16 pc, uint8 prefix, uint8 code) -> string {
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op(0x15, "dec ", D)
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op(0x16, "ld ", E, N)
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op(0x17, "rla ")
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op(0x18, "jr ", R)
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op(0x18, "jr ", REL)
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op(0x19, "add ", HL, DE)
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op(0x1a, "ld ", A, IDE)
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op(0x1b, "dec ", DE)
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@ -130,7 +133,7 @@ auto Z80::disassemble__(uint16 pc, uint8 prefix, uint8 code) -> string {
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op(0x1d, "dec ", E)
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op(0x1e, "ld ", E, N)
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op(0x1f, "rra ")
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op(0x20, "jr ", "nz", R)
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op(0x20, "jr ", "nz", REL)
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op(0x21, "ld ", HL, NN)
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op(0x22, "ld ", INN, HL)
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op(0x23, "inc ", HL)
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@ -138,7 +141,7 @@ auto Z80::disassemble__(uint16 pc, uint8 prefix, uint8 code) -> string {
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op(0x25, "dec ", H)
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op(0x26, "ld ", H, N)
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op(0x27, "daa ")
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op(0x28, "jr ", "z", R)
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op(0x28, "jr ", "z", REL)
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op(0x29, "add ", HL, HL)
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op(0x2a, "ld ", HL, INN)
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op(0x2b, "dec ", HL)
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@ -146,7 +149,7 @@ auto Z80::disassemble__(uint16 pc, uint8 prefix, uint8 code) -> string {
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op(0x2d, "dec ", L)
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op(0x2e, "ld ", L, N)
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op(0x2f, "cpl ")
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op(0x30, "jr ", "nc", R)
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op(0x30, "jr ", "nc", REL)
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op(0x31, "ld ", SP, NN)
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op(0x32, "ld ", INN, A)
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op(0x33, "inc ", SP)
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@ -154,7 +157,7 @@ auto Z80::disassemble__(uint16 pc, uint8 prefix, uint8 code) -> string {
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op(0x35, "dec ", IHL)
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op(0x36, "ld ", IHL, N)
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op(0x37, "scf ")
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op(0x38, "jr ", "c", R)
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op(0x38, "jr ", "c", REL)
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op(0x39, "add ", HL, SP)
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op(0x3a, "ld ", A, INN)
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op(0x3b, "dec ", SP)
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@ -665,44 +668,68 @@ auto Z80::disassembleED(uint16 pc, uint8 prefix, uint8 code) -> string {
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switch(code) {
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op(0x40, "in ", B, IC)
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op(0x41, "out ", IC, B)
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op(0x42, "sbc ", HL, BC)
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op(0x43, "ld ", INN, BC)
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op(0x44, "neg ")
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op(0x45, "retn")
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op(0x46, "im ", "0")
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op(0x47, "ld ", I, A)
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op(0x48, "in ", C, IC)
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op(0x49, "out ", IC, C)
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op(0x4a, "adc ", HL, BC)
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op(0x4b, "ld ", BC, INN)
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op(0x4c, "neg ")
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op(0x4d, "reti")
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op(0x4e, "im ", "0")
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op(0x4f, "ld ", R, A)
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op(0x50, "in ", D, IC)
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op(0x51, "out ", IC, D)
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op(0x52, "sbc ", HL, DE)
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op(0x53, "ld ", INN, DE)
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op(0x54, "neg ")
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op(0x55, "retn")
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op(0x56, "im ", "1")
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op(0x57, "ld ", A, I)
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op(0x58, "in ", E, IC)
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op(0x59, "out ", IC, E)
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op(0x5a, "adc ", HL, DE)
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op(0x5b, "ld ", DE, INN)
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op(0x5c, "neg ")
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op(0x5d, "reti")
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op(0x5e, "im ", "2")
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op(0x5f, "ld ", A, R)
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op(0x60, "in ", H, IC)
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op(0x61, "out ", IC, H)
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op(0x62, "sbc ", HL, HL)
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op(0x63, "ld ", INN, HL)
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op(0x64, "neg ")
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op(0x65, "retn")
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op(0x66, "im ", "0")
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op(0x67, "rrd ")
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op(0x68, "in ", L, IC)
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op(0x69, "out ", IC, L)
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op(0x6a, "adc ", HL, HL)
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op(0x6b, "ld ", HL, INN)
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op(0x6c, "neg ")
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op(0x6d, "reti")
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op(0x6e, "im ", "0")
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op(0x6f, "rld ")
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op(0x70, "in ", F, IC)
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op(0x71, "out ", IC, F)
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op(0x72, "sbc ", HL, SP)
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op(0x73, "ld ", INN, SP)
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op(0x74, "neg ")
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op(0x75, "retn")
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op(0x76, "im ", "1")
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op(0x77, "nop ")
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op(0x78, "in ", A, IC)
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op(0x79, "out ", IC, A)
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op(0x7a, "adc ", HL, SP)
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op(0x7b, "ld ", SP, INN)
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op(0x7c, "neg ")
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op(0x7d, "reti")
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op(0x7e, "im ", "2")
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op(0x7f, "nop ")
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op(0xa0, "ldi ")
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op(0xa1, "cpi ")
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op(0xa2, "ini ")
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@ -721,7 +748,7 @@ auto Z80::disassembleED(uint16 pc, uint8 prefix, uint8 code) -> string {
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op(0xbb, "otdr")
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}
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return {"???: ed ", hex(code, 2L)};
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return {"nop ", "(ed ", hex(code, 2L), ")"};
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}
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#undef op
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@ -730,7 +757,7 @@ auto Z80::disassembleED(uint16 pc, uint8 prefix, uint8 code) -> string {
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#undef IN
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#undef NN
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#undef INN
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#undef R
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#undef REL
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#undef A
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#undef F
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@ -757,6 +784,9 @@ auto Z80::disassembleED(uint16 pc, uint8 prefix, uint8 code) -> string {
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#undef SP
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#undef PC
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#undef I
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#undef R
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#undef IC
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#undef IBC
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#undef IDE
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@ -1,9 +1,3 @@
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auto Z80::trap(uint8 prefix, uint8 code) -> void {
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print("[Z80] unimplemented instruction: ", prefix ? pad(hex(prefix, 2L), -3L, ' ') : "", hex(code, 2L), "\n");
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print("[Z80] instructions executed: ", --instructionsExecuted, "\n");
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while(true) wait();
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}
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auto Z80::instruction() -> void {
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#if 1
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if(instructionsExecuted < 20)
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@ -32,7 +26,7 @@ auto Z80::instruction__(uint8 code) -> void {
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op(0x06, LD_r_n, B)
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op(0x07, RLCA)
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op(0x08, EX_rr_rr, AF, AF_)
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op(0x09, ADD_rr_rr, HL, BC)
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op(0x09, ADD_hl_rr, BC)
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op(0x0a, LD_a_irr, BC)
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op(0x0b, DEC_rr, BC)
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op(0x0c, INC_r, C)
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@ -48,7 +42,7 @@ auto Z80::instruction__(uint8 code) -> void {
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op(0x16, LD_r_n, D)
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op(0x17, RLA)
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op(0x18, JR_c_e, 1)
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op(0x19, ADD_rr_rr, HL, DE)
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op(0x19, ADD_hl_rr, DE)
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op(0x1a, LD_a_irr, DE)
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op(0x1b, DEC_rr, DE)
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op(0x1c, INC_r, E)
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@ -64,7 +58,7 @@ auto Z80::instruction__(uint8 code) -> void {
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op(0x26, LD_r_n, H)
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op(0x27, DAA)
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op(0x28, JR_c_e, ZF == 1)
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op(0x29, ADD_rr_rr, HL, HL)
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op(0x29, ADD_hl_rr, HL)
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op(0x2a, LD_rr_inn, HL)
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op(0x2b, DEC_rr, HL)
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op(0x2c, INC_r, L)
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@ -80,7 +74,7 @@ auto Z80::instruction__(uint8 code) -> void {
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op(0x36, LD_irr_n, HL)
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op(0x37, SCF)
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op(0x38, JR_c_e, CF == 1)
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op(0x39, ADD_rr_rr, HL, SP)
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op(0x39, ADD_hl_rr, SP)
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op(0x3a, LD_a_inn)
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op(0x3b, DEC_rr, SP)
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op(0x3c, INC_r, A)
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@ -546,44 +540,68 @@ auto Z80::instructionED(uint8 code) -> void {
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switch(code) {
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op(0x40, IN_r_ic, B)
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op(0x41, OUT_ic_r, B)
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op(0x42, SBC_hl_rr, BC)
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op(0x43, LD_inn_rr, BC)
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op(0x44, NEG)
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op(0x45, RETN)
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op(0x46, IM_o, 0)
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op(0x47, LD_r_r1, I, A)
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op(0x48, IN_r_ic, C)
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op(0x49, OUT_ic_r, C)
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op(0x4a, ADC_hl_rr, BC)
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op(0x4b, LD_rr_inn, BC)
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op(0x4c, NEG)
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op(0x4d, RETI)
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op(0x4e, IM_o, 0)
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op(0x4f, LD_r_r1, R, A)
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op(0x50, IN_r_ic, D)
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op(0x51, OUT_ic_r, D)
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op(0x52, SBC_hl_rr, DE)
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op(0x53, LD_inn_rr, DE)
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op(0x54, NEG)
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op(0x55, RETN)
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op(0x56, IM_o, 1)
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op(0x57, LD_r_r1, A, I)
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op(0x58, IN_r_ic, E)
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op(0x59, OUT_ic_r, E)
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op(0x5a, ADC_hl_rr, DE)
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op(0x5b, LD_rr_inn, DE)
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op(0x5c, NEG)
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op(0x5d, RETI)
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op(0x5e, IM_o, 2)
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op(0x5f, LD_r_r1, A, R)
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op(0x60, IN_r_ic, H)
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op(0x61, OUT_ic_r, H)
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op(0x62, SBC_hl_rr, HL)
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op(0x63, LD_inn_rr, HL)
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op(0x64, NEG)
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op(0x65, RETN)
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op(0x66, IM_o, 0)
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op(0x67, RRD)
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op(0x68, IN_r_ic, L)
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op(0x69, OUT_ic_r, L)
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op(0x6a, ADC_hl_rr, HL)
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op(0x6b, LD_rr_inn, HL)
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op(0x6c, NEG)
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op(0x6d, RETI)
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op(0x6e, IM_o, 0)
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op(0x6f, RLD)
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op(0x70, IN_r_ic, F)
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op(0x71, OUT_ic_r, F)
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op(0x72, SBC_hl_rr, SP)
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op(0x73, LD_inn_rr, SP)
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op(0x74, NEG)
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op(0x75, RETN)
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op(0x76, IM_o, 1)
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op(0x77, NOP)
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op(0x78, IN_r_ic, A)
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op(0x79, OUT_ic_r, A)
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op(0x7a, ADC_hl_rr, SP)
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op(0x7b, LD_rr_inn, SP)
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op(0x7c, NEG)
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op(0x7d, RETI)
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op(0x7e, IM_o, 2)
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op(0x7f, NOP)
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op(0xa0, LDI)
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op(0xa1, CPI)
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op(0xa2, INI)
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@ -602,7 +620,7 @@ auto Z80::instructionED(uint8 code) -> void {
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op(0xbb, OTDR)
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}
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trap(0xed, code);
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//undefined instructions are NOP
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}
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#undef op
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@ -269,6 +269,15 @@ auto Z80::instructionADC_a_r(uint8& x) -> void {
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A = ADD(A, x, CF);
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}
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auto Z80::instructionADC_hl_rr(uint16& x) -> void {
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wait(4);
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auto lo = ADD(HL >> 0, x >> 0, CF);
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wait(3);
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auto hi = ADD(HL >> 8, x >> 8, CF);
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HL = hi << 8 | lo << 0;
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ZF = HL == 0;
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}
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auto Z80::instructionADD_a_irr(uint16& x) -> void {
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A = ADD(A, read(displace(x)));
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}
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@ -281,11 +290,13 @@ auto Z80::instructionADD_a_r(uint8& x) -> void {
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A = ADD(A, x);
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}
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auto Z80::instructionADD_rr_rr(uint16& x, uint16& y) -> void {
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auto Z80::instructionADD_hl_rr(uint16& x) -> void {
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wait(4);
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x.byte(0) = ADD(x.byte(0), y.byte(0));
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auto lo = ADD(HL >> 0, x >> 0);
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wait(3);
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x.byte(1) = ADD(x.byte(1), y.byte(1), CF);
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auto hi = ADD(HL >> 8, x >> 8, CF);
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HL = hi << 8 | lo << 0;
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ZF = HL == 0;
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}
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auto Z80::instructionAND_a_irr(uint16& x) -> void {
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@ -379,7 +390,30 @@ auto Z80::instructionCPL() -> void {
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}
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auto Z80::instructionDAA() -> void {
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//todo: implement decimal adjust
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uint8 lo = A.bits(0,3);
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uint8 hi = A.bits(4,7);
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uint8 diff;
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if(CF) {
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diff = lo <= 9 && !HF ? 0x60 : 0x66;
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} else if(lo >= 10) {
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diff = hi <= 8 ? 0x06 : 0x66;
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} else if(hi >= 10) {
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diff = HF ? 0x66 : 0x60;
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} else {
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diff = HF ? 0x06 : 0x00;
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}
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if(NF == 0) A += diff;
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if(NF == 1) A -= diff;
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CF = CF || (lo <= 9 ? hi >= 10 : hi >= 9);
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PF = parity(A);
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XF = A.bit(3);
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HF = NF ? (HF && lo <= 5) : (lo >= 10);
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YF = A.bit(5);
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ZF = A == 0;
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SF = A.bit(7);
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}
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auto Z80::instructionDEC_irr(uint16& x) -> void {
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@ -548,6 +582,12 @@ auto Z80::instructionLD_r_r(uint8& x, uint8& y) -> void {
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x = y;
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}
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//LD to/from I/R requires an extra T-cycle
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auto Z80::instructionLD_r_r1(uint8& x, uint8& y) -> void {
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wait(1);
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x = y;
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}
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auto Z80::instructionLD_rr_inn(uint16& x) -> void {
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auto addr = operands();
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x.byte(0) = read(addr + 0);
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@ -732,6 +772,22 @@ auto Z80::instructionRLCA() -> void {
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YF = A.bit(5);
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}
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auto Z80::instructionRLD() -> void {
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auto data = read(HL);
|
||||
wait(1);
|
||||
write(HL, (data << 4) | (A & 0x0f));
|
||||
wait(3);
|
||||
A = (A & 0xf0) | (data >> 4);
|
||||
|
||||
NF = 0;
|
||||
PF = parity(A);
|
||||
XF = A.bit(3);
|
||||
HF = 0;
|
||||
YF = A.bit(5);
|
||||
ZF = A == 0;
|
||||
SF = A.bit(7);
|
||||
}
|
||||
|
||||
auto Z80::instructionRR_irr(uint16& x) -> void {
|
||||
auto addr = displace(x);
|
||||
write(addr, RR(read(addr)));
|
||||
|
|
@ -772,6 +828,22 @@ auto Z80::instructionRRCA() -> void {
|
|||
YF = A.bit(5);
|
||||
}
|
||||
|
||||
auto Z80::instructionRRD() -> void {
|
||||
auto data = read(HL);
|
||||
wait(1);
|
||||
write(HL, (data >> 4) | (A << 4));
|
||||
wait(3);
|
||||
A = (A & 0xf0) | (data & 0x0f);
|
||||
|
||||
NF = 0;
|
||||
PF = parity(A);
|
||||
XF = A.bit(3);
|
||||
HF = 0;
|
||||
YF = A.bit(5);
|
||||
ZF = A == 0;
|
||||
SF = A.bit(7);
|
||||
}
|
||||
|
||||
auto Z80::instructionRST_o(uint3 vector) -> void {
|
||||
wait(1);
|
||||
push(PC);
|
||||
|
|
@ -790,6 +862,15 @@ auto Z80::instructionSBC_a_r(uint8& x) -> void {
|
|||
A = SUB(A, x, CF);
|
||||
}
|
||||
|
||||
auto Z80::instructionSBC_hl_rr(uint16& x) -> void {
|
||||
wait(4);
|
||||
auto lo = SUB(HL >> 0, x >> 0, CF);
|
||||
wait(3);
|
||||
auto hi = SUB(HL >> 8, x >> 8, CF);
|
||||
HL = hi << 8 | lo << 0;
|
||||
ZF = HL == 0;
|
||||
}
|
||||
|
||||
auto Z80::instructionSCF() -> void {
|
||||
CF = 1;
|
||||
NF = 0;
|
||||
|
|
|
|||
|
|
@ -34,7 +34,6 @@ struct Z80 {
|
|||
auto out(uint8 addr, uint8 data) -> void;
|
||||
|
||||
//instruction.cpp
|
||||
auto trap(uint8 prefix, uint8 code) -> void;
|
||||
auto instruction() -> void;
|
||||
auto instruction__(uint8 code) -> void;
|
||||
auto instructionCB(uint8 code) -> void;
|
||||
|
|
@ -63,10 +62,11 @@ struct Z80 {
|
|||
auto instructionADC_a_irr(uint16&) -> void;
|
||||
auto instructionADC_a_n() -> void;
|
||||
auto instructionADC_a_r(uint8&) -> void;
|
||||
auto instructionADC_hl_rr(uint16&) -> void;
|
||||
auto instructionADD_a_irr(uint16&) -> void;
|
||||
auto instructionADD_a_n() -> void;
|
||||
auto instructionADD_a_r(uint8&) -> void;
|
||||
auto instructionADD_rr_rr(uint16&, uint16&) -> void;
|
||||
auto instructionADD_hl_rr(uint16&) -> void;
|
||||
auto instructionAND_a_irr(uint16&) -> void;
|
||||
auto instructionAND_a_n() -> void;
|
||||
auto instructionAND_a_r(uint8&) -> void;
|
||||
|
|
@ -116,6 +116,7 @@ struct Z80 {
|
|||
auto instructionLD_r_n(uint8&) -> void;
|
||||
auto instructionLD_r_irr(uint8&, uint16&) -> void;
|
||||
auto instructionLD_r_r(uint8&, uint8&) -> void;
|
||||
auto instructionLD_r_r1(uint8&, uint8&) -> void;
|
||||
auto instructionLD_rr_inn(uint16&) -> void;
|
||||
auto instructionLD_rr_nn(uint16&) -> void;
|
||||
auto instructionLD_sp_rr(uint16&) -> void;
|
||||
|
|
@ -148,16 +149,19 @@ struct Z80 {
|
|||
auto instructionRLC_irr(uint16&) -> void;
|
||||
auto instructionRLC_r(uint8&) -> void;
|
||||
auto instructionRLCA() -> void;
|
||||
auto instructionRLD() -> void;
|
||||
auto instructionRR_irr(uint16&) -> void;
|
||||
auto instructionRR_r(uint8&) -> void;
|
||||
auto instructionRRA() -> void;
|
||||
auto instructionRRC_irr(uint16&) -> void;
|
||||
auto instructionRRC_r(uint8&) -> void;
|
||||
auto instructionRRCA() -> void;
|
||||
auto instructionRRD() -> void;
|
||||
auto instructionRST_o(uint3) -> void;
|
||||
auto instructionSBC_a_irr(uint16&) -> void;
|
||||
auto instructionSBC_a_n() -> void;
|
||||
auto instructionSBC_a_r(uint8&) -> void;
|
||||
auto instructionSBC_hl_rr(uint16&) -> void;
|
||||
auto instructionSCF() -> void;
|
||||
auto instructionSET_o_irr(uint3, uint16&) -> void;
|
||||
auto instructionSET_o_r(uint3, uint8&) -> void;
|
||||
|
|
|
|||
Loading…
Reference in New Issue