2015-06-28 08:44:56 +00:00
|
|
|
//note: timings are completely unverified
|
|
|
|
|
//due to the ST018 chip design (on-die ROM), testing is nearly impossible
|
|
|
|
|
|
2015-11-14 00:52:51 +00:00
|
|
|
auto ArmDSP::bus_idle() -> void {
|
2012-04-15 06:49:56 +00:00
|
|
|
step(1);
|
|
|
|
|
}
|
|
|
|
|
|
2015-11-14 00:52:51 +00:00
|
|
|
auto ArmDSP::bus_read(unsigned mode, uint32 addr) -> uint32 {
|
2012-04-15 06:49:56 +00:00
|
|
|
step(1);
|
|
|
|
|
|
2015-11-14 00:52:51 +00:00
|
|
|
static auto memory = [&](const uint8* memory, uint mode, uint32 addr) -> uint32 {
|
2015-07-01 10:58:42 +00:00
|
|
|
if(mode & Word) {
|
2012-04-17 12:16:54 +00:00
|
|
|
memory += addr & ~3;
|
|
|
|
|
return memory[0] << 0 | memory[1] << 8 | memory[2] << 16 | memory[3] << 24;
|
2015-07-01 10:58:42 +00:00
|
|
|
} else if(mode & Byte) {
|
2012-04-17 12:16:54 +00:00
|
|
|
return memory[addr];
|
2015-07-01 10:58:42 +00:00
|
|
|
} else {
|
|
|
|
|
return 0; //should never occur
|
2012-04-17 12:16:54 +00:00
|
|
|
}
|
2012-03-23 10:43:39 +00:00
|
|
|
};
|
|
|
|
|
|
Update to v086r15 release.
byuu says:
Most importantly ... I'm now using "st018.rom" which is the program ROM
+ data ROM in one "firmware" file. Since all three Seta DSPs have the
ST01N stamp, unlike some of the arcade variants, I'm just going to go
with ST01N from now on instead of ST-001N. I was using the latter as
that's what Overload called them.
Moving on ...
The memory map should match real hardware now, and I even match the open
bus read results.
I also return the funky 0x40404001 for 60000000-7fffffff, for whatever
that's worth.
The CPU-side registers are also mirrored correctly, as they were in the
last WIP, so we should be good there.
I also simulate the reset pulse now, and a 0->!0 transition of $3804
will destroy the ARM CPU thread.
It will wait until the value is set back to zero to resume execution.
At startup, the ARM CPU will sleep for a while, thus simulating the
reset delay behavior.
Still need to figure out the exact cycle length, but that's really not
important for emulation.
Note in registers.hpp, the |4 in status() is basically what allows the
CPU program to keep going, and hit the checkmate condition.
If we remove that, the CPU deadlocks. Still need to figure out how and
when d4 is set on $3804 reads.
I can run any test program on both real hardware and in my emulator and
compare results, so by all means ... if you can come up with a test,
I'll run it.
2012-03-02 11:07:17 +00:00
|
|
|
switch(addr & 0xe0000000) {
|
2015-07-01 10:58:42 +00:00
|
|
|
case 0x00000000: return memory(programROM, mode, addr & 0x1ffff);
|
2012-03-31 08:14:31 +00:00
|
|
|
case 0x20000000: return pipeline.fetch.instruction;
|
2012-03-23 10:43:39 +00:00
|
|
|
case 0x40000000: break;
|
2012-03-31 08:14:31 +00:00
|
|
|
case 0x60000000: return 0x40404001;
|
|
|
|
|
case 0x80000000: return pipeline.fetch.instruction;
|
2015-07-01 10:58:42 +00:00
|
|
|
case 0xa0000000: return memory(dataROM, mode, addr & 0x7fff);
|
2012-03-31 08:14:31 +00:00
|
|
|
case 0xc0000000: return pipeline.fetch.instruction;
|
2015-07-01 10:58:42 +00:00
|
|
|
case 0xe0000000: return memory(programRAM, mode, addr & 0x3fff);
|
2012-02-27 00:18:50 +00:00
|
|
|
}
|
|
|
|
|
|
Update to v086r15 release.
byuu says:
Most importantly ... I'm now using "st018.rom" which is the program ROM
+ data ROM in one "firmware" file. Since all three Seta DSPs have the
ST01N stamp, unlike some of the arcade variants, I'm just going to go
with ST01N from now on instead of ST-001N. I was using the latter as
that's what Overload called them.
Moving on ...
The memory map should match real hardware now, and I even match the open
bus read results.
I also return the funky 0x40404001 for 60000000-7fffffff, for whatever
that's worth.
The CPU-side registers are also mirrored correctly, as they were in the
last WIP, so we should be good there.
I also simulate the reset pulse now, and a 0->!0 transition of $3804
will destroy the ARM CPU thread.
It will wait until the value is set back to zero to resume execution.
At startup, the ARM CPU will sleep for a while, thus simulating the
reset delay behavior.
Still need to figure out the exact cycle length, but that's really not
important for emulation.
Note in registers.hpp, the |4 in status() is basically what allows the
CPU program to keep going, and hit the checkmate condition.
If we remove that, the CPU deadlocks. Still need to figure out how and
when d4 is set on $3804 reads.
I can run any test program on both real hardware and in my emulator and
compare results, so by all means ... if you can come up with a test,
I'll run it.
2012-03-02 11:07:17 +00:00
|
|
|
addr &= 0xe000003f;
|
2012-02-28 11:21:18 +00:00
|
|
|
|
Update to v086r15 release.
byuu says:
Most importantly ... I'm now using "st018.rom" which is the program ROM
+ data ROM in one "firmware" file. Since all three Seta DSPs have the
ST01N stamp, unlike some of the arcade variants, I'm just going to go
with ST01N from now on instead of ST-001N. I was using the latter as
that's what Overload called them.
Moving on ...
The memory map should match real hardware now, and I even match the open
bus read results.
I also return the funky 0x40404001 for 60000000-7fffffff, for whatever
that's worth.
The CPU-side registers are also mirrored correctly, as they were in the
last WIP, so we should be good there.
I also simulate the reset pulse now, and a 0->!0 transition of $3804
will destroy the ARM CPU thread.
It will wait until the value is set back to zero to resume execution.
At startup, the ARM CPU will sleep for a while, thus simulating the
reset delay behavior.
Still need to figure out the exact cycle length, but that's really not
important for emulation.
Note in registers.hpp, the |4 in status() is basically what allows the
CPU program to keep going, and hit the checkmate condition.
If we remove that, the CPU deadlocks. Still need to figure out how and
when d4 is set on $3804 reads.
I can run any test program on both real hardware and in my emulator and
compare results, so by all means ... if you can come up with a test,
I'll run it.
2012-03-02 11:07:17 +00:00
|
|
|
if(addr == 0x40000010) {
|
|
|
|
|
if(bridge.cputoarm.ready) {
|
|
|
|
|
bridge.cputoarm.ready = false;
|
2012-03-31 08:14:31 +00:00
|
|
|
return bridge.cputoarm.data;
|
2012-02-28 11:21:18 +00:00
|
|
|
}
|
2012-02-27 00:18:50 +00:00
|
|
|
}
|
|
|
|
|
|
Update to v086r15 release.
byuu says:
Most importantly ... I'm now using "st018.rom" which is the program ROM
+ data ROM in one "firmware" file. Since all three Seta DSPs have the
ST01N stamp, unlike some of the arcade variants, I'm just going to go
with ST01N from now on instead of ST-001N. I was using the latter as
that's what Overload called them.
Moving on ...
The memory map should match real hardware now, and I even match the open
bus read results.
I also return the funky 0x40404001 for 60000000-7fffffff, for whatever
that's worth.
The CPU-side registers are also mirrored correctly, as they were in the
last WIP, so we should be good there.
I also simulate the reset pulse now, and a 0->!0 transition of $3804
will destroy the ARM CPU thread.
It will wait until the value is set back to zero to resume execution.
At startup, the ARM CPU will sleep for a while, thus simulating the
reset delay behavior.
Still need to figure out the exact cycle length, but that's really not
important for emulation.
Note in registers.hpp, the |4 in status() is basically what allows the
CPU program to keep going, and hit the checkmate condition.
If we remove that, the CPU deadlocks. Still need to figure out how and
when d4 is set on $3804 reads.
I can run any test program on both real hardware and in my emulator and
compare results, so by all means ... if you can come up with a test,
I'll run it.
2012-03-02 11:07:17 +00:00
|
|
|
if(addr == 0x40000020) {
|
2012-03-31 08:14:31 +00:00
|
|
|
return bridge.status();
|
2012-02-27 00:18:50 +00:00
|
|
|
}
|
|
|
|
|
|
2015-07-01 10:58:42 +00:00
|
|
|
return 0;
|
2012-02-27 00:18:50 +00:00
|
|
|
}
|
|
|
|
|
|
2015-11-14 00:52:51 +00:00
|
|
|
auto ArmDSP::bus_write(uint mode, uint32 addr, uint32 word) -> void {
|
2012-04-15 06:49:56 +00:00
|
|
|
step(1);
|
|
|
|
|
|
2015-11-14 00:52:51 +00:00
|
|
|
static auto memory = [](uint8* memory, uint mode, uint32 addr, uint32 word) {
|
2015-07-01 10:58:42 +00:00
|
|
|
if(mode & Word) {
|
2012-03-23 10:43:39 +00:00
|
|
|
memory += addr & ~3;
|
|
|
|
|
*memory++ = word >> 0;
|
|
|
|
|
*memory++ = word >> 8;
|
|
|
|
|
*memory++ = word >> 16;
|
|
|
|
|
*memory++ = word >> 24;
|
2015-07-01 10:58:42 +00:00
|
|
|
} else if(mode & Byte) {
|
2012-03-23 10:43:39 +00:00
|
|
|
memory += addr;
|
|
|
|
|
*memory++ = word >> 0;
|
|
|
|
|
}
|
|
|
|
|
};
|
|
|
|
|
|
Update to v086r15 release.
byuu says:
Most importantly ... I'm now using "st018.rom" which is the program ROM
+ data ROM in one "firmware" file. Since all three Seta DSPs have the
ST01N stamp, unlike some of the arcade variants, I'm just going to go
with ST01N from now on instead of ST-001N. I was using the latter as
that's what Overload called them.
Moving on ...
The memory map should match real hardware now, and I even match the open
bus read results.
I also return the funky 0x40404001 for 60000000-7fffffff, for whatever
that's worth.
The CPU-side registers are also mirrored correctly, as they were in the
last WIP, so we should be good there.
I also simulate the reset pulse now, and a 0->!0 transition of $3804
will destroy the ARM CPU thread.
It will wait until the value is set back to zero to resume execution.
At startup, the ARM CPU will sleep for a while, thus simulating the
reset delay behavior.
Still need to figure out the exact cycle length, but that's really not
important for emulation.
Note in registers.hpp, the |4 in status() is basically what allows the
CPU program to keep going, and hit the checkmate condition.
If we remove that, the CPU deadlocks. Still need to figure out how and
when d4 is set on $3804 reads.
I can run any test program on both real hardware and in my emulator and
compare results, so by all means ... if you can come up with a test,
I'll run it.
2012-03-02 11:07:17 +00:00
|
|
|
switch(addr & 0xe0000000) {
|
2012-03-23 10:43:39 +00:00
|
|
|
case 0x00000000: return;
|
|
|
|
|
case 0x20000000: return;
|
|
|
|
|
case 0x40000000: break;
|
|
|
|
|
case 0x60000000: return;
|
|
|
|
|
case 0x80000000: return;
|
|
|
|
|
case 0xa0000000: return;
|
|
|
|
|
case 0xc0000000: return;
|
2015-07-01 10:58:42 +00:00
|
|
|
case 0xe0000000: return memory(programRAM, mode, addr & 0x3fff, word);
|
2012-02-28 11:21:18 +00:00
|
|
|
}
|
|
|
|
|
|
Update to v086r15 release.
byuu says:
Most importantly ... I'm now using "st018.rom" which is the program ROM
+ data ROM in one "firmware" file. Since all three Seta DSPs have the
ST01N stamp, unlike some of the arcade variants, I'm just going to go
with ST01N from now on instead of ST-001N. I was using the latter as
that's what Overload called them.
Moving on ...
The memory map should match real hardware now, and I even match the open
bus read results.
I also return the funky 0x40404001 for 60000000-7fffffff, for whatever
that's worth.
The CPU-side registers are also mirrored correctly, as they were in the
last WIP, so we should be good there.
I also simulate the reset pulse now, and a 0->!0 transition of $3804
will destroy the ARM CPU thread.
It will wait until the value is set back to zero to resume execution.
At startup, the ARM CPU will sleep for a while, thus simulating the
reset delay behavior.
Still need to figure out the exact cycle length, but that's really not
important for emulation.
Note in registers.hpp, the |4 in status() is basically what allows the
CPU program to keep going, and hit the checkmate condition.
If we remove that, the CPU deadlocks. Still need to figure out how and
when d4 is set on $3804 reads.
I can run any test program on both real hardware and in my emulator and
compare results, so by all means ... if you can come up with a test,
I'll run it.
2012-03-02 11:07:17 +00:00
|
|
|
addr &= 0xe000003f;
|
2012-03-23 10:43:39 +00:00
|
|
|
word &= 0x000000ff;
|
Update to v086r15 release.
byuu says:
Most importantly ... I'm now using "st018.rom" which is the program ROM
+ data ROM in one "firmware" file. Since all three Seta DSPs have the
ST01N stamp, unlike some of the arcade variants, I'm just going to go
with ST01N from now on instead of ST-001N. I was using the latter as
that's what Overload called them.
Moving on ...
The memory map should match real hardware now, and I even match the open
bus read results.
I also return the funky 0x40404001 for 60000000-7fffffff, for whatever
that's worth.
The CPU-side registers are also mirrored correctly, as they were in the
last WIP, so we should be good there.
I also simulate the reset pulse now, and a 0->!0 transition of $3804
will destroy the ARM CPU thread.
It will wait until the value is set back to zero to resume execution.
At startup, the ARM CPU will sleep for a while, thus simulating the
reset delay behavior.
Still need to figure out the exact cycle length, but that's really not
important for emulation.
Note in registers.hpp, the |4 in status() is basically what allows the
CPU program to keep going, and hit the checkmate condition.
If we remove that, the CPU deadlocks. Still need to figure out how and
when d4 is set on $3804 reads.
I can run any test program on both real hardware and in my emulator and
compare results, so by all means ... if you can come up with a test,
I'll run it.
2012-03-02 11:07:17 +00:00
|
|
|
|
|
|
|
|
if(addr == 0x40000000) {
|
|
|
|
|
bridge.armtocpu.ready = true;
|
2012-03-23 10:43:39 +00:00
|
|
|
bridge.armtocpu.data = word;
|
2012-02-27 00:18:50 +00:00
|
|
|
return;
|
2012-02-26 07:59:44 +00:00
|
|
|
}
|
Update to v086r16 release.
byuu says:
Cydrak, I moved the step from the opcode decoder and opcodes themselves
into bus_(read,write)(byte,word), to minimize code.
If that's not feasible for some reason, please let me know and I'll
change it back to your latest WIP.
This has your carry flag fix, the timer skeleton (doesn't really work
yet), the Booth two-bit steps, and the carry flag clear thing inside
multiply ops.
Also added the aforementioned reset delay and reset bit stuff, and fixed
the steps to 21MHz for instructions and 64KHz for reset pulse.
I wasn't sure about the shifter extra cycles. I only saw it inside one
of the four (or was it three?) opcodes that have shifter functions.
Shouldn't it be in all of them?
The game does indeed appear to be fully playable now, but the AI doesn't
exactly match my real cartridge.
This could be for any number of reasons: ARM CPU bug, timer behavior
bug, oscillator differences between my real hardware and the emulator,
etc.
However ... the AI is 100% predictable every time, both under emulation
and on real hardware.
- For the first step, move 九-1 to 八-1.
- The opponent moves 三-3 to 四-3.
- Now move 七-1 to 六-1.
- The opponent moves 二-2 to 八-8.
However, on my real SNES, the opponent moves 一-3 to 二-4.
2012-03-07 13:03:15 +00:00
|
|
|
|
2012-03-10 12:37:36 +00:00
|
|
|
if(addr == 0x40000010) {
|
|
|
|
|
bridge.signal = true;
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
2012-03-23 10:43:39 +00:00
|
|
|
if(addr == 0x40000020) { bridge.timerlatch = (bridge.timerlatch & 0xffff00) | (word << 0); return; }
|
|
|
|
|
if(addr == 0x40000024) { bridge.timerlatch = (bridge.timerlatch & 0xff00ff) | (word << 8); return; }
|
|
|
|
|
if(addr == 0x40000028) { bridge.timerlatch = (bridge.timerlatch & 0x00ffff) | (word << 16); return; }
|
Update to v086r16 release.
byuu says:
Cydrak, I moved the step from the opcode decoder and opcodes themselves
into bus_(read,write)(byte,word), to minimize code.
If that's not feasible for some reason, please let me know and I'll
change it back to your latest WIP.
This has your carry flag fix, the timer skeleton (doesn't really work
yet), the Booth two-bit steps, and the carry flag clear thing inside
multiply ops.
Also added the aforementioned reset delay and reset bit stuff, and fixed
the steps to 21MHz for instructions and 64KHz for reset pulse.
I wasn't sure about the shifter extra cycles. I only saw it inside one
of the four (or was it three?) opcodes that have shifter functions.
Shouldn't it be in all of them?
The game does indeed appear to be fully playable now, but the AI doesn't
exactly match my real cartridge.
This could be for any number of reasons: ARM CPU bug, timer behavior
bug, oscillator differences between my real hardware and the emulator,
etc.
However ... the AI is 100% predictable every time, both under emulation
and on real hardware.
- For the first step, move 九-1 to 八-1.
- The opponent moves 三-3 to 四-3.
- Now move 七-1 to 六-1.
- The opponent moves 二-2 to 八-8.
However, on my real SNES, the opponent moves 一-3 to 二-4.
2012-03-07 13:03:15 +00:00
|
|
|
|
2012-03-23 10:43:39 +00:00
|
|
|
if(addr == 0x4000002c) {
|
Update to v086r16 release.
byuu says:
Cydrak, I moved the step from the opcode decoder and opcodes themselves
into bus_(read,write)(byte,word), to minimize code.
If that's not feasible for some reason, please let me know and I'll
change it back to your latest WIP.
This has your carry flag fix, the timer skeleton (doesn't really work
yet), the Booth two-bit steps, and the carry flag clear thing inside
multiply ops.
Also added the aforementioned reset delay and reset bit stuff, and fixed
the steps to 21MHz for instructions and 64KHz for reset pulse.
I wasn't sure about the shifter extra cycles. I only saw it inside one
of the four (or was it three?) opcodes that have shifter functions.
Shouldn't it be in all of them?
The game does indeed appear to be fully playable now, but the AI doesn't
exactly match my real cartridge.
This could be for any number of reasons: ARM CPU bug, timer behavior
bug, oscillator differences between my real hardware and the emulator,
etc.
However ... the AI is 100% predictable every time, both under emulation
and on real hardware.
- For the first step, move 九-1 to 八-1.
- The opponent moves 三-3 to 四-3.
- Now move 七-1 to 六-1.
- The opponent moves 二-2 to 八-8.
However, on my real SNES, the opponent moves 一-3 to 二-4.
2012-03-07 13:03:15 +00:00
|
|
|
bridge.timer = bridge.timerlatch;
|
2012-03-23 10:43:39 +00:00
|
|
|
return;
|
Update to v086r16 release.
byuu says:
Cydrak, I moved the step from the opcode decoder and opcodes themselves
into bus_(read,write)(byte,word), to minimize code.
If that's not feasible for some reason, please let me know and I'll
change it back to your latest WIP.
This has your carry flag fix, the timer skeleton (doesn't really work
yet), the Booth two-bit steps, and the carry flag clear thing inside
multiply ops.
Also added the aforementioned reset delay and reset bit stuff, and fixed
the steps to 21MHz for instructions and 64KHz for reset pulse.
I wasn't sure about the shifter extra cycles. I only saw it inside one
of the four (or was it three?) opcodes that have shifter functions.
Shouldn't it be in all of them?
The game does indeed appear to be fully playable now, but the AI doesn't
exactly match my real cartridge.
This could be for any number of reasons: ARM CPU bug, timer behavior
bug, oscillator differences between my real hardware and the emulator,
etc.
However ... the AI is 100% predictable every time, both under emulation
and on real hardware.
- For the first step, move 九-1 to 八-1.
- The opponent moves 三-3 to 四-3.
- Now move 七-1 to 六-1.
- The opponent moves 二-2 to 八-8.
However, on my real SNES, the opponent moves 一-3 to 二-4.
2012-03-07 13:03:15 +00:00
|
|
|
}
|
2012-02-27 00:18:50 +00:00
|
|
|
}
|