mirror of https://github.com/bsnes-emu/bsnes.git
Update to v086r15 release.
byuu says: Most importantly ... I'm now using "st018.rom" which is the program ROM + data ROM in one "firmware" file. Since all three Seta DSPs have the ST01N stamp, unlike some of the arcade variants, I'm just going to go with ST01N from now on instead of ST-001N. I was using the latter as that's what Overload called them. Moving on ... The memory map should match real hardware now, and I even match the open bus read results. I also return the funky 0x40404001 for 60000000-7fffffff, for whatever that's worth. The CPU-side registers are also mirrored correctly, as they were in the last WIP, so we should be good there. I also simulate the reset pulse now, and a 0->!0 transition of $3804 will destroy the ARM CPU thread. It will wait until the value is set back to zero to resume execution. At startup, the ARM CPU will sleep for a while, thus simulating the reset delay behavior. Still need to figure out the exact cycle length, but that's really not important for emulation. Note in registers.hpp, the |4 in status() is basically what allows the CPU program to keep going, and hit the checkmate condition. If we remove that, the CPU deadlocks. Still need to figure out how and when d4 is set on $3804 reads. I can run any test program on both real hardware and in my emulator and compare results, so by all means ... if you can come up with a test, I'll run it.
This commit is contained in:
Tim Allen
parent
aa8ac7bbb8
commit
d118b70b30
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@ -1,7 +1,7 @@
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#ifndef BASE_HPP
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#define BASE_HPP
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const char Version[] = "086.14";
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const char Version[] = "086.15";
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#include <nall/platform.hpp>
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#include <nall/algorithm.hpp>
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@ -494,7 +494,7 @@ SnesCartridge::SnesCartridge(const uint8_t *data, unsigned size) {
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);
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if(has_st010) markup.append(
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" <necdsp model='uPD96050' frequency='10000000' firmware='st0010.rom' sha256='55c697e864562445621cdf8a7bf6e84ae91361e393d382a3704e9aa55559041e'>\n"
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" <necdsp model='uPD96050' frequency='10000000' firmware='st010.rom' sha256='55c697e864562445621cdf8a7bf6e84ae91361e393d382a3704e9aa55559041e'>\n"
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" <dr>\n"
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" <map address='60:0000'/>\n"
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" <map address='e0:0000'/>\n"
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@ -511,7 +511,7 @@ SnesCartridge::SnesCartridge(const uint8_t *data, unsigned size) {
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);
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if(has_st011) markup.append(
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" <necdsp model='uPD96050' frequency='15000000' firmware='st0011.rom' sha256='651b82a1e26c4fa8dd549e91e7f923012ed2ca54c1d9fd858655ab30679c2f0e'>\n"
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" <necdsp model='uPD96050' frequency='15000000' firmware='st011.rom' sha256='651b82a1e26c4fa8dd549e91e7f923012ed2ca54c1d9fd858655ab30679c2f0e'>\n"
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" <dr>\n"
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" <map address='60:0000'/>\n"
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" <map address='e0:0000'/>\n"
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@ -528,7 +528,7 @@ SnesCartridge::SnesCartridge(const uint8_t *data, unsigned size) {
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);
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if(has_st018) markup.append(
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" <armdsp firmware='st0018.rom' sha256='6cceff3c6945bb2672040066d218efcd2f31492f3f5c28916c8e53435c2c887e'>\n"
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" <armdsp firmware='st018.rom' sha256='6df209ab5d2524d1839c038be400ae5eb20dafc14a3771a3239cd9e8acd53806'>\n"
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" <map address='00-3f:3800-38ff'/>\n"
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" <map address='80-bf:3800-38ff'/>\n"
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" </armdsp>\n"
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@ -336,7 +336,6 @@ void Cartridge::parse_markup_armdsp(XML::Node &root) {
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if(root.exists() == false) return;
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has_armdsp = true;
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for(auto &byte : armdsp.programROM) byte = 0x00;
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string firmware = root["firmware"].data;
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string sha256 = root["sha256"].data;
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@ -344,14 +343,14 @@ void Cartridge::parse_markup_armdsp(XML::Node &root) {
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file fp;
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if(fp.open(path, file::mode::read) == false) {
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interface->message({ "Warning: ARM DSP firmware ", firmware, " is missing." });
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} else if(fp.size() != 128 * 1024) {
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} else if(fp.size() != 160 * 1024) {
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interface->message({ "Warning: ARM DSP firmware ", firmware, " is of the wrong file size." });
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fp.close();
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} else {
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for(auto &byte : armdsp.programROM) byte = fp.read();
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fp.read(armdsp.firmware, fp.size());
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if(!sha256.empty()) {
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if(sha256 != nall::sha256(armdsp.programROM, 128 * 1024)) {
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if(sha256 != nall::sha256(armdsp.firmware, fp.size())) {
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interface->message({ "Warning: ARM DSP firmware ", firmware, " SHA256 sum is incorrect." });
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}
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}
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@ -14,6 +14,20 @@ ArmDSP armdsp;
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void ArmDSP::Enter() { armdsp.enter(); }
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void ArmDSP::enter() {
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//reset hold delay
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while(bridge.reset) {
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step(4);
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synchronize_cpu();
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continue;
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}
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//reset sequence delay
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if(bridge.ready == false) {
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step(4096); //todo: verify cycle count
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synchronize_cpu();
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bridge.ready = true;
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}
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while(true) {
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if(scheduler.sync == Scheduler::SynchronizeMode::All) {
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scheduler.exit(Scheduler::ExitReason::SynchronizeEvent);
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@ -44,12 +58,16 @@ void ArmDSP::enter() {
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pipeline.prefetch.opcode = bus_readword(r[15]);
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r[15].step();
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//if(pipeline.instruction.address == 0x0000ef5c) trace = 1;
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pipeline.mdr.address = r[15];
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pipeline.mdr.opcode = bus_readword(r[15]);
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if(pipeline.instruction.address == 0x00000208) trace = 1;
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if(trace) {
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print("\n", disassemble_registers(), "\n");
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print(disassemble_opcode(pipeline.instruction.address), "\n");
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usleep(200000);
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}
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trace = 0;
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instruction = pipeline.instruction.opcode;
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if(!condition()) continue;
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@ -86,7 +104,8 @@ uint8 ArmDSP::mmio_read(unsigned addr) {
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}
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}
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if(addr == 0x3802);
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if(addr == 0x3802) {
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}
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if(addr == 0x3804) {
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data = bridge.status();
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@ -116,7 +135,10 @@ void ArmDSP::mmio_write(unsigned addr, uint8 data) {
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print("* w3802 = ", hex<2>(data), "\n");
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}
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if(addr == 0x3804);
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if(addr == 0x3804) {
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if(!bridge.reset && data) arm_reset();
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bridge.reset = data;
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}
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}
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void ArmDSP::init() {
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@ -129,32 +151,44 @@ void ArmDSP::unload() {
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}
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void ArmDSP::power() {
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string filename = interface->path(Cartridge::Slot::Base, "st0018d.rom");
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string filename = { dir(interface->path(Cartridge::Slot::Base, "st018.rom")), "disassembly.txt" };
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file fp;
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if(fp.open(filename, file::mode::read)) {
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fp.read(dataROM, 32 * 1024);
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fp.close();
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}
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filename = { dir(filename), "disassembly.txt" };
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fp.open(filename, file::mode::write);
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for(unsigned n = 0; n < 128 * 1024; n += 4) {
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fp.print(disassemble_opcode(n), "\n");
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}
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fp.close();
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for(unsigned n = 0; n < 16 * 1024; n++) programRAM[n] = random(0x00);
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}
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void ArmDSP::reset() {
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bridge.reset = false;
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arm_reset();
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}
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void ArmDSP::arm_reset() {
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bridge.ready = false;
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create(ArmDSP::Enter, 21477272);
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for(auto &rd : r) rd = 0;
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shiftercarry = 0;
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exception = false;
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exception = 0;
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pipeline.reload = true;
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r[15].write = [&] { pipeline.reload = true; };
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}
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ArmDSP::ArmDSP() {
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firmware = new uint8[160 * 1024];
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programRAM = new uint8[16 * 1024];
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programROM = &firmware[0];
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dataROM = &firmware[128 * 1024];
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}
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ArmDSP::~ArmDSP() {
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delete[] firmware;
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delete[] programRAM;
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}
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}
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//ARMv3 (ARM6)
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struct ArmDSP : public Coprocessor {
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uint8 programROM[128 * 1024];
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uint8 programRAM[16 * 1024];
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uint8 dataROM[32 * 1024];
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uint8 *firmware;
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uint8 *programROM;
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uint8 *dataROM;
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uint8 *programRAM;
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#include "registers.hpp"
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@ -15,6 +16,10 @@ struct ArmDSP : public Coprocessor {
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void unload();
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void power();
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void reset();
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void arm_reset();
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ArmDSP();
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~ArmDSP();
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uint8 mmio_read(unsigned addr);
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void mmio_write(unsigned addr, uint8 data);
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@ -40,13 +45,13 @@ struct ArmDSP : public Coprocessor {
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void op_branch();
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//memory.cpp
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uint8 bus_iread(uint32 addr);
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void bus_iwrite(uint32 addr, uint8 data);
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uint8 bus_read(uint32 addr);
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void bus_write(uint32 addr, uint8 data);
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uint32 bus_readbyte(uint32 addr);
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uint32 bus_readword(uint32 addr);
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void bus_writebyte(uint32 addr, uint32 data);
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uint32 bus_readword(uint32 addr);
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void bus_writeword(uint32 addr, uint32 data);
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//disassembler.cpp
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@ -164,7 +164,7 @@ string ArmDSP::disassemble_opcode(uint32 pc) {
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if(p == 1) output.append("]");
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if(p == 1 && w == 1) output.append("!");
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if(rn == 15) output.append(" (0x", hex<8>(pc + 8 + (u ? +immediate : -immediate)), ")");
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if(rn == 15) output.append(" =0x", hex<8>(bus_readword(pc + 8 + (u ? +immediate : -immediate))));
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return output;
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}
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@ -1,87 +1,73 @@
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#ifdef ARMDSP_CPP
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uint8 ArmDSP::bus_iread(uint32 addr) {
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if(addr >= 0x00000000 && addr <= 0x0001ffff) {
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return programROM[addr & 0x0001ffff];
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uint8 ArmDSP::bus_read(uint32 addr) {
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switch(addr & 0xe0000000) {
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case 0x00000000: return programROM[addr & 0x0001ffff];
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case 0x20000000: return pipeline.mdr.opcode >> ((addr & 3) << 3);
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case 0x40000000: break; //MMIO
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case 0x60000000: return 0x40404001 >> ((addr & 3) << 3);
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case 0x80000000: return pipeline.mdr.opcode >> ((addr & 3) << 3);
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case 0xa0000000: return dataROM[addr & 0x00007fff];
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case 0xc0000000: return pipeline.mdr.opcode >> ((addr & 3) << 3);
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case 0xe0000000: return programRAM[addr & 0x00003fff];
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}
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if(addr >= 0x40000000 && addr <= 0x400000ff) {
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if(addr == 0x40000000) return 0x00;
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addr &= 0xe000003f;
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if(addr == 0x40000010) {
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if(bridge.cputoarm.ready) {
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bridge.cputoarm.ready = false;
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return bridge.cputoarm.data;
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}
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if(addr == 0x40000010) {
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if(bridge.cputoarm.ready) {
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bridge.cputoarm.ready = false;
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return bridge.cputoarm.data;
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}
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if(addr == 0x40000020) {
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return bridge.status();
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}
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if(addr == 0x40000024) return 0x00;
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if(addr == 0x40000028) return 0x00;
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if(addr == 0x4000002c) return 0x00;
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}
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if(addr >= 0xa0000000 && addr <= 0xa0007fff) {
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return dataROM[addr & 0x00007fff];
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if(addr == 0x40000020) {
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return bridge.status();
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}
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if(addr >= 0xe0000000 && addr <= 0xe0003fff) {
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return programRAM[addr & 0x00003fff];
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}
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if((addr & 3) == 0) print("* ARM r", hex<8>(addr), "\n");
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return 0x00;
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}
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void ArmDSP::bus_iwrite(uint32 addr, uint8 data) {
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if(addr >= 0x40000000 && addr <= 0x400000ff) {
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if(addr == 0x40000000) {
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bridge.armtocpu.ready = true;
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bridge.armtocpu.data = data;
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return;
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}
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if(addr == 0x40000020) return;
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if(addr == 0x40000024) return;
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if(addr == 0x40000028) return;
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if(addr == 0x4000002c) return print("* w4000002c = ", hex<2>(data), "\n");
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void ArmDSP::bus_write(uint32 addr, uint8 data) {
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switch(addr & 0xe0000000) {
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case 0x40000000: break; //MMIO
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case 0xe0000000: programRAM[addr & 0x00003fff] = data; return;
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default: return;
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}
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if(addr >= 0xe0000000 && addr <= 0xe0003fff) {
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programRAM[addr & 0x00003fff] = data;
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addr &= 0xe000003f;
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if(addr == 0x40000000) {
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bridge.armtocpu.ready = true;
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bridge.armtocpu.data = data;
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return;
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}
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if((addr & 3) == 0) print("* ARM w", hex<8>(addr), " = ", hex<2>(data), "\n");
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}
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uint32 ArmDSP::bus_readbyte(uint32 addr) {
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return bus_iread(addr);
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return bus_read(addr);
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}
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void ArmDSP::bus_writebyte(uint32 addr, uint32 data) {
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return bus_write(addr, data);
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}
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uint32 ArmDSP::bus_readword(uint32 addr) {
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addr &= ~3;
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return (
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(bus_iread(addr + 0) << 0)
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| (bus_iread(addr + 1) << 8)
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| (bus_iread(addr + 2) << 16)
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| (bus_iread(addr + 3) << 24)
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(bus_read(addr + 0) << 0)
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| (bus_read(addr + 1) << 8)
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| (bus_read(addr + 2) << 16)
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| (bus_read(addr + 3) << 24)
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);
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}
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void ArmDSP::bus_writebyte(uint32 addr, uint32 data) {
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return bus_iwrite(addr, data);
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}
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void ArmDSP::bus_writeword(uint32 addr, uint32 data) {
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addr &= ~3;
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bus_iwrite(addr + 0, data >> 0);
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bus_iwrite(addr + 1, data >> 8);
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bus_iwrite(addr + 2, data >> 16);
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bus_iwrite(addr + 3, data >> 24);
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bus_write(addr + 0, data >> 0);
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bus_write(addr + 1, data >> 8);
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bus_write(addr + 2, data >> 16);
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bus_write(addr + 3, data >> 24);
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}
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#endif
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@ -14,9 +14,11 @@ struct Bridge {
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};
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Buffer cputoarm;
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Buffer armtocpu;
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bool reset;
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bool ready;
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uint8 status() const {
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return 0x84 | (cputoarm.ready << 3) | (armtocpu.ready << 0);
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return (ready << 7) | (cputoarm.ready << 3) | (armtocpu.ready << 0) | 4;
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}
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} bridge;
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@ -111,6 +113,7 @@ struct Pipeline {
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};
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Instruction instruction;
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Instruction prefetch;
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Instruction mdr;
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} pipeline;
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uint32 instruction;
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