Commit Graph

253 Commits

Author SHA1 Message Date
zeromus 10bceeb0dc Nope, I think it's a good idea now.
Revert "This reverts commit c878c85daeaaf0cae3e28f24bc1a8b511293d7b6."
This reverts commit 1d1f2a18c6.
2020-04-23 21:20:59 -04:00
zeromus 1d1f2a18c6 This reverts commit c878c85dae. 2020-04-23 21:06:12 -04:00
zeromus c878c85dae for your consideration: sync settings return flags instead of a bool, so we can have more granularity in what needs resetting than just "reboot core". for instance, we would like to minimize the number of times the window layout is redone by not doing it when the screen settings havent changed. HOWEVER, while I was writing this commit message, I realized, I should probably do it just by being more cautious in kicking off the layout (unless the data coming from the core has changed, a layout shouldnt happen). So I am going to make this commit, in case it inspires anyone, and then revert it. 2020-04-23 21:05:56 -04:00
adelikat ca90b90698 MOS/Via.cs - comment out unused variable 2020-03-19 10:33:08 -05:00
adelikat 9fa59bad42 refactor CoreComm usages in Computer cores 2020-03-15 09:10:13 -05:00
adelikat da95c1f56f remove RomAnnotation fields on CoreComm and use the service instead 2020-03-14 22:10:57 -05:00
adelikat cdcc1eabde use inline out variables in Emulation.Cores 2020-02-18 15:10:29 -06:00
adelikat 2ccf03fd44 use property initializers in some cores and some constructor cleanups 2020-02-18 10:54:39 -06:00
adelikat 606c3bf1c2
use more advanced language features in Emulation.Cores (#1852)
* Use expression bodies in Emulation.Cores, and a few other misc cleanups

* remove unused usings in Emulation.Common

* cleanups in Tables_Direct.cs

* some cleanups in nes boards - redundant code

* remove some redundant array initializers in Emulation.Cores

* cleanup AmstradCPC.Controllers

* use object initializers in a lot of places

* nes mappers - remove disch's notes comments in favor of the nesdev wiki link

* cleanup CdtConverter.cs, mostly use of object initializers

* remove redundant .ToString() calls in Emulation.Cores

* using var in Emulation.Cores

* AmstradCPC/ZXSpectrum - simplify some linq, tabs instead of spaces, a few other misc cleanups

* Use null-propagation in Emulation.Cores
2020-02-17 16:54:51 -06:00
adelikat 969642b6c7 add Get/SetCpuFlagsAndRegisters to MOS6502X, and have cores point to that, instead of the same boilerplate in each core 2020-02-16 17:44:52 -06:00
adelikat 027dc01c8b
create StateSerializer as a base implementation of IStatable (#1850)
* create StateSerializer, an ITextStatable implementation using the Serializer class, and wire it up to the TI83 core

* wire StateSerializer to A2600 core

* wire up StateSerializer to AmstradCPC, C64, and ZXS

* wire up StateSerializer to MSX, A27800, and Coleco

* wire up state serializer to ChannelF, Vectrex, Intellivision

* fix GambatteLink to implement ITextStatable, implement TextSerializer in O2

* StateSerializer - wire up a loadstate callback and implement StateSerializer for NesHawk, a bit of rework to subNesHawk as a result

* fix subneshawk text savestates

* StateSerializer - implement byte[] buffer storing (optionally), wire up to PCE

* implement StateSerializer to SMS, tweak GGLink accordingly

* implement StateSerializer in GBHawk, fix link cores accordingly

* StateSerializer - use Serializer static methods to create serializers
2020-02-16 12:05:57 -06:00
adelikat 4b7a7dd293
Make Binary states default and Textstates opt-in for cores (#1848)
* Rewind & State config - remove the default option

* remove the savestate type of default, not that this is a breaking config change for anyone that had specifically set savestates to text

* remove BinaryStatesPreferred from IStatable and use config setting when starting movies from "Now" in record movie dialog

* remove BinaryStatesPreferred from cores

* make text savestates an extension method off of IStatable and an inteface ITextStatable it uses if the core implements it. This will allow cores to opt in to text states if desired

* make cores with actual text savestate impleemntations get ITextStatable, remove text state logic from cores that just have a binary as as text implementation
2020-02-15 10:22:26 -06:00
YoshiRulz b2a3477f52
Enable SA1123 and fix noncompliance
"Do not place regions within elements"
2020-01-25 18:06:56 +10:00
YoshiRulz 6f3f01125c
Enable SA1504 and fix noncompliance
"All accessors should be single-line or multi-line"
i.e. no block form on one line
2020-01-25 14:56:56 +10:00
adelikat f83261c116 misc cleanups in emulator core service logic 2020-01-11 13:19:51 -06:00
adelikat fef746dffa properly dispose of IDisposables in core savestate code, and a few other places 2019-12-06 17:33:17 -06:00
J.D. Purcell fec63fb66a Spaces -> tabs, fix mixed newlines. 2019-11-03 20:58:36 -05:00
J.D. Purcell c956b5993b Small FFT change I had stashed. 2019-10-21 00:10:28 -04:00
SaxxonPike 1e5fe55f30 C64: Don't reallocate the SID filter buffer every time (purely perf) 2019-07-19 19:09:08 -05:00
SaxxonPike a119420c79 C64: VC count enable seems to need to be delayed by 1 cycle after badline
- which doesn't affect normal operation
- which DOES affect VSP
2019-07-14 20:22:07 -05:00
SaxxonPike 4d6ed8d6c8 C64: Savestate should include the new variables 2019-07-14 16:32:53 -05:00
SaxxonPike 8e8d3a6a1b C64: Writes to some registers on the VIC in phase 2 by the CPU should only take effect on the following cycle 2019-07-14 10:44:56 -05:00
SaxxonPike e8902b829a C64: Apparently the 6502X core needs interrupts delayed by a cycle, do that with IRQ and NMI 2019-07-14 10:43:52 -05:00
SaxxonPike 3bbfb98fc2 C64: Split out VIC IRQ delays 2019-07-13 19:28:44 -05:00
SaxxonPike 154eefd2ad C64: Give BA/IRQ counting another go, seems to resolve many issues 2019-07-13 16:51:30 -05:00
SaxxonPike db38d5e65b C64: Try counting IRQ and BA correctly 2019-07-13 15:28:57 -05:00
SaxxonPike f22c9b7abd C64: CPU reads open bus when !AEC is asserted 2019-07-13 15:25:40 -05:00
SaxxonPike 894adbb610 C64: Remove an unused variable 2019-07-13 15:02:18 -05:00
SaxxonPike 76679bc8bc C64: Use the correct background color in bitmapped modes for 0 2019-07-13 15:01:11 -05:00
SaxxonPike bd20b355f0 C64: Writing to CPU port writes open bus data to 00/01 2019-07-13 14:06:23 -05:00
SaxxonPike f18e7c8833 C64: Make the system debuggable for once 2019-07-13 13:15:50 -05:00
SaxxonPike cae3340946 C64: No need to expose these with the CPU link in place 2019-07-13 12:53:34 -05:00
SaxxonPike 3369dbf43f C64: IRQ is implemented as a delay line; no delay added (yet) 2019-07-13 12:51:39 -05:00
SaxxonPike d39f3e2e61 6502X: pending IRQs are not delayed when !RDY is asserted 2019-07-13 12:31:09 -05:00
SaxxonPike d62f2ac3fe C64: 0F7 is a badline eligible raster (fixes 26-line text demo in Frodo test suite) 2019-07-13 01:41:58 -05:00
SaxxonPike e6871b2cc3 C64: Move VIC raster IRQ to phase 1 2019-07-13 00:27:08 -05:00
SaxxonPike dbf6b39e7f C64: Split out VIC phase1/phase2 2019-07-12 23:51:55 -05:00
SaxxonPike 85bc92b688 Merge remote-tracking branch 'origin/c64-refactor' into c64-refactor
# Conflicts:
#	BizHawk.Emulation.Cores/Computers/Commodore64/MOS/Chip6510.cs
2019-07-12 22:10:08 -05:00
SaxxonPike 0a7dc52aa0 C64: BA and raster IRQ cleanup 2019-07-09 22:41:12 -05:00
SaxxonPike 3a135c7c26 C64: Raster interrupt bit can be set even if not enabled, just won't actually assert IRQ 2019-07-09 21:40:03 -05:00
SaxxonPike e63d10b608 C64: Interrupts generated in phase 2 by the VIC won't trigger for the CPU until next cycle, also buffer BA 2019-07-09 20:55:14 -05:00
SaxxonPike b471fdc692 C64: The CPU can trigger VIC badlines on its own (needed for VSP) 2019-07-09 20:53:54 -05:00
SaxxonPike 2abe832289 C64: AEC does not prohibit the CPU from functioning, only BA (RDY) does 2019-07-09 20:52:51 -05:00
SaxxonPike a8fd85157c VIC: Use correct color mapping for non-multicolor bitmap mode 2019-07-09 08:02:55 -05:00
SaxxonPike 83b6553749 VIC: Respect idle state background color registers, plus black in undocumented gfx mode 2019-07-09 06:58:13 -05:00
SaxxonPike 89fa153477 VIC: Resolve background color registers separately to color matrix memory 2019-07-09 06:55:55 -05:00
SaxxonPike 9f733d3e7a VIC: More accurate pixel pipeline 2019-07-09 05:26:26 -05:00
SaxxonPike d36e02045b C64: Optimize the RNG for 1541 flux transitions. (same output) 2019-07-06 16:32:21 -05:00
SaxxonPike 3bf37f1c17 C64: No need for LagCycles anymore. 2019-07-06 16:29:14 -05:00
SaxxonPike 6ed11de85b C64: Soft/Hard reset: it's about time 2019-07-06 01:19:58 -05:00