SaxxonPike
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cc077ac459
|
C64: Sprite collision interrupts do not fire if the collision registers are not already clear
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2019-07-28 09:44:47 -05:00 |
|
SaxxonPike
|
f4c64ddf38
|
C64: Implement the color register decode / priority logic
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2019-07-26 21:51:44 -05:00 |
|
SaxxonPike
|
0de5dedb3e
|
C64: Clean up things (again) for savestates sake.
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2019-07-26 02:32:56 -05:00 |
|
SaxxonPike
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ac52d0e5f6
|
C64: Raster IRQ is edge triggered, how'd I miss this?
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2019-07-26 01:40:31 -05:00 |
|
SaxxonPike
|
92eb569b12
|
C64: Nudge BA signal generation back a half cycle
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2019-07-26 01:19:52 -05:00 |
|
SaxxonPike
|
4e5179b495
|
C64: Pass sprite collision in border tests
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2019-07-25 23:43:04 -05:00 |
|
SaxxonPike
|
f9b6af9ea9
|
C64: Pass VICII/rasterirq
|
2019-07-25 22:58:32 -05:00 |
|
SaxxonPike
|
fba98fef2c
|
C64: Actually proper border checking.
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2019-07-25 22:35:12 -05:00 |
|
SaxxonPike
|
e4a3c2f410
|
C64: Proper border checking.
|
2019-07-25 21:38:33 -05:00 |
|
SaxxonPike
|
15e71b93eb
|
C64: Simplified render logic.
|
2019-07-25 19:21:42 -05:00 |
|
SaxxonPike
|
558f0c6873
|
C64: Don't offset hblank anymore, not needed
|
2019-07-25 15:53:54 -05:00 |
|
SaxxonPike
|
c02eeaf08c
|
C64: Implement sprite crunch and better vsync rates.
|
2019-07-25 15:42:09 -05:00 |
|
SaxxonPike
|
9f638ec1c2
|
C64: Add sprite crunch table.
|
2019-07-25 14:25:48 -05:00 |
|
SaxxonPike
|
cd7ea15ce5
|
C64: Offset graphics and sprite output to match BG color registers.
|
2019-07-25 12:11:58 -05:00 |
|
SaxxonPike
|
58b7630f71
|
C64: Get rid of all the pixel buffer/delay hacks in the VIC.
|
2019-07-25 10:52:10 -05:00 |
|
SaxxonPike
|
361860361a
|
C64: 1541 SYNC is present for longer on VIA1 PB7
|
2019-07-23 06:57:07 -05:00 |
|
SaxxonPike
|
01d1bb47b6
|
C64: Sprite DMA clears out existing bits
|
2019-07-23 06:54:28 -05:00 |
|
SaxxonPike
|
b662646f2c
|
C64: Don't need separate PRG support anymore, they are simulated on disk
|
2019-07-23 04:53:24 -05:00 |
|
SaxxonPike
|
47880fabb7
|
Merge branch 'master' into c64-refactor
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2019-07-23 04:52:35 -05:00 |
|
Tony Konzel
|
58513ea22f
|
Merge pull request #1607 from TASVideos/c64-refactor
C64: General improvements (disk writing, CIA/VIA timers, 6502X decimal mode fixes)
|
2019-07-22 09:29:22 -05:00 |
|
alyosha-tas
|
fca98ffe34
|
Various code cleanup
|
2019-07-21 09:05:07 -04:00 |
|
alyosha-tas
|
6a773ac272
|
Atari 2600: more bug fixes
|
2019-07-20 14:47:36 -04:00 |
|
SaxxonPike
|
1e5fe55f30
|
C64: Don't reallocate the SID filter buffer every time (purely perf)
|
2019-07-19 19:09:08 -05:00 |
|
alyosha-tas
|
cf6cdf4ecc
|
A2600: Bug fixes and Improvements
|
2019-07-19 20:03:30 -04:00 |
|
SaxxonPike
|
a119420c79
|
C64: VC count enable seems to need to be delayed by 1 cycle after badline
- which doesn't affect normal operation
- which DOES affect VSP
|
2019-07-14 20:22:07 -05:00 |
|
SaxxonPike
|
4d6ed8d6c8
|
C64: Savestate should include the new variables
|
2019-07-14 16:32:53 -05:00 |
|
alyosha-tas
|
7f29c4173b
|
A2600: Fix a test rom mapper
|
2019-07-14 17:06:50 -04:00 |
|
SaxxonPike
|
ad7cae8b71
|
Merge branch 'master' into c64-refactor
|
2019-07-14 10:45:44 -05:00 |
|
SaxxonPike
|
8e8d3a6a1b
|
C64: Writes to some registers on the VIC in phase 2 by the CPU should only take effect on the following cycle
|
2019-07-14 10:44:56 -05:00 |
|
SaxxonPike
|
e8902b829a
|
C64: Apparently the 6502X core needs interrupts delayed by a cycle, do that with IRQ and NMI
|
2019-07-14 10:43:52 -05:00 |
|
SaxxonPike
|
3bbfb98fc2
|
C64: Split out VIC IRQ delays
|
2019-07-13 19:28:44 -05:00 |
|
alyosha-tas
|
7df8ed1f27
|
A2600: Add HMCLR delay
|
2019-07-13 18:33:54 -04:00 |
|
SaxxonPike
|
154eefd2ad
|
C64: Give BA/IRQ counting another go, seems to resolve many issues
|
2019-07-13 16:51:30 -05:00 |
|
SaxxonPike
|
db38d5e65b
|
C64: Try counting IRQ and BA correctly
|
2019-07-13 15:28:57 -05:00 |
|
SaxxonPike
|
f22c9b7abd
|
C64: CPU reads open bus when !AEC is asserted
|
2019-07-13 15:25:40 -05:00 |
|
SaxxonPike
|
894adbb610
|
C64: Remove an unused variable
|
2019-07-13 15:02:18 -05:00 |
|
SaxxonPike
|
76679bc8bc
|
C64: Use the correct background color in bitmapped modes for 0
|
2019-07-13 15:01:11 -05:00 |
|
SaxxonPike
|
bd20b355f0
|
C64: Writing to CPU port writes open bus data to 00/01
|
2019-07-13 14:06:23 -05:00 |
|
SaxxonPike
|
f18e7c8833
|
C64: Make the system debuggable for once
|
2019-07-13 13:15:50 -05:00 |
|
SaxxonPike
|
cae3340946
|
C64: No need to expose these with the CPU link in place
|
2019-07-13 12:53:34 -05:00 |
|
SaxxonPike
|
3369dbf43f
|
C64: IRQ is implemented as a delay line; no delay added (yet)
|
2019-07-13 12:51:39 -05:00 |
|
SaxxonPike
|
d39f3e2e61
|
6502X: pending IRQs are not delayed when !RDY is asserted
|
2019-07-13 12:31:09 -05:00 |
|
SaxxonPike
|
bf2cba0e23
|
6502X: remove a comment (this is indeed a dummy fetch)
|
2019-07-13 11:38:03 -05:00 |
|
SaxxonPike
|
d62f2ac3fe
|
C64: 0F7 is a badline eligible raster (fixes 26-line text demo in Frodo test suite)
|
2019-07-13 01:41:58 -05:00 |
|
SaxxonPike
|
e6871b2cc3
|
C64: Move VIC raster IRQ to phase 1
|
2019-07-13 00:27:08 -05:00 |
|
SaxxonPike
|
dbf6b39e7f
|
C64: Split out VIC phase1/phase2
|
2019-07-12 23:51:55 -05:00 |
|
SaxxonPike
|
85bc92b688
|
Merge remote-tracking branch 'origin/c64-refactor' into c64-refactor
# Conflicts:
# BizHawk.Emulation.Cores/Computers/Commodore64/MOS/Chip6510.cs
|
2019-07-12 22:10:08 -05:00 |
|
alyosha-tas
|
66cf00a917
|
Vectrex: Add frame buffer to state an set to released
|
2019-07-12 18:15:25 -04:00 |
|
alyosha-tas
|
90436811b9
|
GG: Fix World Derby
|
2019-07-12 15:07:58 -04:00 |
|
alyosha-tas
|
5e2b097902
|
MC6809: fix DAA
|
2019-07-10 19:30:17 -04:00 |