2013-11-04 00:36:15 +00:00
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using BizHawk.Common;
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2013-11-13 03:32:25 +00:00
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namespace BizHawk.Emulation.Cores.Atari.Atari2600
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2012-03-31 20:53:14 +00:00
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{
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2012-04-29 21:01:06 +00:00
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/*
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3E (Boulderdash
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-----
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This works similar to 3F (Tigervision) above, except RAM has been added. The range of
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addresses has been restricted, too. Only 3E and 3F can be written to now.
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1000-17FF - this bank is selectable
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1800-1FFF - this bank is the last 2K of the ROM
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To select a particular 2K ROM bank, its number is poked into address 3F. Because there's
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8 bits, there's enough for 256 2K banks, or a maximum of 512K of ROM.
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Writing to 3E, however, is what's new. Writing here selects a 1K RAM bank into
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1000-17FF. The example (Boulderdash) uses 16K of RAM, however there's theoretically
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enough space for 256K of RAM. When RAM is selected, 1000-13FF is the read port while
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1400-17FF is the write port.
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*/
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2014-04-02 21:27:14 +00:00
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internal class m3E : MapperBase
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2012-03-31 20:53:14 +00:00
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{
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2014-04-03 19:58:47 +00:00
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private int _lowbank_2K;
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private int _rambank_1K;
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private bool _hasRam;
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2014-04-05 02:42:23 +00:00
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private ByteBuffer _ram = new ByteBuffer(256 * 1024); // Up to 256k
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2012-03-31 20:53:14 +00:00
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2012-10-20 01:51:38 +00:00
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public override void SyncState(Serializer ser)
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{
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base.SyncState(ser);
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2014-04-03 19:58:47 +00:00
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ser.Sync("lowbank_2k", ref _lowbank_2K);
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ser.Sync("rambank_1k", ref _rambank_1K);
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ser.Sync("cart_ram", ref _ram);
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ser.Sync("hasRam", ref _hasRam);
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2012-10-20 01:51:38 +00:00
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}
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2014-04-06 22:40:10 +00:00
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public override void HardReset()
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{
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_lowbank_2K = 0;
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_rambank_1K = 0;
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_hasRam = false;
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_ram = new ByteBuffer(256 * 1024);
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base.HardReset();
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}
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2012-10-20 01:51:38 +00:00
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public override void Dispose()
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{
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base.Dispose();
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2014-04-03 19:58:47 +00:00
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_ram.Dispose();
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2012-10-20 01:51:38 +00:00
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}
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public override byte ReadMemory(ushort addr)
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{
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if (addr < 0x1000)
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{
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return base.ReadMemory(addr);
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}
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2014-04-03 19:58:47 +00:00
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if (addr < 0x17FF) // Low 2k Bank
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2012-10-20 01:51:38 +00:00
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{
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2014-04-03 19:58:47 +00:00
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if (_hasRam)
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2012-10-20 01:51:38 +00:00
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{
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if (addr < 0x13FF)
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{
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2014-04-03 19:58:47 +00:00
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return _ram[(addr & 0x03FF) + (_rambank_1K << 10)];
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2012-10-20 01:51:38 +00:00
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}
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2014-04-03 19:58:47 +00:00
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return _ram[(addr & 0x03FF) + (_rambank_1K << 10)] = 0xFF; // Reading from the write port triggers an unwanted write
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2013-03-11 01:46:12 +00:00
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}
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2014-04-03 19:58:47 +00:00
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2014-04-05 14:13:05 +00:00
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return Core.Rom[(_lowbank_2K << 11) + (addr & 0x07FF)];
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2013-03-11 01:46:12 +00:00
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}
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2014-04-03 19:58:47 +00:00
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if (addr < 0x2000) // High bank fixed to last 2k of ROM
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2013-03-11 01:46:12 +00:00
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{
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2014-04-05 14:13:05 +00:00
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return Core.Rom[(Core.Rom.Length - 2048) + (addr & 0x07FF)];
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2013-03-11 01:46:12 +00:00
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}
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2014-04-03 19:58:47 +00:00
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2013-03-11 01:46:12 +00:00
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return base.ReadMemory(addr);
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}
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public override byte PeekMemory(ushort addr)
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{
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if (addr < 0x1000)
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{
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return base.ReadMemory(addr);
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}
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2014-04-03 19:58:47 +00:00
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if (addr < 0x17FF) // Low 2k Bank
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2013-03-11 01:46:12 +00:00
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{
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2014-04-03 19:58:47 +00:00
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if (_hasRam)
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2013-03-11 01:46:12 +00:00
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{
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if (addr < 0x13FF)
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{
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2014-04-03 19:58:47 +00:00
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return _ram[(addr & 0x03FF) + (_rambank_1K << 10)];
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2013-03-11 01:46:12 +00:00
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}
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2014-04-03 19:58:47 +00:00
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return _ram[(addr & 0x03FF) + (_rambank_1K << 10)]; // Reading from the write port triggers an unwanted write
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2012-10-20 01:51:38 +00:00
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}
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2014-04-03 19:58:47 +00:00
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2014-04-05 14:13:05 +00:00
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return Core.Rom[(_lowbank_2K << 11) + (addr & 0x07FF)];
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2012-10-20 01:51:38 +00:00
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}
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2014-04-03 19:58:47 +00:00
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if (addr < 0x2000) // High bank fixed to last 2k of ROM
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2012-10-20 01:51:38 +00:00
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{
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2014-04-05 14:13:05 +00:00
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return Core.Rom[(Core.Rom.Length - 2048) + (addr & 0x07FF)];
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2012-10-20 01:51:38 +00:00
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}
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2014-04-03 19:58:47 +00:00
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2012-10-20 01:51:38 +00:00
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return base.ReadMemory(addr);
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}
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public override void WriteMemory(ushort addr, byte value)
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{
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if (addr < 0x1000)
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{
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if (addr == 0x003E)
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{
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2014-04-03 19:58:47 +00:00
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_hasRam = true;
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_rambank_1K = value;
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2012-10-20 01:51:38 +00:00
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}
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else if (addr == 0x003F)
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{
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2014-04-03 19:58:47 +00:00
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_hasRam = false;
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2014-04-05 14:13:05 +00:00
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if ((value << 11) < Core.Rom.Length)
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2012-10-20 01:51:38 +00:00
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{
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2014-04-03 19:58:47 +00:00
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_lowbank_2K = value;
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2012-10-20 01:51:38 +00:00
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}
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else
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{
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2014-04-05 14:13:05 +00:00
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_lowbank_2K = value & (Core.Rom.Length >> 11);
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2012-10-20 01:51:38 +00:00
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}
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}
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base.WriteMemory(addr, value);
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}
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else if (addr < 0x1400)
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{
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2014-04-03 19:58:47 +00:00
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// Writing to the read port, for shame!
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2012-10-20 01:51:38 +00:00
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}
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2014-04-03 19:58:47 +00:00
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else if (addr < 0x1800) // Write port
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2012-10-20 01:51:38 +00:00
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{
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2014-04-03 19:58:47 +00:00
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_ram[(_rambank_1K << 10) + (addr & 0x3FF)] = value;
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2012-10-20 01:51:38 +00:00
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}
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}
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2012-03-31 20:53:14 +00:00
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}
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}
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