Triang3l
|
10a3dc6d94
|
[D3D12] ROV: 32-bit loading, except for 7e3
|
2018-10-12 20:07:00 +03:00 |
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Triang3l
|
013087108b
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[D3D12] ROV: Used render targets flags
|
2018-10-12 12:32:48 +03:00 |
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Triang3l
|
3dc15dbb44
|
[D3D12] ROV: 32bpp storing (except for 7e3)
|
2018-10-12 09:59:31 +03:00 |
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Triang3l
|
615fade64e
|
[D3D12] ROV: Fix EDRAM pitch shader constant size
|
2018-10-11 19:59:35 +03:00 |
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Triang3l
|
197b1d8114
|
[D3D12] ROV: EDRAM offset calculation
|
2018-10-11 10:16:36 +03:00 |
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Triang3l
|
8cde541596
|
[D3D12] ROV: Binding
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2018-10-10 18:33:39 +03:00 |
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Triang3l
|
67e5cb8681
|
[D3D12] ROV: Disable RTs when using ROV
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2018-10-10 16:37:35 +03:00 |
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Triang3l
|
6d2e74325c
|
[D3D12] ROV: Check if supported
|
2018-10-10 14:30:29 +03:00 |
|
Triang3l
|
90f700c785
|
[D3D12] Analysis: Display fetch constant contents if type is wrong
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2018-10-10 12:44:02 +03:00 |
|
Triang3l
|
7bc79cbd01
|
[D3D12] Signed texture SRVs
|
2018-10-09 21:44:18 +03:00 |
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Triang3l
|
7603de218b
|
[D3D12] DXBC part of signed textures
|
2018-10-09 08:31:09 +03:00 |
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Triang3l
|
6a6e63060b
|
[D3D12] Submit barriers before uploading gamma ramp
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2018-10-08 19:42:02 +03:00 |
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Triang3l
|
fccebae703
|
[D3D12] PIX: Capture with F4, disable tiled resources when attached
|
2018-10-08 12:05:15 +03:00 |
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Triang3l
|
16dc6e4100
|
[D3D12] DXBC: In getWeights, apply the offset for unnormalized coordinates only when needed
|
2018-10-07 21:51:18 +03:00 |
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Triang3l
|
685d3074f4
|
[D3D12] Hash sampler bindings and refactor names in UpdateBindings
|
2018-10-07 20:21:18 +03:00 |
|
Triang3l
|
3de2b5e692
|
[D3D12] Code style fixes
|
2018-10-07 17:30:12 +03:00 |
|
Triang3l
|
400e6b7137
|
[D3D12] Don't replace strip reset index when not used, profile ConvertPrimitives
|
2018-10-07 15:26:47 +03:00 |
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Triang3l
|
9194c3f8b0
|
[D3D12] Primitive converter cache and strip restart, texture invalidation acquire/release
|
2018-10-06 20:27:48 +03:00 |
|
Triang3l
|
128ac2a3f9
|
[D3D12] Align mipmap storage size to power of 2 when untiling
|
2018-10-05 20:48:11 +03:00 |
|
Triang3l
|
34946c57b0
|
[D3D12] Rename XeTextureCopy to XeTextureLoad in shaders
|
2018-10-05 20:02:36 +03:00 |
|
Triang3l
|
9dc7dfab02
|
[D3D12] Fix currently bound textures not reloaded if not needed immediately
|
2018-10-05 09:20:51 +03:00 |
|
Triang3l
|
d827bbeb6c
|
[D3D12] Fix texture binding hashing
|
2018-10-04 23:57:08 +03:00 |
|
Triang3l
|
131525e44d
|
[D3D12] Don't create SRVs if textures not changed
|
2018-10-04 14:36:48 +03:00 |
|
Triang3l
|
b77ffe3df6
|
[D3D12] Output gamma ramp
|
2018-10-03 14:36:17 +03:00 |
|
Triang3l
|
c624bf8c49
|
[D3D12] DXBC: Use a0 for maxas scratch because ps must not be modified without a write mask
|
2018-10-02 21:24:50 +03:00 |
|
Triang3l
|
90f586383a
|
[D3D12] Make tiled resources optional - not available on old Intel HD Graphics
|
2018-10-02 17:36:10 +03:00 |
|
Triang3l
|
9e17bbf016
|
[D3D12] Refactor system and bool/loop constants into separate descriptor ranges
|
2018-10-02 16:34:22 +03:00 |
|
Triang3l
|
2588aab89d
|
[GPU/D3D12] Float constant remapping fixes
|
2018-10-01 20:15:00 +03:00 |
|
Triang3l
|
c4599ff211
|
[D3D12] Compact float constants and don't split them into pages
|
2018-09-30 20:17:26 +03:00 |
|
Triang3l
|
eb50ebd885
|
[D3D12] Write to 8_8_8_8_GAMMA in gamma space
|
2018-09-29 13:30:05 +03:00 |
|
Triang3l
|
64209748e3
|
[D3D12] Better polygon offset scale
|
2018-09-29 12:01:09 +03:00 |
|
Triang3l
|
400747bf7c
|
[D3D12] Point sprite size
|
2018-09-29 11:25:03 +03:00 |
|
Triang3l
|
d9538e6cc2
|
[D3D12] Log unsupported texture formats and don't log texture invalidation
|
2018-09-27 10:27:55 +03:00 |
|
Triang3l
|
ea7d9e9060
|
[D3D12] Emulate reversed Z in shaders because it's unsupported on Nvidia
|
2018-09-26 20:46:24 +03:00 |
|
Triang3l
|
55f96c0f83
|
[D3D12] DXBC: Apply exp bias after alpha test
|
2018-09-26 16:20:04 +03:00 |
|
Triang3l
|
70103804c3
|
[D3D12] 8/16bpp resolves, fixed16 RT exp bias, RT format documentation
|
2018-09-26 16:10:23 +03:00 |
|
Triang3l
|
6e36101b42
|
[D3D12] Experimental write watch implementation for shared memory
|
2018-09-24 23:18:16 +03:00 |
|
Triang3l
|
005e590c92
|
[D3D12] SHM upload range cleanup and mask index buffer address
|
2018-09-23 18:37:41 +03:00 |
|
Triang3l
|
ecfa70284e
|
[D3D12] Treat gamma/as_16 EDRAM formats the same as their base formats
|
2018-09-22 19:22:57 +03:00 |
|
Triang3l
|
133604f249
|
[D3D12] Decompress textures if their size is not 4x4-aligned
|
2018-09-22 19:03:25 +03:00 |
|
Triang3l
|
bb24521c2b
|
[D3D12] DXT5 decompression shader (not used yet)
|
2018-09-22 15:52:07 +03:00 |
|
Triang3l
|
4d1b3caf8c
|
[D3D12] DXBC: Fix max4 instruction length
|
2018-09-22 13:36:04 +03:00 |
|
Triang3l
|
6e3cf5dd22
|
[D3D12] Cleanup selection in shaders and add some DXT5 alpha code
|
2018-09-21 21:22:33 +03:00 |
|
Triang3l
|
17e3f09c1e
|
[D3D12] DXT1 decompression shader
|
2018-09-21 08:55:55 +03:00 |
|
Triang3l
|
1f248572ac
|
[D3D12] Better explanation of dxbc_switch
|
2018-09-19 23:26:45 +03:00 |
|
Triang3l
|
9daea21edc
|
[D3D12] Don't use _COLOR blend modes for alpha
|
2018-09-19 22:54:35 +03:00 |
|
Triang3l
|
cbd36218bf
|
[D3D12] DXBC: Use switch instead of if for flow control (experimentally)
|
2018-09-19 21:25:58 +03:00 |
|
Triang3l
|
4db3a927ad
|
[D3D12] Remove ID3DBlob from D3D12Shader
|
2018-09-19 17:08:48 +03:00 |
|
Triang3l
|
ed66694319
|
[D3D12] Slightly better logging
|
2018-09-19 16:50:13 +03:00 |
|
Triang3l
|
fdd536f572
|
[D3D12] Swap columns 0:39 and 40:79 of depth buffers in EDRAM
|
2018-09-19 11:40:28 +03:00 |