OK, this is the first pass at a huge reorganization of the debugger
classes. First off, the distella code has been integrated into a
DiStella class. This code isn't yet tied to the debugger, but it does
at least compile and generate valid output.
The RamDebug class has been replaced by a CartDebug class, which
takes responsibility for the previous RamDebug stuff as well as
things related to Cart address space (read from write ports,
disassembly, etc).
Fixed E7 bankswitching when reading from the write port in the upper
256byte area.
Fixed 'read from write port functionality' in general for all carts
that supported it previously. Basically, if _rwport is enabled, the
address is checked to be an actual read (vs. one that's part of a
normal write cycle), *and* it's actually an illegal access (each
cart/bankswitch type now provides a hint to indicate this condition).
Still TODO is clean up the rework, properly integrate DiStella, and
fix labels and defines (which seem to be completely broken).
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1922 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-01-17 16:48:45 +00:00
|
|
|
//============================================================================
|
|
|
|
|
//
|
|
|
|
|
// SSSS tt lll lll
|
|
|
|
|
// SS SS tt ll ll
|
|
|
|
|
// SS tttttt eeee ll ll aaaa
|
|
|
|
|
// SSSS tt ee ee ll ll aa
|
|
|
|
|
// SS tt eeeeee ll ll aaaaa -- "An Atari 2600 VCS Emulator"
|
|
|
|
|
// SS SS tt ee ll ll aa aa
|
|
|
|
|
// SSSS ttt eeeee llll llll aaaaa
|
|
|
|
|
//
|
2014-01-12 17:23:42 +00:00
|
|
|
// Copyright (c) 1995-2014 by Bradford W. Mott, Stephen Anthony
|
2010-04-10 21:37:23 +00:00
|
|
|
// and the Stella Team
|
OK, this is the first pass at a huge reorganization of the debugger
classes. First off, the distella code has been integrated into a
DiStella class. This code isn't yet tied to the debugger, but it does
at least compile and generate valid output.
The RamDebug class has been replaced by a CartDebug class, which
takes responsibility for the previous RamDebug stuff as well as
things related to Cart address space (read from write ports,
disassembly, etc).
Fixed E7 bankswitching when reading from the write port in the upper
256byte area.
Fixed 'read from write port functionality' in general for all carts
that supported it previously. Basically, if _rwport is enabled, the
address is checked to be an actual read (vs. one that's part of a
normal write cycle), *and* it's actually an illegal access (each
cart/bankswitch type now provides a hint to indicate this condition).
Still TODO is clean up the rework, properly integrate DiStella, and
fix labels and defines (which seem to be completely broken).
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1922 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-01-17 16:48:45 +00:00
|
|
|
//
|
2010-04-10 21:37:23 +00:00
|
|
|
// See the file "License.txt" for information on usage and redistribution of
|
OK, this is the first pass at a huge reorganization of the debugger
classes. First off, the distella code has been integrated into a
DiStella class. This code isn't yet tied to the debugger, but it does
at least compile and generate valid output.
The RamDebug class has been replaced by a CartDebug class, which
takes responsibility for the previous RamDebug stuff as well as
things related to Cart address space (read from write ports,
disassembly, etc).
Fixed E7 bankswitching when reading from the write port in the upper
256byte area.
Fixed 'read from write port functionality' in general for all carts
that supported it previously. Basically, if _rwport is enabled, the
address is checked to be an actual read (vs. one that's part of a
normal write cycle), *and* it's actually an illegal access (each
cart/bankswitch type now provides a hint to indicate this condition).
Still TODO is clean up the rework, properly integrate DiStella, and
fix labels and defines (which seem to be completely broken).
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1922 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-01-17 16:48:45 +00:00
|
|
|
// this file, and for a DISCLAIMER OF ALL WARRANTIES.
|
|
|
|
|
//
|
|
|
|
|
// $Id$
|
|
|
|
|
//============================================================================
|
|
|
|
|
|
2013-03-04 23:35:26 +00:00
|
|
|
#include <time.h>
|
|
|
|
|
|
OK, this is the first pass at a huge reorganization of the debugger
classes. First off, the distella code has been integrated into a
DiStella class. This code isn't yet tied to the debugger, but it does
at least compile and generate valid output.
The RamDebug class has been replaced by a CartDebug class, which
takes responsibility for the previous RamDebug stuff as well as
things related to Cart address space (read from write ports,
disassembly, etc).
Fixed E7 bankswitching when reading from the write port in the upper
256byte area.
Fixed 'read from write port functionality' in general for all carts
that supported it previously. Basically, if _rwport is enabled, the
address is checked to be an actual read (vs. one that's part of a
normal write cycle), *and* it's actually an illegal access (each
cart/bankswitch type now provides a hint to indicate this condition).
Still TODO is clean up the rework, properly integrate DiStella, and
fix labels and defines (which seem to be completely broken).
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1922 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-01-17 16:48:45 +00:00
|
|
|
#include "bspf.hxx"
|
|
|
|
|
#include "System.hxx"
|
2010-10-18 18:39:57 +00:00
|
|
|
#include "FSNode.hxx"
|
2010-02-01 20:00:50 +00:00
|
|
|
#include "DiStella.hxx"
|
2010-10-18 18:39:57 +00:00
|
|
|
#include "Debugger.hxx"
|
2010-03-05 22:02:12 +00:00
|
|
|
#include "CpuDebug.hxx"
|
2010-10-18 18:39:57 +00:00
|
|
|
#include "OSystem.hxx"
|
2010-09-05 17:57:21 +00:00
|
|
|
#include "Settings.hxx"
|
2013-03-04 23:35:26 +00:00
|
|
|
#include "Version.hxx"
|
OK, this is the first pass at a huge reorganization of the debugger
classes. First off, the distella code has been integrated into a
DiStella class. This code isn't yet tied to the debugger, but it does
at least compile and generate valid output.
The RamDebug class has been replaced by a CartDebug class, which
takes responsibility for the previous RamDebug stuff as well as
things related to Cart address space (read from write ports,
disassembly, etc).
Fixed E7 bankswitching when reading from the write port in the upper
256byte area.
Fixed 'read from write port functionality' in general for all carts
that supported it previously. Basically, if _rwport is enabled, the
address is checked to be an actual read (vs. one that's part of a
normal write cycle), *and* it's actually an illegal access (each
cart/bankswitch type now provides a hint to indicate this condition).
Still TODO is clean up the rework, properly integrate DiStella, and
fix labels and defines (which seem to be completely broken).
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1922 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-01-17 16:48:45 +00:00
|
|
|
#include "CartDebug.hxx"
|
2013-04-20 22:23:42 +00:00
|
|
|
#include "CartDebugWidget.hxx"
|
2014-06-13 16:28:28 +00:00
|
|
|
#include "CartRamWidget.hxx"
|
2013-07-27 22:28:41 +00:00
|
|
|
using namespace Common;
|
OK, this is the first pass at a huge reorganization of the debugger
classes. First off, the distella code has been integrated into a
DiStella class. This code isn't yet tied to the debugger, but it does
at least compile and generate valid output.
The RamDebug class has been replaced by a CartDebug class, which
takes responsibility for the previous RamDebug stuff as well as
things related to Cart address space (read from write ports,
disassembly, etc).
Fixed E7 bankswitching when reading from the write port in the upper
256byte area.
Fixed 'read from write port functionality' in general for all carts
that supported it previously. Basically, if _rwport is enabled, the
address is checked to be an actual read (vs. one that's part of a
normal write cycle), *and* it's actually an illegal access (each
cart/bankswitch type now provides a hint to indicate this condition).
Still TODO is clean up the rework, properly integrate DiStella, and
fix labels and defines (which seem to be completely broken).
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1922 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-01-17 16:48:45 +00:00
|
|
|
|
|
|
|
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
2010-09-06 00:17:51 +00:00
|
|
|
CartDebug::CartDebug(Debugger& dbg, Console& console, const OSystem& osystem)
|
OK, this is the first pass at a huge reorganization of the debugger
classes. First off, the distella code has been integrated into a
DiStella class. This code isn't yet tied to the debugger, but it does
at least compile and generate valid output.
The RamDebug class has been replaced by a CartDebug class, which
takes responsibility for the previous RamDebug stuff as well as
things related to Cart address space (read from write ports,
disassembly, etc).
Fixed E7 bankswitching when reading from the write port in the upper
256byte area.
Fixed 'read from write port functionality' in general for all carts
that supported it previously. Basically, if _rwport is enabled, the
address is checked to be an actual read (vs. one that's part of a
normal write cycle), *and* it's actually an illegal access (each
cart/bankswitch type now provides a hint to indicate this condition).
Still TODO is clean up the rework, properly integrate DiStella, and
fix labels and defines (which seem to be completely broken).
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1922 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-01-17 16:48:45 +00:00
|
|
|
: DebuggerSystem(dbg, console),
|
2010-09-06 00:17:51 +00:00
|
|
|
myOSystem(osystem),
|
2014-11-07 14:26:56 +00:00
|
|
|
myDebugWidget(nullptr),
|
2014-10-28 16:44:18 +00:00
|
|
|
myAddrToLineIsROM(true),
|
2010-05-12 00:04:14 +00:00
|
|
|
myRWPortAddress(0),
|
2013-03-11 19:43:19 +00:00
|
|
|
myLabelLength(8) // longest pre-defined label
|
OK, this is the first pass at a huge reorganization of the debugger
classes. First off, the distella code has been integrated into a
DiStella class. This code isn't yet tied to the debugger, but it does
at least compile and generate valid output.
The RamDebug class has been replaced by a CartDebug class, which
takes responsibility for the previous RamDebug stuff as well as
things related to Cart address space (read from write ports,
disassembly, etc).
Fixed E7 bankswitching when reading from the write port in the upper
256byte area.
Fixed 'read from write port functionality' in general for all carts
that supported it previously. Basically, if _rwport is enabled, the
address is checked to be an actual read (vs. one that's part of a
normal write cycle), *and* it's actually an illegal access (each
cart/bankswitch type now provides a hint to indicate this condition).
Still TODO is clean up the rework, properly integrate DiStella, and
fix labels and defines (which seem to be completely broken).
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1922 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-01-17 16:48:45 +00:00
|
|
|
{
|
2014-07-24 17:15:28 +00:00
|
|
|
// Add Zero-page RAM addresses
|
|
|
|
|
for(uInt32 i = 0x80; i <= 0xFF; ++i)
|
|
|
|
|
{
|
|
|
|
|
myState.rport.push_back(i);
|
|
|
|
|
myState.wport.push_back(i);
|
|
|
|
|
myOldState.rport.push_back(i);
|
|
|
|
|
myOldState.wport.push_back(i);
|
|
|
|
|
}
|
OK, this is the first pass at a huge reorganization of the debugger
classes. First off, the distella code has been integrated into a
DiStella class. This code isn't yet tied to the debugger, but it does
at least compile and generate valid output.
The RamDebug class has been replaced by a CartDebug class, which
takes responsibility for the previous RamDebug stuff as well as
things related to Cart address space (read from write ports,
disassembly, etc).
Fixed E7 bankswitching when reading from the write port in the upper
256byte area.
Fixed 'read from write port functionality' in general for all carts
that supported it previously. Basically, if _rwport is enabled, the
address is checked to be an actual read (vs. one that's part of a
normal write cycle), *and* it's actually an illegal access (each
cart/bankswitch type now provides a hint to indicate this condition).
Still TODO is clean up the rework, properly integrate DiStella, and
fix labels and defines (which seem to be completely broken).
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1922 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-01-17 16:48:45 +00:00
|
|
|
|
2010-08-30 12:04:56 +00:00
|
|
|
// Create bank information for each potential bank, and an extra one for ZP RAM
|
2013-03-13 21:16:14 +00:00
|
|
|
// Banksizes greater than 4096 indicate multi-bank ROMs, but we handle only
|
|
|
|
|
// 4K pieces at a time
|
|
|
|
|
// Banksizes less than 4K use the actual value
|
2013-03-14 12:25:35 +00:00
|
|
|
int banksize = 0;
|
|
|
|
|
myConsole.cartridge().getImage(banksize);
|
|
|
|
|
|
2013-03-14 13:22:26 +00:00
|
|
|
BankInfo info;
|
|
|
|
|
info.size = BSPF_min(banksize, 4096);
|
2010-09-05 17:57:21 +00:00
|
|
|
for(int i = 0; i < myConsole.cartridge().bankCount(); ++i)
|
2010-08-30 12:04:56 +00:00
|
|
|
myBankInfo.push_back(info);
|
2013-03-14 13:22:26 +00:00
|
|
|
|
2010-09-06 23:29:05 +00:00
|
|
|
info.size = 128; // ZP RAM
|
2010-09-05 17:57:21 +00:00
|
|
|
myBankInfo.push_back(info);
|
2010-03-05 22:02:12 +00:00
|
|
|
|
|
|
|
|
// We know the address for the startup bank right now
|
2010-08-30 12:04:56 +00:00
|
|
|
myBankInfo[myConsole.cartridge().startBank()].addressList.push_back(myDebugger.dpeek(0xfffc));
|
2010-08-19 21:48:28 +00:00
|
|
|
addLabel("START", myDebugger.dpeek(0xfffc));
|
2010-04-03 12:45:20 +00:00
|
|
|
|
|
|
|
|
// Add system equates
|
2013-05-19 20:55:25 +00:00
|
|
|
for(uInt16 addr = 0x00; addr <= 0x0F; ++addr)
|
2013-03-05 18:01:55 +00:00
|
|
|
{
|
2013-05-19 20:55:25 +00:00
|
|
|
if(ourTIAMnemonicR[addr])
|
|
|
|
|
mySystemAddresses.insert(make_pair(ourTIAMnemonicR[addr], addr));
|
2013-03-05 18:01:55 +00:00
|
|
|
myReserved.TIARead[addr] = false;
|
|
|
|
|
}
|
2013-05-19 20:55:25 +00:00
|
|
|
for(uInt16 addr = 0x00; addr <= 0x3F; ++addr)
|
2013-03-05 18:01:55 +00:00
|
|
|
{
|
2013-05-19 20:55:25 +00:00
|
|
|
if(ourTIAMnemonicW[addr])
|
|
|
|
|
mySystemAddresses.insert(make_pair(ourTIAMnemonicW[addr], addr));
|
2013-03-05 18:01:55 +00:00
|
|
|
myReserved.TIAWrite[addr] = false;
|
|
|
|
|
}
|
2010-04-03 12:45:20 +00:00
|
|
|
for(uInt16 addr = 0x280; addr <= 0x297; ++addr)
|
2013-03-05 18:01:55 +00:00
|
|
|
{
|
2013-05-19 20:55:25 +00:00
|
|
|
if(ourIOMnemonic[addr-0x280])
|
|
|
|
|
mySystemAddresses.insert(make_pair(ourIOMnemonic[addr-0x280], addr));
|
2013-03-05 18:01:55 +00:00
|
|
|
myReserved.IOReadWrite[addr-0x280] = false;
|
|
|
|
|
}
|
2013-05-19 20:55:25 +00:00
|
|
|
for(uInt16 addr = 0x80; addr <= 0xFF; ++addr)
|
|
|
|
|
{
|
|
|
|
|
mySystemAddresses.insert(make_pair(ourZPMnemonic[addr-0x80], addr));
|
|
|
|
|
myReserved.ZPRAM[addr-0x80] = false;
|
|
|
|
|
}
|
2010-09-05 17:57:21 +00:00
|
|
|
|
2013-03-11 19:43:19 +00:00
|
|
|
myReserved.Label.clear();
|
2013-05-20 21:53:25 +00:00
|
|
|
myDisassembly.list.reserve(2048);
|
2013-03-11 19:43:19 +00:00
|
|
|
|
2010-09-05 17:57:21 +00:00
|
|
|
// Add settings for Distella
|
|
|
|
|
DiStella::settings.gfx_format =
|
2013-07-27 22:28:41 +00:00
|
|
|
myOSystem.settings().getInt("dis.gfxformat") == 16 ? Base::F_16 : Base::F_2;
|
2013-06-17 15:57:41 +00:00
|
|
|
DiStella::settings.resolve_code =
|
|
|
|
|
myOSystem.settings().getBool("dis.resolve");
|
2010-10-03 18:19:09 +00:00
|
|
|
DiStella::settings.show_addresses =
|
2012-05-27 19:27:55 +00:00
|
|
|
myOSystem.settings().getBool("dis.showaddr");
|
2013-03-10 22:12:37 +00:00
|
|
|
DiStella::settings.aflag = false; // Not currently configurable
|
2012-05-27 13:07:38 +00:00
|
|
|
DiStella::settings.fflag = true; // Not currently configurable
|
2013-03-10 22:12:37 +00:00
|
|
|
DiStella::settings.rflag = myOSystem.settings().getBool("dis.relocate");
|
|
|
|
|
DiStella::settings.bwidth = 9; // TODO - configure based on window size
|
2010-03-05 22:02:12 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
|
|
|
|
CartDebug::~CartDebug()
|
|
|
|
|
{
|
2010-04-03 12:45:20 +00:00
|
|
|
myUserLabels.clear();
|
|
|
|
|
myUserAddresses.clear();
|
2013-08-15 16:07:58 +00:00
|
|
|
myUserCLabels.clear();
|
|
|
|
|
// myUserCAddresses.clear();
|
2010-04-03 12:45:20 +00:00
|
|
|
mySystemAddresses.clear();
|
|
|
|
|
|
2010-08-30 12:04:56 +00:00
|
|
|
for(uInt32 i = 0; i < myBankInfo.size(); ++i)
|
|
|
|
|
{
|
|
|
|
|
myBankInfo[i].addressList.clear();
|
|
|
|
|
myBankInfo[i].directiveList.clear();
|
|
|
|
|
}
|
|
|
|
|
myBankInfo.clear();
|
OK, this is the first pass at a huge reorganization of the debugger
classes. First off, the distella code has been integrated into a
DiStella class. This code isn't yet tied to the debugger, but it does
at least compile and generate valid output.
The RamDebug class has been replaced by a CartDebug class, which
takes responsibility for the previous RamDebug stuff as well as
things related to Cart address space (read from write ports,
disassembly, etc).
Fixed E7 bankswitching when reading from the write port in the upper
256byte area.
Fixed 'read from write port functionality' in general for all carts
that supported it previously. Basically, if _rwport is enabled, the
address is checked to be an actual read (vs. one that's part of a
normal write cycle), *and* it's actually an illegal access (each
cart/bankswitch type now provides a hint to indicate this condition).
Still TODO is clean up the rework, properly integrate DiStella, and
fix labels and defines (which seem to be completely broken).
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1922 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-01-17 16:48:45 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
|
|
|
|
const DebuggerState& CartDebug::getState()
|
|
|
|
|
{
|
|
|
|
|
myState.ram.clear();
|
|
|
|
|
for(uInt32 i = 0; i < myState.rport.size(); ++i)
|
2010-06-03 12:41:49 +00:00
|
|
|
myState.ram.push_back(peek(myState.rport[i]));
|
OK, this is the first pass at a huge reorganization of the debugger
classes. First off, the distella code has been integrated into a
DiStella class. This code isn't yet tied to the debugger, but it does
at least compile and generate valid output.
The RamDebug class has been replaced by a CartDebug class, which
takes responsibility for the previous RamDebug stuff as well as
things related to Cart address space (read from write ports,
disassembly, etc).
Fixed E7 bankswitching when reading from the write port in the upper
256byte area.
Fixed 'read from write port functionality' in general for all carts
that supported it previously. Basically, if _rwport is enabled, the
address is checked to be an actual read (vs. one that's part of a
normal write cycle), *and* it's actually an illegal access (each
cart/bankswitch type now provides a hint to indicate this condition).
Still TODO is clean up the rework, properly integrate DiStella, and
fix labels and defines (which seem to be completely broken).
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1922 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-01-17 16:48:45 +00:00
|
|
|
|
2013-05-29 16:27:12 +00:00
|
|
|
if(myDebugWidget)
|
|
|
|
|
myState.bank = myDebugWidget->bankState();
|
|
|
|
|
|
OK, this is the first pass at a huge reorganization of the debugger
classes. First off, the distella code has been integrated into a
DiStella class. This code isn't yet tied to the debugger, but it does
at least compile and generate valid output.
The RamDebug class has been replaced by a CartDebug class, which
takes responsibility for the previous RamDebug stuff as well as
things related to Cart address space (read from write ports,
disassembly, etc).
Fixed E7 bankswitching when reading from the write port in the upper
256byte area.
Fixed 'read from write port functionality' in general for all carts
that supported it previously. Basically, if _rwport is enabled, the
address is checked to be an actual read (vs. one that's part of a
normal write cycle), *and* it's actually an illegal access (each
cart/bankswitch type now provides a hint to indicate this condition).
Still TODO is clean up the rework, properly integrate DiStella, and
fix labels and defines (which seem to be completely broken).
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1922 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-01-17 16:48:45 +00:00
|
|
|
return myState;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
|
|
|
|
void CartDebug::saveOldState()
|
|
|
|
|
{
|
|
|
|
|
myOldState.ram.clear();
|
|
|
|
|
for(uInt32 i = 0; i < myOldState.rport.size(); ++i)
|
2010-06-03 12:41:49 +00:00
|
|
|
myOldState.ram.push_back(peek(myOldState.rport[i]));
|
2013-04-20 22:23:42 +00:00
|
|
|
|
|
|
|
|
if(myDebugWidget)
|
2013-05-29 16:27:12 +00:00
|
|
|
{
|
|
|
|
|
myOldState.bank = myDebugWidget->bankState();
|
2013-04-20 22:23:42 +00:00
|
|
|
myDebugWidget->saveOldState();
|
2013-05-29 16:27:12 +00:00
|
|
|
}
|
OK, this is the first pass at a huge reorganization of the debugger
classes. First off, the distella code has been integrated into a
DiStella class. This code isn't yet tied to the debugger, but it does
at least compile and generate valid output.
The RamDebug class has been replaced by a CartDebug class, which
takes responsibility for the previous RamDebug stuff as well as
things related to Cart address space (read from write ports,
disassembly, etc).
Fixed E7 bankswitching when reading from the write port in the upper
256byte area.
Fixed 'read from write port functionality' in general for all carts
that supported it previously. Basically, if _rwport is enabled, the
address is checked to be an actual read (vs. one that's part of a
normal write cycle), *and* it's actually an illegal access (each
cart/bankswitch type now provides a hint to indicate this condition).
Still TODO is clean up the rework, properly integrate DiStella, and
fix labels and defines (which seem to be completely broken).
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1922 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-01-17 16:48:45 +00:00
|
|
|
}
|
|
|
|
|
|
2010-03-28 04:26:41 +00:00
|
|
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
|
|
|
|
void CartDebug::triggerReadFromWritePort(uInt16 addr)
|
|
|
|
|
{
|
|
|
|
|
myRWPortAddress = addr;
|
|
|
|
|
mySystem.setDirtyPage(addr);
|
|
|
|
|
}
|
|
|
|
|
|
OK, this is the first pass at a huge reorganization of the debugger
classes. First off, the distella code has been integrated into a
DiStella class. This code isn't yet tied to the debugger, but it does
at least compile and generate valid output.
The RamDebug class has been replaced by a CartDebug class, which
takes responsibility for the previous RamDebug stuff as well as
things related to Cart address space (read from write ports,
disassembly, etc).
Fixed E7 bankswitching when reading from the write port in the upper
256byte area.
Fixed 'read from write port functionality' in general for all carts
that supported it previously. Basically, if _rwport is enabled, the
address is checked to be an actual read (vs. one that's part of a
normal write cycle), *and* it's actually an illegal access (each
cart/bankswitch type now provides a hint to indicate this condition).
Still TODO is clean up the rework, properly integrate DiStella, and
fix labels and defines (which seem to be completely broken).
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1922 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-01-17 16:48:45 +00:00
|
|
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
|
|
|
|
int CartDebug::readFromWritePort()
|
|
|
|
|
{
|
2010-04-12 19:56:14 +00:00
|
|
|
uInt16 addr = myRWPortAddress;
|
OK, this is the first pass at a huge reorganization of the debugger
classes. First off, the distella code has been integrated into a
DiStella class. This code isn't yet tied to the debugger, but it does
at least compile and generate valid output.
The RamDebug class has been replaced by a CartDebug class, which
takes responsibility for the previous RamDebug stuff as well as
things related to Cart address space (read from write ports,
disassembly, etc).
Fixed E7 bankswitching when reading from the write port in the upper
256byte area.
Fixed 'read from write port functionality' in general for all carts
that supported it previously. Basically, if _rwport is enabled, the
address is checked to be an actual read (vs. one that's part of a
normal write cycle), *and* it's actually an illegal access (each
cart/bankswitch type now provides a hint to indicate this condition).
Still TODO is clean up the rework, properly integrate DiStella, and
fix labels and defines (which seem to be completely broken).
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1922 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-01-17 16:48:45 +00:00
|
|
|
myRWPortAddress = 0;
|
|
|
|
|
|
|
|
|
|
// A read from the write port occurs when the read is actually in the write
|
|
|
|
|
// port address space AND the last access was actually a read (the latter
|
|
|
|
|
// differentiates between reads that are normally part of a write cycle vs.
|
2010-02-28 17:12:16 +00:00
|
|
|
// ones that are illegal)
|
2010-04-12 19:56:14 +00:00
|
|
|
if(mySystem.m6502().lastReadAddress() &&
|
2010-04-14 22:35:46 +00:00
|
|
|
(mySystem.getPageAccessType(addr) & System::PA_WRITE) == System::PA_WRITE)
|
2010-04-12 19:56:14 +00:00
|
|
|
return addr;
|
|
|
|
|
else
|
|
|
|
|
return 0;
|
OK, this is the first pass at a huge reorganization of the debugger
classes. First off, the distella code has been integrated into a
DiStella class. This code isn't yet tied to the debugger, but it does
at least compile and generate valid output.
The RamDebug class has been replaced by a CartDebug class, which
takes responsibility for the previous RamDebug stuff as well as
things related to Cart address space (read from write ports,
disassembly, etc).
Fixed E7 bankswitching when reading from the write port in the upper
256byte area.
Fixed 'read from write port functionality' in general for all carts
that supported it previously. Basically, if _rwport is enabled, the
address is checked to be an actual read (vs. one that's part of a
normal write cycle), *and* it's actually an illegal access (each
cart/bankswitch type now provides a hint to indicate this condition).
Still TODO is clean up the rework, properly integrate DiStella, and
fix labels and defines (which seem to be completely broken).
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1922 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-01-17 16:48:45 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
|
|
|
|
string CartDebug::toString()
|
|
|
|
|
{
|
2010-11-11 16:46:41 +00:00
|
|
|
ostringstream buf;
|
OK, this is the first pass at a huge reorganization of the debugger
classes. First off, the distella code has been integrated into a
DiStella class. This code isn't yet tied to the debugger, but it does
at least compile and generate valid output.
The RamDebug class has been replaced by a CartDebug class, which
takes responsibility for the previous RamDebug stuff as well as
things related to Cart address space (read from write ports,
disassembly, etc).
Fixed E7 bankswitching when reading from the write port in the upper
256byte area.
Fixed 'read from write port functionality' in general for all carts
that supported it previously. Basically, if _rwport is enabled, the
address is checked to be an actual read (vs. one that's part of a
normal write cycle), *and* it's actually an illegal access (each
cart/bankswitch type now provides a hint to indicate this condition).
Still TODO is clean up the rework, properly integrate DiStella, and
fix labels and defines (which seem to be completely broken).
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1922 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-01-17 16:48:45 +00:00
|
|
|
uInt32 bytesPerLine;
|
|
|
|
|
|
2013-07-27 22:28:41 +00:00
|
|
|
switch(Base::format())
|
OK, this is the first pass at a huge reorganization of the debugger
classes. First off, the distella code has been integrated into a
DiStella class. This code isn't yet tied to the debugger, but it does
at least compile and generate valid output.
The RamDebug class has been replaced by a CartDebug class, which
takes responsibility for the previous RamDebug stuff as well as
things related to Cart address space (read from write ports,
disassembly, etc).
Fixed E7 bankswitching when reading from the write port in the upper
256byte area.
Fixed 'read from write port functionality' in general for all carts
that supported it previously. Basically, if _rwport is enabled, the
address is checked to be an actual read (vs. one that's part of a
normal write cycle), *and* it's actually an illegal access (each
cart/bankswitch type now provides a hint to indicate this condition).
Still TODO is clean up the rework, properly integrate DiStella, and
fix labels and defines (which seem to be completely broken).
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1922 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-01-17 16:48:45 +00:00
|
|
|
{
|
2013-07-27 22:28:41 +00:00
|
|
|
case Base::F_16:
|
|
|
|
|
case Base::F_10:
|
OK, this is the first pass at a huge reorganization of the debugger
classes. First off, the distella code has been integrated into a
DiStella class. This code isn't yet tied to the debugger, but it does
at least compile and generate valid output.
The RamDebug class has been replaced by a CartDebug class, which
takes responsibility for the previous RamDebug stuff as well as
things related to Cart address space (read from write ports,
disassembly, etc).
Fixed E7 bankswitching when reading from the write port in the upper
256byte area.
Fixed 'read from write port functionality' in general for all carts
that supported it previously. Basically, if _rwport is enabled, the
address is checked to be an actual read (vs. one that's part of a
normal write cycle), *and* it's actually an illegal access (each
cart/bankswitch type now provides a hint to indicate this condition).
Still TODO is clean up the rework, properly integrate DiStella, and
fix labels and defines (which seem to be completely broken).
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1922 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-01-17 16:48:45 +00:00
|
|
|
bytesPerLine = 0x10;
|
|
|
|
|
break;
|
|
|
|
|
|
2013-07-27 22:28:41 +00:00
|
|
|
case Base::F_2:
|
OK, this is the first pass at a huge reorganization of the debugger
classes. First off, the distella code has been integrated into a
DiStella class. This code isn't yet tied to the debugger, but it does
at least compile and generate valid output.
The RamDebug class has been replaced by a CartDebug class, which
takes responsibility for the previous RamDebug stuff as well as
things related to Cart address space (read from write ports,
disassembly, etc).
Fixed E7 bankswitching when reading from the write port in the upper
256byte area.
Fixed 'read from write port functionality' in general for all carts
that supported it previously. Basically, if _rwport is enabled, the
address is checked to be an actual read (vs. one that's part of a
normal write cycle), *and* it's actually an illegal access (each
cart/bankswitch type now provides a hint to indicate this condition).
Still TODO is clean up the rework, properly integrate DiStella, and
fix labels and defines (which seem to be completely broken).
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1922 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-01-17 16:48:45 +00:00
|
|
|
bytesPerLine = 0x04;
|
|
|
|
|
break;
|
|
|
|
|
|
2013-07-27 22:28:41 +00:00
|
|
|
case Base::F_DEFAULT:
|
OK, this is the first pass at a huge reorganization of the debugger
classes. First off, the distella code has been integrated into a
DiStella class. This code isn't yet tied to the debugger, but it does
at least compile and generate valid output.
The RamDebug class has been replaced by a CartDebug class, which
takes responsibility for the previous RamDebug stuff as well as
things related to Cart address space (read from write ports,
disassembly, etc).
Fixed E7 bankswitching when reading from the write port in the upper
256byte area.
Fixed 'read from write port functionality' in general for all carts
that supported it previously. Basically, if _rwport is enabled, the
address is checked to be an actual read (vs. one that's part of a
normal write cycle), *and* it's actually an illegal access (each
cart/bankswitch type now provides a hint to indicate this condition).
Still TODO is clean up the rework, properly integrate DiStella, and
fix labels and defines (which seem to be completely broken).
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1922 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-01-17 16:48:45 +00:00
|
|
|
default:
|
|
|
|
|
return DebuggerParser::red("invalid base, this is a BUG");
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
const CartState& state = (CartState&) getState();
|
|
|
|
|
const CartState& oldstate = (CartState&) getOldState();
|
|
|
|
|
|
|
|
|
|
uInt32 curraddr = 0, bytesSoFar = 0;
|
|
|
|
|
for(uInt32 i = 0; i < state.ram.size(); i += bytesPerLine, bytesSoFar += bytesPerLine)
|
|
|
|
|
{
|
|
|
|
|
// We detect different 'pages' of RAM when the addresses jump by
|
|
|
|
|
// more than the number of bytes on the previous line, or when 256
|
|
|
|
|
// bytes have been previously output
|
|
|
|
|
if(state.rport[i] - curraddr > bytesPerLine || bytesSoFar >= 256)
|
|
|
|
|
{
|
2011-07-13 14:13:49 +00:00
|
|
|
char port[37];
|
|
|
|
|
BSPF_snprintf(port, 36, "%04x: (rport = %04x, wport = %04x)\n",
|
OK, this is the first pass at a huge reorganization of the debugger
classes. First off, the distella code has been integrated into a
DiStella class. This code isn't yet tied to the debugger, but it does
at least compile and generate valid output.
The RamDebug class has been replaced by a CartDebug class, which
takes responsibility for the previous RamDebug stuff as well as
things related to Cart address space (read from write ports,
disassembly, etc).
Fixed E7 bankswitching when reading from the write port in the upper
256byte area.
Fixed 'read from write port functionality' in general for all carts
that supported it previously. Basically, if _rwport is enabled, the
address is checked to be an actual read (vs. one that's part of a
normal write cycle), *and* it's actually an illegal access (each
cart/bankswitch type now provides a hint to indicate this condition).
Still TODO is clean up the rework, properly integrate DiStella, and
fix labels and defines (which seem to be completely broken).
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1922 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-01-17 16:48:45 +00:00
|
|
|
state.rport[i], state.rport[i], state.wport[i]);
|
2010-11-11 16:46:41 +00:00
|
|
|
port[2] = port[3] = 'x';
|
|
|
|
|
buf << DebuggerParser::red(port);
|
OK, this is the first pass at a huge reorganization of the debugger
classes. First off, the distella code has been integrated into a
DiStella class. This code isn't yet tied to the debugger, but it does
at least compile and generate valid output.
The RamDebug class has been replaced by a CartDebug class, which
takes responsibility for the previous RamDebug stuff as well as
things related to Cart address space (read from write ports,
disassembly, etc).
Fixed E7 bankswitching when reading from the write port in the upper
256byte area.
Fixed 'read from write port functionality' in general for all carts
that supported it previously. Basically, if _rwport is enabled, the
address is checked to be an actual read (vs. one that's part of a
normal write cycle), *and* it's actually an illegal access (each
cart/bankswitch type now provides a hint to indicate this condition).
Still TODO is clean up the rework, properly integrate DiStella, and
fix labels and defines (which seem to be completely broken).
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1922 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-01-17 16:48:45 +00:00
|
|
|
bytesSoFar = 0;
|
|
|
|
|
}
|
|
|
|
|
curraddr = state.rport[i];
|
2013-07-27 22:28:41 +00:00
|
|
|
buf << Base::HEX2 << (curraddr & 0x00ff) << ": ";
|
OK, this is the first pass at a huge reorganization of the debugger
classes. First off, the distella code has been integrated into a
DiStella class. This code isn't yet tied to the debugger, but it does
at least compile and generate valid output.
The RamDebug class has been replaced by a CartDebug class, which
takes responsibility for the previous RamDebug stuff as well as
things related to Cart address space (read from write ports,
disassembly, etc).
Fixed E7 bankswitching when reading from the write port in the upper
256byte area.
Fixed 'read from write port functionality' in general for all carts
that supported it previously. Basically, if _rwport is enabled, the
address is checked to be an actual read (vs. one that's part of a
normal write cycle), *and* it's actually an illegal access (each
cart/bankswitch type now provides a hint to indicate this condition).
Still TODO is clean up the rework, properly integrate DiStella, and
fix labels and defines (which seem to be completely broken).
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1922 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-01-17 16:48:45 +00:00
|
|
|
|
|
|
|
|
for(uInt8 j = 0; j < bytesPerLine; ++j)
|
|
|
|
|
{
|
2010-11-11 16:46:41 +00:00
|
|
|
buf << myDebugger.invIfChanged(state.ram[i+j], oldstate.ram[i+j]) << " ";
|
OK, this is the first pass at a huge reorganization of the debugger
classes. First off, the distella code has been integrated into a
DiStella class. This code isn't yet tied to the debugger, but it does
at least compile and generate valid output.
The RamDebug class has been replaced by a CartDebug class, which
takes responsibility for the previous RamDebug stuff as well as
things related to Cart address space (read from write ports,
disassembly, etc).
Fixed E7 bankswitching when reading from the write port in the upper
256byte area.
Fixed 'read from write port functionality' in general for all carts
that supported it previously. Basically, if _rwport is enabled, the
address is checked to be an actual read (vs. one that's part of a
normal write cycle), *and* it's actually an illegal access (each
cart/bankswitch type now provides a hint to indicate this condition).
Still TODO is clean up the rework, properly integrate DiStella, and
fix labels and defines (which seem to be completely broken).
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1922 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-01-17 16:48:45 +00:00
|
|
|
|
2010-11-11 16:46:41 +00:00
|
|
|
if(j == 0x07) buf << " ";
|
OK, this is the first pass at a huge reorganization of the debugger
classes. First off, the distella code has been integrated into a
DiStella class. This code isn't yet tied to the debugger, but it does
at least compile and generate valid output.
The RamDebug class has been replaced by a CartDebug class, which
takes responsibility for the previous RamDebug stuff as well as
things related to Cart address space (read from write ports,
disassembly, etc).
Fixed E7 bankswitching when reading from the write port in the upper
256byte area.
Fixed 'read from write port functionality' in general for all carts
that supported it previously. Basically, if _rwport is enabled, the
address is checked to be an actual read (vs. one that's part of a
normal write cycle), *and* it's actually an illegal access (each
cart/bankswitch type now provides a hint to indicate this condition).
Still TODO is clean up the rework, properly integrate DiStella, and
fix labels and defines (which seem to be completely broken).
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1922 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-01-17 16:48:45 +00:00
|
|
|
}
|
2010-11-11 16:46:41 +00:00
|
|
|
buf << endl;
|
OK, this is the first pass at a huge reorganization of the debugger
classes. First off, the distella code has been integrated into a
DiStella class. This code isn't yet tied to the debugger, but it does
at least compile and generate valid output.
The RamDebug class has been replaced by a CartDebug class, which
takes responsibility for the previous RamDebug stuff as well as
things related to Cart address space (read from write ports,
disassembly, etc).
Fixed E7 bankswitching when reading from the write port in the upper
256byte area.
Fixed 'read from write port functionality' in general for all carts
that supported it previously. Basically, if _rwport is enabled, the
address is checked to be an actual read (vs. one that's part of a
normal write cycle), *and* it's actually an illegal access (each
cart/bankswitch type now provides a hint to indicate this condition).
Still TODO is clean up the rework, properly integrate DiStella, and
fix labels and defines (which seem to be completely broken).
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1922 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-01-17 16:48:45 +00:00
|
|
|
}
|
|
|
|
|
|
2010-11-11 16:46:41 +00:00
|
|
|
return buf.str();
|
OK, this is the first pass at a huge reorganization of the debugger
classes. First off, the distella code has been integrated into a
DiStella class. This code isn't yet tied to the debugger, but it does
at least compile and generate valid output.
The RamDebug class has been replaced by a CartDebug class, which
takes responsibility for the previous RamDebug stuff as well as
things related to Cart address space (read from write ports,
disassembly, etc).
Fixed E7 bankswitching when reading from the write port in the upper
256byte area.
Fixed 'read from write port functionality' in general for all carts
that supported it previously. Basically, if _rwport is enabled, the
address is checked to be an actual read (vs. one that's part of a
normal write cycle), *and* it's actually an illegal access (each
cart/bankswitch type now provides a hint to indicate this condition).
Still TODO is clean up the rework, properly integrate DiStella, and
fix labels and defines (which seem to be completely broken).
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1922 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-01-17 16:48:45 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
2013-06-17 15:57:41 +00:00
|
|
|
bool CartDebug::disassemble(bool force)
|
OK, this is the first pass at a huge reorganization of the debugger
classes. First off, the distella code has been integrated into a
DiStella class. This code isn't yet tied to the debugger, but it does
at least compile and generate valid output.
The RamDebug class has been replaced by a CartDebug class, which
takes responsibility for the previous RamDebug stuff as well as
things related to Cart address space (read from write ports,
disassembly, etc).
Fixed E7 bankswitching when reading from the write port in the upper
256byte area.
Fixed 'read from write port functionality' in general for all carts
that supported it previously. Basically, if _rwport is enabled, the
address is checked to be an actual read (vs. one that's part of a
normal write cycle), *and* it's actually an illegal access (each
cart/bankswitch type now provides a hint to indicate this condition).
Still TODO is clean up the rework, properly integrate DiStella, and
fix labels and defines (which seem to be completely broken).
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1922 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-01-17 16:48:45 +00:00
|
|
|
{
|
2010-02-07 21:23:26 +00:00
|
|
|
// Test current disassembly; don't re-disassemble if it hasn't changed
|
OK, I've finally gotten back to Stella development and fixing the
disassembler. Hopefully this will lead to a new release very soon.
Added 'autocode' commandline argument and associated UI item (in the
RomWidget debugger area), which controls how Distella will use the
'automatic code determination' option. If set to 0/never, this is
completely disabled. If set to 1/always, it is always enabled.
The default is 2/automatic, whereby it is first turned on, and then
turned off if the disassembly doesn't contain the current PC address.
RomListWidget has now been completely reworked, so that it informs
RomWidget of its intent to change breakpoints and patch ROM. If
either of these fail, the action won't be performed, and more
importantly, it won't appear onscreen as if the action has succeeded.
This fixes an old bug whereby patching could fail, yet the onscreen
ROM data was actually changed. Related to this, the list has been
made as efficient as possible, and its contents are never un-necessarily
copied. Also, lines in the disassembly that cannot be modified no
longer show an edit area.
Due to the way the new disassembly works, you can no longer switch between
banks in the RomWidget (Distella would probably fail to disassemble in
such as case).
EditTextWidget can now indicate its contents have changed when adding
text to it.
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1966 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-03-18 16:36:12 +00:00
|
|
|
// Also check if the current PC is in the current list
|
2010-08-19 21:48:28 +00:00
|
|
|
bool bankChanged = myConsole.cartridge().bankChanged();
|
OK, I've finally gotten back to Stella development and fixing the
disassembler. Hopefully this will lead to a new release very soon.
Added 'autocode' commandline argument and associated UI item (in the
RomWidget debugger area), which controls how Distella will use the
'automatic code determination' option. If set to 0/never, this is
completely disabled. If set to 1/always, it is always enabled.
The default is 2/automatic, whereby it is first turned on, and then
turned off if the disassembly doesn't contain the current PC address.
RomListWidget has now been completely reworked, so that it informs
RomWidget of its intent to change breakpoints and patch ROM. If
either of these fail, the action won't be performed, and more
importantly, it won't appear onscreen as if the action has succeeded.
This fixes an old bug whereby patching could fail, yet the onscreen
ROM data was actually changed. Related to this, the list has been
made as efficient as possible, and its contents are never un-necessarily
copied. Also, lines in the disassembly that cannot be modified no
longer show an edit area.
Due to the way the new disassembly works, you can no longer switch between
banks in the RomWidget (Distella would probably fail to disassemble in
such as case).
EditTextWidget can now indicate its contents have changed when adding
text to it.
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1966 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-03-18 16:36:12 +00:00
|
|
|
uInt16 PC = myDebugger.cpuDebug().pc();
|
2010-03-26 00:03:35 +00:00
|
|
|
int pcline = addressToLine(PC);
|
2010-08-19 21:48:28 +00:00
|
|
|
bool pcfound = (pcline != -1) && ((uInt32)pcline < myDisassembly.list.size()) &&
|
|
|
|
|
(myDisassembly.list[pcline].disasm[0] != '.');
|
|
|
|
|
bool pagedirty = (PC & 0x1000) ? mySystem.isPageDirty(0x1000, 0x1FFF) :
|
|
|
|
|
mySystem.isPageDirty(0x80, 0xFF);
|
2010-04-14 15:41:42 +00:00
|
|
|
|
2010-08-19 21:48:28 +00:00
|
|
|
bool changed = (force || bankChanged || !pcfound || pagedirty);
|
2010-02-07 21:23:26 +00:00
|
|
|
if(changed)
|
|
|
|
|
{
|
2010-08-19 21:48:28 +00:00
|
|
|
// Are we disassembling from ROM or ZP RAM?
|
2010-08-30 12:04:56 +00:00
|
|
|
BankInfo& info = (PC & 0x1000) ? myBankInfo[getBank()] :
|
|
|
|
|
myBankInfo[myBankInfo.size()-1];
|
2010-08-16 16:41:24 +00:00
|
|
|
|
2010-08-19 21:48:28 +00:00
|
|
|
// If the offset has changed, all old addresses must be 'converted'
|
2010-08-16 16:41:24 +00:00
|
|
|
// For example, if the list contains any $fxxx and the address space is now
|
|
|
|
|
// $bxxx, it must be changed
|
|
|
|
|
uInt16 offset = (PC - (PC % 0x1000));
|
2010-08-30 12:04:56 +00:00
|
|
|
AddressList& addresses = info.addressList;
|
2014-11-02 23:40:20 +00:00
|
|
|
for(auto& i: addresses)
|
|
|
|
|
i = (i & 0xFFF) + offset;
|
2010-08-19 21:48:28 +00:00
|
|
|
|
|
|
|
|
// Only add addresses when absolutely necessary, to cut down on the
|
|
|
|
|
// work that Distella has to do
|
|
|
|
|
// Distella expects the addresses to be unique and in sorted order
|
|
|
|
|
if(bankChanged || !pcfound)
|
2010-04-14 15:41:42 +00:00
|
|
|
{
|
2014-11-02 23:40:20 +00:00
|
|
|
AddressList::const_iterator i;
|
2010-08-19 21:48:28 +00:00
|
|
|
for(i = addresses.begin(); i != addresses.end(); ++i)
|
|
|
|
|
{
|
|
|
|
|
if(PC < *i)
|
|
|
|
|
{
|
|
|
|
|
addresses.insert(i, PC);
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
else if(PC == *i) // already present
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
// Otherwise, add the item at the end
|
|
|
|
|
if(i == addresses.end())
|
|
|
|
|
addresses.push_back(PC);
|
2010-04-14 15:41:42 +00:00
|
|
|
}
|
2010-03-05 22:02:12 +00:00
|
|
|
|
2013-06-17 15:57:41 +00:00
|
|
|
// Always attempt to resolve code sections unless it's been
|
|
|
|
|
// specifically disabled
|
|
|
|
|
bool found = fillDisassemblyList(info, PC);
|
|
|
|
|
if(!found && DiStella::settings.resolve_code)
|
OK, I've finally gotten back to Stella development and fixing the
disassembler. Hopefully this will lead to a new release very soon.
Added 'autocode' commandline argument and associated UI item (in the
RomWidget debugger area), which controls how Distella will use the
'automatic code determination' option. If set to 0/never, this is
completely disabled. If set to 1/always, it is always enabled.
The default is 2/automatic, whereby it is first turned on, and then
turned off if the disassembly doesn't contain the current PC address.
RomListWidget has now been completely reworked, so that it informs
RomWidget of its intent to change breakpoints and patch ROM. If
either of these fail, the action won't be performed, and more
importantly, it won't appear onscreen as if the action has succeeded.
This fixes an old bug whereby patching could fail, yet the onscreen
ROM data was actually changed. Related to this, the list has been
made as efficient as possible, and its contents are never un-necessarily
copied. Also, lines in the disassembly that cannot be modified no
longer show an edit area.
Due to the way the new disassembly works, you can no longer switch between
banks in the RomWidget (Distella would probably fail to disassemble in
such as case).
EditTextWidget can now indicate its contents have changed when adding
text to it.
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1966 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-03-18 16:36:12 +00:00
|
|
|
{
|
2013-06-17 15:57:41 +00:00
|
|
|
// Temporarily turn off code resolution
|
|
|
|
|
DiStella::settings.resolve_code = false;
|
|
|
|
|
fillDisassemblyList(info, PC);
|
|
|
|
|
DiStella::settings.resolve_code = true;
|
OK, I've finally gotten back to Stella development and fixing the
disassembler. Hopefully this will lead to a new release very soon.
Added 'autocode' commandline argument and associated UI item (in the
RomWidget debugger area), which controls how Distella will use the
'automatic code determination' option. If set to 0/never, this is
completely disabled. If set to 1/always, it is always enabled.
The default is 2/automatic, whereby it is first turned on, and then
turned off if the disassembly doesn't contain the current PC address.
RomListWidget has now been completely reworked, so that it informs
RomWidget of its intent to change breakpoints and patch ROM. If
either of these fail, the action won't be performed, and more
importantly, it won't appear onscreen as if the action has succeeded.
This fixes an old bug whereby patching could fail, yet the onscreen
ROM data was actually changed. Related to this, the list has been
made as efficient as possible, and its contents are never un-necessarily
copied. Also, lines in the disassembly that cannot be modified no
longer show an edit area.
Due to the way the new disassembly works, you can no longer switch between
banks in the RomWidget (Distella would probably fail to disassemble in
such as case).
EditTextWidget can now indicate its contents have changed when adding
text to it.
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1966 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-03-18 16:36:12 +00:00
|
|
|
}
|
|
|
|
|
}
|
2010-03-05 22:02:12 +00:00
|
|
|
|
OK, I've finally gotten back to Stella development and fixing the
disassembler. Hopefully this will lead to a new release very soon.
Added 'autocode' commandline argument and associated UI item (in the
RomWidget debugger area), which controls how Distella will use the
'automatic code determination' option. If set to 0/never, this is
completely disabled. If set to 1/always, it is always enabled.
The default is 2/automatic, whereby it is first turned on, and then
turned off if the disassembly doesn't contain the current PC address.
RomListWidget has now been completely reworked, so that it informs
RomWidget of its intent to change breakpoints and patch ROM. If
either of these fail, the action won't be performed, and more
importantly, it won't appear onscreen as if the action has succeeded.
This fixes an old bug whereby patching could fail, yet the onscreen
ROM data was actually changed. Related to this, the list has been
made as efficient as possible, and its contents are never un-necessarily
copied. Also, lines in the disassembly that cannot be modified no
longer show an edit area.
Due to the way the new disassembly works, you can no longer switch between
banks in the RomWidget (Distella would probably fail to disassemble in
such as case).
EditTextWidget can now indicate its contents have changed when adding
text to it.
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1966 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-03-18 16:36:12 +00:00
|
|
|
return changed;
|
|
|
|
|
}
|
2010-03-05 22:02:12 +00:00
|
|
|
|
OK, I've finally gotten back to Stella development and fixing the
disassembler. Hopefully this will lead to a new release very soon.
Added 'autocode' commandline argument and associated UI item (in the
RomWidget debugger area), which controls how Distella will use the
'automatic code determination' option. If set to 0/never, this is
completely disabled. If set to 1/always, it is always enabled.
The default is 2/automatic, whereby it is first turned on, and then
turned off if the disassembly doesn't contain the current PC address.
RomListWidget has now been completely reworked, so that it informs
RomWidget of its intent to change breakpoints and patch ROM. If
either of these fail, the action won't be performed, and more
importantly, it won't appear onscreen as if the action has succeeded.
This fixes an old bug whereby patching could fail, yet the onscreen
ROM data was actually changed. Related to this, the list has been
made as efficient as possible, and its contents are never un-necessarily
copied. Also, lines in the disassembly that cannot be modified no
longer show an edit area.
Due to the way the new disassembly works, you can no longer switch between
banks in the RomWidget (Distella would probably fail to disassemble in
such as case).
EditTextWidget can now indicate its contents have changed when adding
text to it.
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1966 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-03-18 16:36:12 +00:00
|
|
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
2013-06-17 15:57:41 +00:00
|
|
|
bool CartDebug::fillDisassemblyList(BankInfo& info, uInt16 search)
|
OK, I've finally gotten back to Stella development and fixing the
disassembler. Hopefully this will lead to a new release very soon.
Added 'autocode' commandline argument and associated UI item (in the
RomWidget debugger area), which controls how Distella will use the
'automatic code determination' option. If set to 0/never, this is
completely disabled. If set to 1/always, it is always enabled.
The default is 2/automatic, whereby it is first turned on, and then
turned off if the disassembly doesn't contain the current PC address.
RomListWidget has now been completely reworked, so that it informs
RomWidget of its intent to change breakpoints and patch ROM. If
either of these fail, the action won't be performed, and more
importantly, it won't appear onscreen as if the action has succeeded.
This fixes an old bug whereby patching could fail, yet the onscreen
ROM data was actually changed. Related to this, the list has been
made as efficient as possible, and its contents are never un-necessarily
copied. Also, lines in the disassembly that cannot be modified no
longer show an edit area.
Due to the way the new disassembly works, you can no longer switch between
banks in the RomWidget (Distella would probably fail to disassemble in
such as case).
EditTextWidget can now indicate its contents have changed when adding
text to it.
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1966 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-03-18 16:36:12 +00:00
|
|
|
{
|
2014-11-07 23:28:40 +00:00
|
|
|
myDisassembly.list.clear();
|
2013-05-19 20:55:25 +00:00
|
|
|
myDisassembly.fieldwidth = 14 + myLabelLength;
|
2013-03-04 23:35:26 +00:00
|
|
|
DiStella distella(*this, myDisassembly.list, info, DiStella::settings,
|
2013-06-17 15:57:41 +00:00
|
|
|
myDisLabels, myDisDirectives, myReserved);
|
OK, this is the first pass at a huge reorganization of the debugger
classes. First off, the distella code has been integrated into a
DiStella class. This code isn't yet tied to the debugger, but it does
at least compile and generate valid output.
The RamDebug class has been replaced by a CartDebug class, which
takes responsibility for the previous RamDebug stuff as well as
things related to Cart address space (read from write ports,
disassembly, etc).
Fixed E7 bankswitching when reading from the write port in the upper
256byte area.
Fixed 'read from write port functionality' in general for all carts
that supported it previously. Basically, if _rwport is enabled, the
address is checked to be an actual read (vs. one that's part of a
normal write cycle), *and* it's actually an illegal access (each
cart/bankswitch type now provides a hint to indicate this condition).
Still TODO is clean up the rework, properly integrate DiStella, and
fix labels and defines (which seem to be completely broken).
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1922 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-01-17 16:48:45 +00:00
|
|
|
|
OK, I've finally gotten back to Stella development and fixing the
disassembler. Hopefully this will lead to a new release very soon.
Added 'autocode' commandline argument and associated UI item (in the
RomWidget debugger area), which controls how Distella will use the
'automatic code determination' option. If set to 0/never, this is
completely disabled. If set to 1/always, it is always enabled.
The default is 2/automatic, whereby it is first turned on, and then
turned off if the disassembly doesn't contain the current PC address.
RomListWidget has now been completely reworked, so that it informs
RomWidget of its intent to change breakpoints and patch ROM. If
either of these fail, the action won't be performed, and more
importantly, it won't appear onscreen as if the action has succeeded.
This fixes an old bug whereby patching could fail, yet the onscreen
ROM data was actually changed. Related to this, the list has been
made as efficient as possible, and its contents are never un-necessarily
copied. Also, lines in the disassembly that cannot be modified no
longer show an edit area.
Due to the way the new disassembly works, you can no longer switch between
banks in the RomWidget (Distella would probably fail to disassemble in
such as case).
EditTextWidget can now indicate its contents have changed when adding
text to it.
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1966 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-03-18 16:36:12 +00:00
|
|
|
// Parts of the disassembly will be accessed later in different ways
|
|
|
|
|
// We place those parts in separate maps, to speed up access
|
2013-03-04 23:35:26 +00:00
|
|
|
bool found = false;
|
OK, I've finally gotten back to Stella development and fixing the
disassembler. Hopefully this will lead to a new release very soon.
Added 'autocode' commandline argument and associated UI item (in the
RomWidget debugger area), which controls how Distella will use the
'automatic code determination' option. If set to 0/never, this is
completely disabled. If set to 1/always, it is always enabled.
The default is 2/automatic, whereby it is first turned on, and then
turned off if the disassembly doesn't contain the current PC address.
RomListWidget has now been completely reworked, so that it informs
RomWidget of its intent to change breakpoints and patch ROM. If
either of these fail, the action won't be performed, and more
importantly, it won't appear onscreen as if the action has succeeded.
This fixes an old bug whereby patching could fail, yet the onscreen
ROM data was actually changed. Related to this, the list has been
made as efficient as possible, and its contents are never un-necessarily
copied. Also, lines in the disassembly that cannot be modified no
longer show an edit area.
Due to the way the new disassembly works, you can no longer switch between
banks in the RomWidget (Distella would probably fail to disassemble in
such as case).
EditTextWidget can now indicate its contents have changed when adding
text to it.
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1966 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-03-18 16:36:12 +00:00
|
|
|
myAddrToLineList.clear();
|
2013-07-17 23:00:55 +00:00
|
|
|
myAddrToLineIsROM = info.offset & 0x1000;
|
2010-06-05 01:17:03 +00:00
|
|
|
for(uInt32 i = 0; i < myDisassembly.list.size(); ++i)
|
OK, I've finally gotten back to Stella development and fixing the
disassembler. Hopefully this will lead to a new release very soon.
Added 'autocode' commandline argument and associated UI item (in the
RomWidget debugger area), which controls how Distella will use the
'automatic code determination' option. If set to 0/never, this is
completely disabled. If set to 1/always, it is always enabled.
The default is 2/automatic, whereby it is first turned on, and then
turned off if the disassembly doesn't contain the current PC address.
RomListWidget has now been completely reworked, so that it informs
RomWidget of its intent to change breakpoints and patch ROM. If
either of these fail, the action won't be performed, and more
importantly, it won't appear onscreen as if the action has succeeded.
This fixes an old bug whereby patching could fail, yet the onscreen
ROM data was actually changed. Related to this, the list has been
made as efficient as possible, and its contents are never un-necessarily
copied. Also, lines in the disassembly that cannot be modified no
longer show an edit area.
Due to the way the new disassembly works, you can no longer switch between
banks in the RomWidget (Distella would probably fail to disassemble in
such as case).
EditTextWidget can now indicate its contents have changed when adding
text to it.
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1966 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-03-18 16:36:12 +00:00
|
|
|
{
|
2010-06-05 01:17:03 +00:00
|
|
|
const DisassemblyTag& tag = myDisassembly.list[i];
|
2013-07-17 23:00:55 +00:00
|
|
|
const uInt16 address = tag.address & 0xFFF;
|
OK, I've finally gotten back to Stella development and fixing the
disassembler. Hopefully this will lead to a new release very soon.
Added 'autocode' commandline argument and associated UI item (in the
RomWidget debugger area), which controls how Distella will use the
'automatic code determination' option. If set to 0/never, this is
completely disabled. If set to 1/always, it is always enabled.
The default is 2/automatic, whereby it is first turned on, and then
turned off if the disassembly doesn't contain the current PC address.
RomListWidget has now been completely reworked, so that it informs
RomWidget of its intent to change breakpoints and patch ROM. If
either of these fail, the action won't be performed, and more
importantly, it won't appear onscreen as if the action has succeeded.
This fixes an old bug whereby patching could fail, yet the onscreen
ROM data was actually changed. Related to this, the list has been
made as efficient as possible, and its contents are never un-necessarily
copied. Also, lines in the disassembly that cannot be modified no
longer show an edit area.
Due to the way the new disassembly works, you can no longer switch between
banks in the RomWidget (Distella would probably fail to disassemble in
such as case).
EditTextWidget can now indicate its contents have changed when adding
text to it.
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1966 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-03-18 16:36:12 +00:00
|
|
|
|
2014-07-31 15:54:14 +00:00
|
|
|
// Exclude 'ROW'; they don't have a valid address
|
|
|
|
|
if(tag.type != CartDebug::ROW)
|
OK, I've finally gotten back to Stella development and fixing the
disassembler. Hopefully this will lead to a new release very soon.
Added 'autocode' commandline argument and associated UI item (in the
RomWidget debugger area), which controls how Distella will use the
'automatic code determination' option. If set to 0/never, this is
completely disabled. If set to 1/always, it is always enabled.
The default is 2/automatic, whereby it is first turned on, and then
turned off if the disassembly doesn't contain the current PC address.
RomListWidget has now been completely reworked, so that it informs
RomWidget of its intent to change breakpoints and patch ROM. If
either of these fail, the action won't be performed, and more
importantly, it won't appear onscreen as if the action has succeeded.
This fixes an old bug whereby patching could fail, yet the onscreen
ROM data was actually changed. Related to this, the list has been
made as efficient as possible, and its contents are never un-necessarily
copied. Also, lines in the disassembly that cannot be modified no
longer show an edit area.
Due to the way the new disassembly works, you can no longer switch between
banks in the RomWidget (Distella would probably fail to disassemble in
such as case).
EditTextWidget can now indicate its contents have changed when adding
text to it.
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1966 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-03-18 16:36:12 +00:00
|
|
|
{
|
2010-02-07 21:23:26 +00:00
|
|
|
// Create a mapping from addresses to line numbers
|
2013-07-17 23:00:55 +00:00
|
|
|
myAddrToLineList.insert(make_pair(address, i));
|
OK, this is the first pass at a huge reorganization of the debugger
classes. First off, the distella code has been integrated into a
DiStella class. This code isn't yet tied to the debugger, but it does
at least compile and generate valid output.
The RamDebug class has been replaced by a CartDebug class, which
takes responsibility for the previous RamDebug stuff as well as
things related to Cart address space (read from write ports,
disassembly, etc).
Fixed E7 bankswitching when reading from the write port in the upper
256byte area.
Fixed 'read from write port functionality' in general for all carts
that supported it previously. Basically, if _rwport is enabled, the
address is checked to be an actual read (vs. one that's part of a
normal write cycle), *and* it's actually an illegal access (each
cart/bankswitch type now provides a hint to indicate this condition).
Still TODO is clean up the rework, properly integrate DiStella, and
fix labels and defines (which seem to be completely broken).
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1922 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-01-17 16:48:45 +00:00
|
|
|
|
OK, I've finally gotten back to Stella development and fixing the
disassembler. Hopefully this will lead to a new release very soon.
Added 'autocode' commandline argument and associated UI item (in the
RomWidget debugger area), which controls how Distella will use the
'automatic code determination' option. If set to 0/never, this is
completely disabled. If set to 1/always, it is always enabled.
The default is 2/automatic, whereby it is first turned on, and then
turned off if the disassembly doesn't contain the current PC address.
RomListWidget has now been completely reworked, so that it informs
RomWidget of its intent to change breakpoints and patch ROM. If
either of these fail, the action won't be performed, and more
importantly, it won't appear onscreen as if the action has succeeded.
This fixes an old bug whereby patching could fail, yet the onscreen
ROM data was actually changed. Related to this, the list has been
made as efficient as possible, and its contents are never un-necessarily
copied. Also, lines in the disassembly that cannot be modified no
longer show an edit area.
Due to the way the new disassembly works, you can no longer switch between
banks in the RomWidget (Distella would probably fail to disassemble in
such as case).
EditTextWidget can now indicate its contents have changed when adding
text to it.
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1966 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-03-18 16:36:12 +00:00
|
|
|
// Did we find the search value?
|
2013-07-17 23:00:55 +00:00
|
|
|
if(address == (search & 0xFFF))
|
OK, I've finally gotten back to Stella development and fixing the
disassembler. Hopefully this will lead to a new release very soon.
Added 'autocode' commandline argument and associated UI item (in the
RomWidget debugger area), which controls how Distella will use the
'automatic code determination' option. If set to 0/never, this is
completely disabled. If set to 1/always, it is always enabled.
The default is 2/automatic, whereby it is first turned on, and then
turned off if the disassembly doesn't contain the current PC address.
RomListWidget has now been completely reworked, so that it informs
RomWidget of its intent to change breakpoints and patch ROM. If
either of these fail, the action won't be performed, and more
importantly, it won't appear onscreen as if the action has succeeded.
This fixes an old bug whereby patching could fail, yet the onscreen
ROM data was actually changed. Related to this, the list has been
made as efficient as possible, and its contents are never un-necessarily
copied. Also, lines in the disassembly that cannot be modified no
longer show an edit area.
Due to the way the new disassembly works, you can no longer switch between
banks in the RomWidget (Distella would probably fail to disassemble in
such as case).
EditTextWidget can now indicate its contents have changed when adding
text to it.
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1966 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-03-18 16:36:12 +00:00
|
|
|
found = true;
|
OK, this is the first pass at a huge reorganization of the debugger
classes. First off, the distella code has been integrated into a
DiStella class. This code isn't yet tied to the debugger, but it does
at least compile and generate valid output.
The RamDebug class has been replaced by a CartDebug class, which
takes responsibility for the previous RamDebug stuff as well as
things related to Cart address space (read from write ports,
disassembly, etc).
Fixed E7 bankswitching when reading from the write port in the upper
256byte area.
Fixed 'read from write port functionality' in general for all carts
that supported it previously. Basically, if _rwport is enabled, the
address is checked to be an actual read (vs. one that's part of a
normal write cycle), *and* it's actually an illegal access (each
cart/bankswitch type now provides a hint to indicate this condition).
Still TODO is clean up the rework, properly integrate DiStella, and
fix labels and defines (which seem to be completely broken).
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1922 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-01-17 16:48:45 +00:00
|
|
|
}
|
OK, I've finally gotten back to Stella development and fixing the
disassembler. Hopefully this will lead to a new release very soon.
Added 'autocode' commandline argument and associated UI item (in the
RomWidget debugger area), which controls how Distella will use the
'automatic code determination' option. If set to 0/never, this is
completely disabled. If set to 1/always, it is always enabled.
The default is 2/automatic, whereby it is first turned on, and then
turned off if the disassembly doesn't contain the current PC address.
RomListWidget has now been completely reworked, so that it informs
RomWidget of its intent to change breakpoints and patch ROM. If
either of these fail, the action won't be performed, and more
importantly, it won't appear onscreen as if the action has succeeded.
This fixes an old bug whereby patching could fail, yet the onscreen
ROM data was actually changed. Related to this, the list has been
made as efficient as possible, and its contents are never un-necessarily
copied. Also, lines in the disassembly that cannot be modified no
longer show an edit area.
Due to the way the new disassembly works, you can no longer switch between
banks in the RomWidget (Distella would probably fail to disassemble in
such as case).
EditTextWidget can now indicate its contents have changed when adding
text to it.
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1966 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-03-18 16:36:12 +00:00
|
|
|
}
|
|
|
|
|
return found;
|
OK, this is the first pass at a huge reorganization of the debugger
classes. First off, the distella code has been integrated into a
DiStella class. This code isn't yet tied to the debugger, but it does
at least compile and generate valid output.
The RamDebug class has been replaced by a CartDebug class, which
takes responsibility for the previous RamDebug stuff as well as
things related to Cart address space (read from write ports,
disassembly, etc).
Fixed E7 bankswitching when reading from the write port in the upper
256byte area.
Fixed 'read from write port functionality' in general for all carts
that supported it previously. Basically, if _rwport is enabled, the
address is checked to be an actual read (vs. one that's part of a
normal write cycle), *and* it's actually an illegal access (each
cart/bankswitch type now provides a hint to indicate this condition).
Still TODO is clean up the rework, properly integrate DiStella, and
fix labels and defines (which seem to be completely broken).
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1922 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-01-17 16:48:45 +00:00
|
|
|
}
|
|
|
|
|
|
2010-02-01 20:00:50 +00:00
|
|
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
2010-02-07 21:23:26 +00:00
|
|
|
int CartDebug::addressToLine(uInt16 address) const
|
2010-02-01 20:00:50 +00:00
|
|
|
{
|
2013-07-17 23:00:55 +00:00
|
|
|
// Switching between ZP RAM address space and Cart/ROM address space
|
|
|
|
|
// means the line isn't present
|
|
|
|
|
if(!myAddrToLineIsROM != !(address & 0x1000))
|
|
|
|
|
return -1;
|
|
|
|
|
|
2014-11-02 23:40:20 +00:00
|
|
|
const auto& iter = myAddrToLineList.find(address & 0xFFF);
|
OK, I've finally gotten back to Stella development and fixing the
disassembler. Hopefully this will lead to a new release very soon.
Added 'autocode' commandline argument and associated UI item (in the
RomWidget debugger area), which controls how Distella will use the
'automatic code determination' option. If set to 0/never, this is
completely disabled. If set to 1/always, it is always enabled.
The default is 2/automatic, whereby it is first turned on, and then
turned off if the disassembly doesn't contain the current PC address.
RomListWidget has now been completely reworked, so that it informs
RomWidget of its intent to change breakpoints and patch ROM. If
either of these fail, the action won't be performed, and more
importantly, it won't appear onscreen as if the action has succeeded.
This fixes an old bug whereby patching could fail, yet the onscreen
ROM data was actually changed. Related to this, the list has been
made as efficient as possible, and its contents are never un-necessarily
copied. Also, lines in the disassembly that cannot be modified no
longer show an edit area.
Due to the way the new disassembly works, you can no longer switch between
banks in the RomWidget (Distella would probably fail to disassemble in
such as case).
EditTextWidget can now indicate its contents have changed when adding
text to it.
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1966 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-03-18 16:36:12 +00:00
|
|
|
return iter != myAddrToLineList.end() ? iter->second : -1;
|
2010-02-01 20:00:50 +00:00
|
|
|
}
|
|
|
|
|
|
OK, this is the first pass at a huge reorganization of the debugger
classes. First off, the distella code has been integrated into a
DiStella class. This code isn't yet tied to the debugger, but it does
at least compile and generate valid output.
The RamDebug class has been replaced by a CartDebug class, which
takes responsibility for the previous RamDebug stuff as well as
things related to Cart address space (read from write ports,
disassembly, etc).
Fixed E7 bankswitching when reading from the write port in the upper
256byte area.
Fixed 'read from write port functionality' in general for all carts
that supported it previously. Basically, if _rwport is enabled, the
address is checked to be an actual read (vs. one that's part of a
normal write cycle), *and* it's actually an illegal access (each
cart/bankswitch type now provides a hint to indicate this condition).
Still TODO is clean up the rework, properly integrate DiStella, and
fix labels and defines (which seem to be completely broken).
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1922 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-01-17 16:48:45 +00:00
|
|
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
2010-02-07 21:23:26 +00:00
|
|
|
string CartDebug::disassemble(uInt16 start, uInt16 lines) const
|
OK, this is the first pass at a huge reorganization of the debugger
classes. First off, the distella code has been integrated into a
DiStella class. This code isn't yet tied to the debugger, but it does
at least compile and generate valid output.
The RamDebug class has been replaced by a CartDebug class, which
takes responsibility for the previous RamDebug stuff as well as
things related to Cart address space (read from write ports,
disassembly, etc).
Fixed E7 bankswitching when reading from the write port in the upper
256byte area.
Fixed 'read from write port functionality' in general for all carts
that supported it previously. Basically, if _rwport is enabled, the
address is checked to be an actual read (vs. one that's part of a
normal write cycle), *and* it's actually an illegal access (each
cart/bankswitch type now provides a hint to indicate this condition).
Still TODO is clean up the rework, properly integrate DiStella, and
fix labels and defines (which seem to be completely broken).
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1922 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-01-17 16:48:45 +00:00
|
|
|
{
|
2010-02-07 21:23:26 +00:00
|
|
|
// Fill the string with disassembled data
|
|
|
|
|
start &= 0xFFF;
|
|
|
|
|
ostringstream buffer;
|
2010-06-05 01:17:03 +00:00
|
|
|
|
|
|
|
|
// First find the lines in the range, and determine the longest string
|
2013-05-17 01:05:50 +00:00
|
|
|
uInt32 list_size = myDisassembly.list.size();
|
2010-08-16 16:41:24 +00:00
|
|
|
uInt32 begin = list_size, end = 0, length = 0;
|
|
|
|
|
for(end = 0; end < list_size && lines > 0; ++end)
|
OK, this is the first pass at a huge reorganization of the debugger
classes. First off, the distella code has been integrated into a
DiStella class. This code isn't yet tied to the debugger, but it does
at least compile and generate valid output.
The RamDebug class has been replaced by a CartDebug class, which
takes responsibility for the previous RamDebug stuff as well as
things related to Cart address space (read from write ports,
disassembly, etc).
Fixed E7 bankswitching when reading from the write port in the upper
256byte area.
Fixed 'read from write port functionality' in general for all carts
that supported it previously. Basically, if _rwport is enabled, the
address is checked to be an actual read (vs. one that's part of a
normal write cycle), *and* it's actually an illegal access (each
cart/bankswitch type now provides a hint to indicate this condition).
Still TODO is clean up the rework, properly integrate DiStella, and
fix labels and defines (which seem to be completely broken).
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1922 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-01-17 16:48:45 +00:00
|
|
|
{
|
2013-05-17 01:05:50 +00:00
|
|
|
const CartDebug::DisassemblyTag& tag = myDisassembly.list[end];
|
2010-02-07 21:23:26 +00:00
|
|
|
if((tag.address & 0xfff) >= start)
|
|
|
|
|
{
|
2010-08-16 16:41:24 +00:00
|
|
|
if(begin == list_size) begin = end;
|
2010-11-11 16:46:41 +00:00
|
|
|
if(tag.type != CartDebug::ROW)
|
|
|
|
|
length = BSPF_max(length, (uInt32)tag.disasm.length());
|
2010-06-05 01:17:03 +00:00
|
|
|
|
2010-04-06 15:15:44 +00:00
|
|
|
--lines;
|
2010-02-07 21:23:26 +00:00
|
|
|
}
|
OK, this is the first pass at a huge reorganization of the debugger
classes. First off, the distella code has been integrated into a
DiStella class. This code isn't yet tied to the debugger, but it does
at least compile and generate valid output.
The RamDebug class has been replaced by a CartDebug class, which
takes responsibility for the previous RamDebug stuff as well as
things related to Cart address space (read from write ports,
disassembly, etc).
Fixed E7 bankswitching when reading from the write port in the upper
256byte area.
Fixed 'read from write port functionality' in general for all carts
that supported it previously. Basically, if _rwport is enabled, the
address is checked to be an actual read (vs. one that's part of a
normal write cycle), *and* it's actually an illegal access (each
cart/bankswitch type now provides a hint to indicate this condition).
Still TODO is clean up the rework, properly integrate DiStella, and
fix labels and defines (which seem to be completely broken).
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1922 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-01-17 16:48:45 +00:00
|
|
|
}
|
|
|
|
|
|
2010-06-05 01:17:03 +00:00
|
|
|
// Now output the disassembly, using as little space as possible
|
|
|
|
|
for(uInt32 i = begin; i < end; ++i)
|
|
|
|
|
{
|
2013-05-17 01:05:50 +00:00
|
|
|
const CartDebug::DisassemblyTag& tag = myDisassembly.list[i];
|
2010-11-11 16:46:41 +00:00
|
|
|
if(tag.type == CartDebug::NONE)
|
|
|
|
|
continue;
|
|
|
|
|
else if(tag.address)
|
|
|
|
|
buffer << uppercase << hex << setw(4) << setfill('0') << tag.address
|
|
|
|
|
<< ": ";
|
|
|
|
|
else
|
|
|
|
|
buffer << " ";
|
|
|
|
|
|
2014-06-16 16:34:48 +00:00
|
|
|
buffer << tag.disasm << setw(int(length - tag.disasm.length() + 2))
|
2010-06-05 01:17:03 +00:00
|
|
|
<< setfill(' ') << " "
|
2013-05-17 01:05:50 +00:00
|
|
|
<< setw(4) << left << tag.ccount << " " << tag.bytes << endl;
|
2010-06-05 01:17:03 +00:00
|
|
|
}
|
|
|
|
|
|
2010-02-07 21:23:26 +00:00
|
|
|
return buffer.str();
|
OK, this is the first pass at a huge reorganization of the debugger
classes. First off, the distella code has been integrated into a
DiStella class. This code isn't yet tied to the debugger, but it does
at least compile and generate valid output.
The RamDebug class has been replaced by a CartDebug class, which
takes responsibility for the previous RamDebug stuff as well as
things related to Cart address space (read from write ports,
disassembly, etc).
Fixed E7 bankswitching when reading from the write port in the upper
256byte area.
Fixed 'read from write port functionality' in general for all carts
that supported it previously. Basically, if _rwport is enabled, the
address is checked to be an actual read (vs. one that's part of a
normal write cycle), *and* it's actually an illegal access (each
cart/bankswitch type now provides a hint to indicate this condition).
Still TODO is clean up the rework, properly integrate DiStella, and
fix labels and defines (which seem to be completely broken).
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1922 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-01-17 16:48:45 +00:00
|
|
|
}
|
|
|
|
|
|
2010-08-30 12:04:56 +00:00
|
|
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
2010-09-06 00:17:51 +00:00
|
|
|
bool CartDebug::addDirective(CartDebug::DisasmType type,
|
|
|
|
|
uInt16 start, uInt16 end, int bank)
|
2010-08-30 12:04:56 +00:00
|
|
|
{
|
2010-09-06 23:29:05 +00:00
|
|
|
if(end < start || start == 0 || end == 0)
|
|
|
|
|
return false;
|
|
|
|
|
|
2010-09-06 00:17:51 +00:00
|
|
|
if(bank < 0) // Do we want the current bank or ZP RAM?
|
|
|
|
|
bank = (myDebugger.cpuDebug().pc() & 0x1000) ? getBank() : myBankInfo.size()-1;
|
2010-08-30 12:04:56 +00:00
|
|
|
|
2010-09-06 23:29:05 +00:00
|
|
|
bank = BSPF_min(bank, bankCount());
|
2010-09-06 00:17:51 +00:00
|
|
|
BankInfo& info = myBankInfo[bank];
|
Many big improvements to disassembler directives. Directives are no
longer simply added to a list, but intelligently 'merged' (so that
the entire range represented by all directives contains no overlap).
This makes the disassembly a little faster, since it doesn't have to
iterate redundantly. Still TODO in this area is intelligent insertion
for the same type (ie, if inserting in between like blocks, the
blocks should coalesce, instead of being clipped and then a new range
inserted in between).
Added 'loadconfig' and 'saveconfig' debugger prompt commands, which
will eventually access Distella-like config files. No implementation
is present yet.
Added 'listconfig' debugger command, which lists all directives
currently defined by the user, as well as the directives resulting
from a disassembly of a bank (taking into account extra knowledge
that Stella has WRT cached entry points). This command can show
information for a specified bank, or all banks in the cart.
User-defined directives can now be removed; simply issue the same
command that caused an insertion (ie, attempting to insert the same
type and range will remove it instead).
Fixed bug in Distella processing of directives; similar to the
standalone Distella, directives should be processed *before* any
automatic code determination is done.
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@2121 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-08-31 16:37:27 +00:00
|
|
|
DirectiveList& list = info.directiveList;
|
2010-09-06 00:17:51 +00:00
|
|
|
|
2010-08-30 12:04:56 +00:00
|
|
|
DirectiveTag tag;
|
|
|
|
|
tag.type = type;
|
|
|
|
|
tag.start = start;
|
|
|
|
|
tag.end = end;
|
|
|
|
|
|
Many big improvements to disassembler directives. Directives are no
longer simply added to a list, but intelligently 'merged' (so that
the entire range represented by all directives contains no overlap).
This makes the disassembly a little faster, since it doesn't have to
iterate redundantly. Still TODO in this area is intelligent insertion
for the same type (ie, if inserting in between like blocks, the
blocks should coalesce, instead of being clipped and then a new range
inserted in between).
Added 'loadconfig' and 'saveconfig' debugger prompt commands, which
will eventually access Distella-like config files. No implementation
is present yet.
Added 'listconfig' debugger command, which lists all directives
currently defined by the user, as well as the directives resulting
from a disassembly of a bank (taking into account extra knowledge
that Stella has WRT cached entry points). This command can show
information for a specified bank, or all banks in the cart.
User-defined directives can now be removed; simply issue the same
command that caused an insertion (ie, attempting to insert the same
type and range will remove it instead).
Fixed bug in Distella processing of directives; similar to the
standalone Distella, directives should be processed *before* any
automatic code determination is done.
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@2121 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-08-31 16:37:27 +00:00
|
|
|
DirectiveList::iterator i;
|
|
|
|
|
|
|
|
|
|
// If the same directive and range is added, consider it a removal instead
|
|
|
|
|
for(i = list.begin(); i != list.end(); ++i)
|
|
|
|
|
{
|
|
|
|
|
if(i->type == tag.type && i->start == tag.start && i->end == tag.end)
|
|
|
|
|
{
|
|
|
|
|
list.erase(i);
|
|
|
|
|
return false;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// Otherwise, scan the list and make space for a 'smart' merge
|
|
|
|
|
// Note that there are 4 possibilities:
|
|
|
|
|
// 1: a range is completely inside the new range
|
|
|
|
|
// 2: a range is completely outside the new range
|
|
|
|
|
// 3: a range overlaps at the beginning of the new range
|
|
|
|
|
// 4: a range overlaps at the end of the new range
|
|
|
|
|
for(i = list.begin(); i != list.end(); ++i)
|
|
|
|
|
{
|
|
|
|
|
// Case 1: remove range that is completely inside new range
|
2010-09-01 16:44:31 +00:00
|
|
|
if(tag.start <= i->start && tag.end >= i->end)
|
Many big improvements to disassembler directives. Directives are no
longer simply added to a list, but intelligently 'merged' (so that
the entire range represented by all directives contains no overlap).
This makes the disassembly a little faster, since it doesn't have to
iterate redundantly. Still TODO in this area is intelligent insertion
for the same type (ie, if inserting in between like blocks, the
blocks should coalesce, instead of being clipped and then a new range
inserted in between).
Added 'loadconfig' and 'saveconfig' debugger prompt commands, which
will eventually access Distella-like config files. No implementation
is present yet.
Added 'listconfig' debugger command, which lists all directives
currently defined by the user, as well as the directives resulting
from a disassembly of a bank (taking into account extra knowledge
that Stella has WRT cached entry points). This command can show
information for a specified bank, or all banks in the cart.
User-defined directives can now be removed; simply issue the same
command that caused an insertion (ie, attempting to insert the same
type and range will remove it instead).
Fixed bug in Distella processing of directives; similar to the
standalone Distella, directives should be processed *before* any
automatic code determination is done.
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@2121 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-08-31 16:37:27 +00:00
|
|
|
{
|
2010-10-09 17:55:22 +00:00
|
|
|
i = list.erase(i);
|
Many big improvements to disassembler directives. Directives are no
longer simply added to a list, but intelligently 'merged' (so that
the entire range represented by all directives contains no overlap).
This makes the disassembly a little faster, since it doesn't have to
iterate redundantly. Still TODO in this area is intelligent insertion
for the same type (ie, if inserting in between like blocks, the
blocks should coalesce, instead of being clipped and then a new range
inserted in between).
Added 'loadconfig' and 'saveconfig' debugger prompt commands, which
will eventually access Distella-like config files. No implementation
is present yet.
Added 'listconfig' debugger command, which lists all directives
currently defined by the user, as well as the directives resulting
from a disassembly of a bank (taking into account extra knowledge
that Stella has WRT cached entry points). This command can show
information for a specified bank, or all banks in the cart.
User-defined directives can now be removed; simply issue the same
command that caused an insertion (ie, attempting to insert the same
type and range will remove it instead).
Fixed bug in Distella processing of directives; similar to the
standalone Distella, directives should be processed *before* any
automatic code determination is done.
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@2121 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-08-31 16:37:27 +00:00
|
|
|
}
|
|
|
|
|
// Case 2: split the old range
|
2010-09-01 16:44:31 +00:00
|
|
|
else if(tag.start >= i->start && tag.end <= i->end)
|
Many big improvements to disassembler directives. Directives are no
longer simply added to a list, but intelligently 'merged' (so that
the entire range represented by all directives contains no overlap).
This makes the disassembly a little faster, since it doesn't have to
iterate redundantly. Still TODO in this area is intelligent insertion
for the same type (ie, if inserting in between like blocks, the
blocks should coalesce, instead of being clipped and then a new range
inserted in between).
Added 'loadconfig' and 'saveconfig' debugger prompt commands, which
will eventually access Distella-like config files. No implementation
is present yet.
Added 'listconfig' debugger command, which lists all directives
currently defined by the user, as well as the directives resulting
from a disassembly of a bank (taking into account extra knowledge
that Stella has WRT cached entry points). This command can show
information for a specified bank, or all banks in the cart.
User-defined directives can now be removed; simply issue the same
command that caused an insertion (ie, attempting to insert the same
type and range will remove it instead).
Fixed bug in Distella processing of directives; similar to the
standalone Distella, directives should be processed *before* any
automatic code determination is done.
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@2121 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-08-31 16:37:27 +00:00
|
|
|
{
|
2010-09-01 16:44:31 +00:00
|
|
|
// Only split when necessary
|
|
|
|
|
if(tag.type == i->type)
|
|
|
|
|
return true; // node is fine as-is
|
|
|
|
|
|
Many big improvements to disassembler directives. Directives are no
longer simply added to a list, but intelligently 'merged' (so that
the entire range represented by all directives contains no overlap).
This makes the disassembly a little faster, since it doesn't have to
iterate redundantly. Still TODO in this area is intelligent insertion
for the same type (ie, if inserting in between like blocks, the
blocks should coalesce, instead of being clipped and then a new range
inserted in between).
Added 'loadconfig' and 'saveconfig' debugger prompt commands, which
will eventually access Distella-like config files. No implementation
is present yet.
Added 'listconfig' debugger command, which lists all directives
currently defined by the user, as well as the directives resulting
from a disassembly of a bank (taking into account extra knowledge
that Stella has WRT cached entry points). This command can show
information for a specified bank, or all banks in the cart.
User-defined directives can now be removed; simply issue the same
command that caused an insertion (ie, attempting to insert the same
type and range will remove it instead).
Fixed bug in Distella processing of directives; similar to the
standalone Distella, directives should be processed *before* any
automatic code determination is done.
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@2121 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-08-31 16:37:27 +00:00
|
|
|
// Create new endpoint
|
|
|
|
|
DirectiveTag tag2;
|
|
|
|
|
tag2.type = i->type;
|
|
|
|
|
tag2.start = tag.end + 1;
|
|
|
|
|
tag2.end = i->end;
|
|
|
|
|
|
|
|
|
|
// Modify startpoint
|
|
|
|
|
i->end = tag.start - 1;
|
|
|
|
|
|
|
|
|
|
// Insert new endpoint
|
|
|
|
|
i++;
|
2010-09-01 16:44:31 +00:00
|
|
|
list.insert(i, tag2);
|
Many big improvements to disassembler directives. Directives are no
longer simply added to a list, but intelligently 'merged' (so that
the entire range represented by all directives contains no overlap).
This makes the disassembly a little faster, since it doesn't have to
iterate redundantly. Still TODO in this area is intelligent insertion
for the same type (ie, if inserting in between like blocks, the
blocks should coalesce, instead of being clipped and then a new range
inserted in between).
Added 'loadconfig' and 'saveconfig' debugger prompt commands, which
will eventually access Distella-like config files. No implementation
is present yet.
Added 'listconfig' debugger command, which lists all directives
currently defined by the user, as well as the directives resulting
from a disassembly of a bank (taking into account extra knowledge
that Stella has WRT cached entry points). This command can show
information for a specified bank, or all banks in the cart.
User-defined directives can now be removed; simply issue the same
command that caused an insertion (ie, attempting to insert the same
type and range will remove it instead).
Fixed bug in Distella processing of directives; similar to the
standalone Distella, directives should be processed *before* any
automatic code determination is done.
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@2121 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-08-31 16:37:27 +00:00
|
|
|
break; // no need to go further; this is the insertion point
|
|
|
|
|
}
|
|
|
|
|
// Case 3: truncate end of old range
|
2010-09-01 16:44:31 +00:00
|
|
|
else if(tag.start >= i->start && tag.start <= i->end)
|
Many big improvements to disassembler directives. Directives are no
longer simply added to a list, but intelligently 'merged' (so that
the entire range represented by all directives contains no overlap).
This makes the disassembly a little faster, since it doesn't have to
iterate redundantly. Still TODO in this area is intelligent insertion
for the same type (ie, if inserting in between like blocks, the
blocks should coalesce, instead of being clipped and then a new range
inserted in between).
Added 'loadconfig' and 'saveconfig' debugger prompt commands, which
will eventually access Distella-like config files. No implementation
is present yet.
Added 'listconfig' debugger command, which lists all directives
currently defined by the user, as well as the directives resulting
from a disassembly of a bank (taking into account extra knowledge
that Stella has WRT cached entry points). This command can show
information for a specified bank, or all banks in the cart.
User-defined directives can now be removed; simply issue the same
command that caused an insertion (ie, attempting to insert the same
type and range will remove it instead).
Fixed bug in Distella processing of directives; similar to the
standalone Distella, directives should be processed *before* any
automatic code determination is done.
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@2121 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-08-31 16:37:27 +00:00
|
|
|
{
|
|
|
|
|
i->end = tag.start - 1;
|
|
|
|
|
}
|
|
|
|
|
// Case 4: truncate start of old range
|
2010-09-01 16:44:31 +00:00
|
|
|
else if(tag.end >= i->start && tag.end <= i->end)
|
Many big improvements to disassembler directives. Directives are no
longer simply added to a list, but intelligently 'merged' (so that
the entire range represented by all directives contains no overlap).
This makes the disassembly a little faster, since it doesn't have to
iterate redundantly. Still TODO in this area is intelligent insertion
for the same type (ie, if inserting in between like blocks, the
blocks should coalesce, instead of being clipped and then a new range
inserted in between).
Added 'loadconfig' and 'saveconfig' debugger prompt commands, which
will eventually access Distella-like config files. No implementation
is present yet.
Added 'listconfig' debugger command, which lists all directives
currently defined by the user, as well as the directives resulting
from a disassembly of a bank (taking into account extra knowledge
that Stella has WRT cached entry points). This command can show
information for a specified bank, or all banks in the cart.
User-defined directives can now be removed; simply issue the same
command that caused an insertion (ie, attempting to insert the same
type and range will remove it instead).
Fixed bug in Distella processing of directives; similar to the
standalone Distella, directives should be processed *before* any
automatic code determination is done.
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@2121 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-08-31 16:37:27 +00:00
|
|
|
{
|
|
|
|
|
i->start = tag.end + 1;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// We now know that the new range can be inserted without overlap
|
2010-09-01 16:44:31 +00:00
|
|
|
// Where possible, consecutive ranges should be merged rather than
|
|
|
|
|
// new nodes created
|
Many big improvements to disassembler directives. Directives are no
longer simply added to a list, but intelligently 'merged' (so that
the entire range represented by all directives contains no overlap).
This makes the disassembly a little faster, since it doesn't have to
iterate redundantly. Still TODO in this area is intelligent insertion
for the same type (ie, if inserting in between like blocks, the
blocks should coalesce, instead of being clipped and then a new range
inserted in between).
Added 'loadconfig' and 'saveconfig' debugger prompt commands, which
will eventually access Distella-like config files. No implementation
is present yet.
Added 'listconfig' debugger command, which lists all directives
currently defined by the user, as well as the directives resulting
from a disassembly of a bank (taking into account extra knowledge
that Stella has WRT cached entry points). This command can show
information for a specified bank, or all banks in the cart.
User-defined directives can now be removed; simply issue the same
command that caused an insertion (ie, attempting to insert the same
type and range will remove it instead).
Fixed bug in Distella processing of directives; similar to the
standalone Distella, directives should be processed *before* any
automatic code determination is done.
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@2121 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-08-31 16:37:27 +00:00
|
|
|
for(i = list.begin(); i != list.end(); ++i)
|
|
|
|
|
{
|
2010-09-01 16:44:31 +00:00
|
|
|
if(tag.end < i->start) // node should be inserted *before* this one
|
Many big improvements to disassembler directives. Directives are no
longer simply added to a list, but intelligently 'merged' (so that
the entire range represented by all directives contains no overlap).
This makes the disassembly a little faster, since it doesn't have to
iterate redundantly. Still TODO in this area is intelligent insertion
for the same type (ie, if inserting in between like blocks, the
blocks should coalesce, instead of being clipped and then a new range
inserted in between).
Added 'loadconfig' and 'saveconfig' debugger prompt commands, which
will eventually access Distella-like config files. No implementation
is present yet.
Added 'listconfig' debugger command, which lists all directives
currently defined by the user, as well as the directives resulting
from a disassembly of a bank (taking into account extra knowledge
that Stella has WRT cached entry points). This command can show
information for a specified bank, or all banks in the cart.
User-defined directives can now be removed; simply issue the same
command that caused an insertion (ie, attempting to insert the same
type and range will remove it instead).
Fixed bug in Distella processing of directives; similar to the
standalone Distella, directives should be processed *before* any
automatic code determination is done.
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@2121 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-08-31 16:37:27 +00:00
|
|
|
{
|
2010-09-01 16:44:31 +00:00
|
|
|
bool createNode = true;
|
|
|
|
|
|
|
|
|
|
// Is the new range ending consecutive with the old range beginning?
|
|
|
|
|
// If so, a merge will suffice
|
|
|
|
|
if(i->type == tag.type && tag.end + 1 == i->start)
|
|
|
|
|
{
|
|
|
|
|
i->start = tag.start;
|
|
|
|
|
createNode = false; // a merge was done, so a new node isn't needed
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// Can we also merge with the previous range (if any)?
|
|
|
|
|
if(i != list.begin())
|
|
|
|
|
{
|
|
|
|
|
DirectiveList::iterator p = i;
|
|
|
|
|
--p;
|
|
|
|
|
if(p->type == tag.type && p->end + 1 == tag.start)
|
|
|
|
|
{
|
|
|
|
|
if(createNode) // a merge with right-hand range didn't previously occur
|
|
|
|
|
{
|
|
|
|
|
p->end = tag.end;
|
|
|
|
|
createNode = false; // a merge was done, so a new node isn't needed
|
|
|
|
|
}
|
|
|
|
|
else // merge all three ranges
|
|
|
|
|
{
|
|
|
|
|
i->start = p->start;
|
|
|
|
|
i = list.erase(p);
|
|
|
|
|
createNode = false; // a merge was done, so a new node isn't needed
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// Create the node only when necessary
|
|
|
|
|
if(createNode)
|
|
|
|
|
i = list.insert(i, tag);
|
|
|
|
|
|
Many big improvements to disassembler directives. Directives are no
longer simply added to a list, but intelligently 'merged' (so that
the entire range represented by all directives contains no overlap).
This makes the disassembly a little faster, since it doesn't have to
iterate redundantly. Still TODO in this area is intelligent insertion
for the same type (ie, if inserting in between like blocks, the
blocks should coalesce, instead of being clipped and then a new range
inserted in between).
Added 'loadconfig' and 'saveconfig' debugger prompt commands, which
will eventually access Distella-like config files. No implementation
is present yet.
Added 'listconfig' debugger command, which lists all directives
currently defined by the user, as well as the directives resulting
from a disassembly of a bank (taking into account extra knowledge
that Stella has WRT cached entry points). This command can show
information for a specified bank, or all banks in the cart.
User-defined directives can now be removed; simply issue the same
command that caused an insertion (ie, attempting to insert the same
type and range will remove it instead).
Fixed bug in Distella processing of directives; similar to the
standalone Distella, directives should be processed *before* any
automatic code determination is done.
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@2121 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-08-31 16:37:27 +00:00
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
// Otherwise, add the tag at the end
|
|
|
|
|
if(i == list.end())
|
|
|
|
|
list.push_back(tag);
|
|
|
|
|
|
|
|
|
|
return true;
|
2010-08-30 12:04:56 +00:00
|
|
|
}
|
|
|
|
|
|
OK, this is the first pass at a huge reorganization of the debugger
classes. First off, the distella code has been integrated into a
DiStella class. This code isn't yet tied to the debugger, but it does
at least compile and generate valid output.
The RamDebug class has been replaced by a CartDebug class, which
takes responsibility for the previous RamDebug stuff as well as
things related to Cart address space (read from write ports,
disassembly, etc).
Fixed E7 bankswitching when reading from the write port in the upper
256byte area.
Fixed 'read from write port functionality' in general for all carts
that supported it previously. Basically, if _rwport is enabled, the
address is checked to be an actual read (vs. one that's part of a
normal write cycle), *and* it's actually an illegal access (each
cart/bankswitch type now provides a hint to indicate this condition).
Still TODO is clean up the rework, properly integrate DiStella, and
fix labels and defines (which seem to be completely broken).
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1922 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-01-17 16:48:45 +00:00
|
|
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
2010-04-03 12:45:20 +00:00
|
|
|
bool CartDebug::addLabel(const string& label, uInt16 address)
|
OK, this is the first pass at a huge reorganization of the debugger
classes. First off, the distella code has been integrated into a
DiStella class. This code isn't yet tied to the debugger, but it does
at least compile and generate valid output.
The RamDebug class has been replaced by a CartDebug class, which
takes responsibility for the previous RamDebug stuff as well as
things related to Cart address space (read from write ports,
disassembly, etc).
Fixed E7 bankswitching when reading from the write port in the upper
256byte area.
Fixed 'read from write port functionality' in general for all carts
that supported it previously. Basically, if _rwport is enabled, the
address is checked to be an actual read (vs. one that's part of a
normal write cycle), *and* it's actually an illegal access (each
cart/bankswitch type now provides a hint to indicate this condition).
Still TODO is clean up the rework, properly integrate DiStella, and
fix labels and defines (which seem to be completely broken).
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1922 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-01-17 16:48:45 +00:00
|
|
|
{
|
2010-04-03 12:45:20 +00:00
|
|
|
// Only user-defined labels can be added or redefined
|
2010-02-28 17:12:16 +00:00
|
|
|
switch(addressType(address))
|
|
|
|
|
{
|
|
|
|
|
case ADDR_TIA:
|
2013-05-19 20:55:25 +00:00
|
|
|
case ADDR_IO:
|
2010-04-03 12:45:20 +00:00
|
|
|
return false;
|
2010-02-28 17:12:16 +00:00
|
|
|
default:
|
|
|
|
|
removeLabel(label);
|
|
|
|
|
myUserAddresses.insert(make_pair(label, address));
|
|
|
|
|
myUserLabels.insert(make_pair(address, label));
|
2010-05-12 00:04:14 +00:00
|
|
|
myLabelLength = BSPF_max(myLabelLength, (uInt16)label.size());
|
|
|
|
|
mySystem.setDirtyPage(address);
|
2010-04-03 12:45:20 +00:00
|
|
|
return true;
|
OK, this is the first pass at a huge reorganization of the debugger
classes. First off, the distella code has been integrated into a
DiStella class. This code isn't yet tied to the debugger, but it does
at least compile and generate valid output.
The RamDebug class has been replaced by a CartDebug class, which
takes responsibility for the previous RamDebug stuff as well as
things related to Cart address space (read from write ports,
disassembly, etc).
Fixed E7 bankswitching when reading from the write port in the upper
256byte area.
Fixed 'read from write port functionality' in general for all carts
that supported it previously. Basically, if _rwport is enabled, the
address is checked to be an actual read (vs. one that's part of a
normal write cycle), *and* it's actually an illegal access (each
cart/bankswitch type now provides a hint to indicate this condition).
Still TODO is clean up the rework, properly integrate DiStella, and
fix labels and defines (which seem to be completely broken).
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1922 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-01-17 16:48:45 +00:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
|
|
|
|
bool CartDebug::removeLabel(const string& label)
|
|
|
|
|
{
|
2010-02-28 17:12:16 +00:00
|
|
|
// Only user-defined labels can be removed
|
OK, this is the first pass at a huge reorganization of the debugger
classes. First off, the distella code has been integrated into a
DiStella class. This code isn't yet tied to the debugger, but it does
at least compile and generate valid output.
The RamDebug class has been replaced by a CartDebug class, which
takes responsibility for the previous RamDebug stuff as well as
things related to Cart address space (read from write ports,
disassembly, etc).
Fixed E7 bankswitching when reading from the write port in the upper
256byte area.
Fixed 'read from write port functionality' in general for all carts
that supported it previously. Basically, if _rwport is enabled, the
address is checked to be an actual read (vs. one that's part of a
normal write cycle), *and* it's actually an illegal access (each
cart/bankswitch type now provides a hint to indicate this condition).
Still TODO is clean up the rework, properly integrate DiStella, and
fix labels and defines (which seem to be completely broken).
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1922 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-01-17 16:48:45 +00:00
|
|
|
LabelToAddr::iterator iter = myUserAddresses.find(label);
|
|
|
|
|
if(iter != myUserAddresses.end())
|
|
|
|
|
{
|
2014-10-26 18:46:17 +00:00
|
|
|
// Erase the address assigned to the label
|
2010-02-28 17:12:16 +00:00
|
|
|
AddrToLabel::iterator iter2 = myUserLabels.find(iter->second);
|
OK, this is the first pass at a huge reorganization of the debugger
classes. First off, the distella code has been integrated into a
DiStella class. This code isn't yet tied to the debugger, but it does
at least compile and generate valid output.
The RamDebug class has been replaced by a CartDebug class, which
takes responsibility for the previous RamDebug stuff as well as
things related to Cart address space (read from write ports,
disassembly, etc).
Fixed E7 bankswitching when reading from the write port in the upper
256byte area.
Fixed 'read from write port functionality' in general for all carts
that supported it previously. Basically, if _rwport is enabled, the
address is checked to be an actual read (vs. one that's part of a
normal write cycle), *and* it's actually an illegal access (each
cart/bankswitch type now provides a hint to indicate this condition).
Still TODO is clean up the rework, properly integrate DiStella, and
fix labels and defines (which seem to be completely broken).
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1922 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-01-17 16:48:45 +00:00
|
|
|
if(iter2 != myUserLabels.end())
|
|
|
|
|
myUserLabels.erase(iter2);
|
|
|
|
|
|
2014-10-26 18:46:17 +00:00
|
|
|
// Erase the label itself
|
|
|
|
|
mySystem.setDirtyPage(iter->second);
|
|
|
|
|
myUserAddresses.erase(iter);
|
|
|
|
|
|
OK, this is the first pass at a huge reorganization of the debugger
classes. First off, the distella code has been integrated into a
DiStella class. This code isn't yet tied to the debugger, but it does
at least compile and generate valid output.
The RamDebug class has been replaced by a CartDebug class, which
takes responsibility for the previous RamDebug stuff as well as
things related to Cart address space (read from write ports,
disassembly, etc).
Fixed E7 bankswitching when reading from the write port in the upper
256byte area.
Fixed 'read from write port functionality' in general for all carts
that supported it previously. Basically, if _rwport is enabled, the
address is checked to be an actual read (vs. one that's part of a
normal write cycle), *and* it's actually an illegal access (each
cart/bankswitch type now provides a hint to indicate this condition).
Still TODO is clean up the rework, properly integrate DiStella, and
fix labels and defines (which seem to be completely broken).
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1922 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-01-17 16:48:45 +00:00
|
|
|
return true;
|
|
|
|
|
}
|
|
|
|
|
return false;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
2013-05-19 20:55:25 +00:00
|
|
|
bool CartDebug::getLabel(ostream& buf, uInt16 addr, bool isRead, int places) const
|
OK, this is the first pass at a huge reorganization of the debugger
classes. First off, the distella code has been integrated into a
DiStella class. This code isn't yet tied to the debugger, but it does
at least compile and generate valid output.
The RamDebug class has been replaced by a CartDebug class, which
takes responsibility for the previous RamDebug stuff as well as
things related to Cart address space (read from write ports,
disassembly, etc).
Fixed E7 bankswitching when reading from the write port in the upper
256byte area.
Fixed 'read from write port functionality' in general for all carts
that supported it previously. Basically, if _rwport is enabled, the
address is checked to be an actual read (vs. one that's part of a
normal write cycle), *and* it's actually an illegal access (each
cart/bankswitch type now provides a hint to indicate this condition).
Still TODO is clean up the rework, properly integrate DiStella, and
fix labels and defines (which seem to be completely broken).
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1922 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-01-17 16:48:45 +00:00
|
|
|
{
|
2010-02-28 17:12:16 +00:00
|
|
|
switch(addressType(addr))
|
OK, this is the first pass at a huge reorganization of the debugger
classes. First off, the distella code has been integrated into a
DiStella class. This code isn't yet tied to the debugger, but it does
at least compile and generate valid output.
The RamDebug class has been replaced by a CartDebug class, which
takes responsibility for the previous RamDebug stuff as well as
things related to Cart address space (read from write ports,
disassembly, etc).
Fixed E7 bankswitching when reading from the write port in the upper
256byte area.
Fixed 'read from write port functionality' in general for all carts
that supported it previously. Basically, if _rwport is enabled, the
address is checked to be an actual read (vs. one that's part of a
normal write cycle), *and* it's actually an illegal access (each
cart/bankswitch type now provides a hint to indicate this condition).
Still TODO is clean up the rework, properly integrate DiStella, and
fix labels and defines (which seem to be completely broken).
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1922 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-01-17 16:48:45 +00:00
|
|
|
{
|
|
|
|
|
case ADDR_TIA:
|
2013-05-19 20:55:25 +00:00
|
|
|
{
|
|
|
|
|
if(isRead)
|
|
|
|
|
{
|
|
|
|
|
uInt16 a = addr & 0x0F, offset = addr & 0xFFF0;
|
|
|
|
|
if(ourTIAMnemonicR[a])
|
|
|
|
|
{
|
|
|
|
|
buf << ourTIAMnemonicR[a];
|
|
|
|
|
if(offset > 0)
|
2013-07-27 22:28:41 +00:00
|
|
|
buf << "|$" << Base::HEX2 << offset;
|
2013-05-19 20:55:25 +00:00
|
|
|
}
|
|
|
|
|
else
|
2013-07-27 22:28:41 +00:00
|
|
|
buf << "$" << Base::HEX2 << addr;
|
2013-05-19 20:55:25 +00:00
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
uInt16 a = addr & 0x3F, offset = addr & 0xFFC0;
|
|
|
|
|
if(ourTIAMnemonicW[a])
|
|
|
|
|
{
|
|
|
|
|
buf << ourTIAMnemonicW[a];
|
|
|
|
|
if(offset > 0)
|
2013-07-27 22:28:41 +00:00
|
|
|
buf << "|$" << Base::HEX2 << offset;
|
2013-05-19 20:55:25 +00:00
|
|
|
}
|
|
|
|
|
else
|
2013-07-27 22:28:41 +00:00
|
|
|
buf << "$" << Base::HEX2 << addr;
|
2013-05-19 20:55:25 +00:00
|
|
|
}
|
|
|
|
|
return true;
|
|
|
|
|
}
|
OK, this is the first pass at a huge reorganization of the debugger
classes. First off, the distella code has been integrated into a
DiStella class. This code isn't yet tied to the debugger, but it does
at least compile and generate valid output.
The RamDebug class has been replaced by a CartDebug class, which
takes responsibility for the previous RamDebug stuff as well as
things related to Cart address space (read from write ports,
disassembly, etc).
Fixed E7 bankswitching when reading from the write port in the upper
256byte area.
Fixed 'read from write port functionality' in general for all carts
that supported it previously. Basically, if _rwport is enabled, the
address is checked to be an actual read (vs. one that's part of a
normal write cycle), *and* it's actually an illegal access (each
cart/bankswitch type now provides a hint to indicate this condition).
Still TODO is clean up the rework, properly integrate DiStella, and
fix labels and defines (which seem to be completely broken).
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1922 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-01-17 16:48:45 +00:00
|
|
|
|
2013-05-19 20:55:25 +00:00
|
|
|
case ADDR_IO:
|
2010-04-23 19:25:11 +00:00
|
|
|
{
|
2013-05-19 20:55:25 +00:00
|
|
|
uInt16 a = addr & 0xFF, offset = addr & 0xFD00;
|
|
|
|
|
if(a <= 0x97)
|
|
|
|
|
{
|
|
|
|
|
if(ourIOMnemonic[a - 0x80])
|
|
|
|
|
{
|
|
|
|
|
buf << ourIOMnemonic[a - 0x80];
|
|
|
|
|
if(offset > 0)
|
2013-07-27 22:28:41 +00:00
|
|
|
buf << "|$" << Base::HEX2 << offset;
|
2013-05-19 20:55:25 +00:00
|
|
|
}
|
|
|
|
|
else
|
2013-07-27 22:28:41 +00:00
|
|
|
buf << "$" << Base::HEX2 << addr;
|
2013-05-19 20:55:25 +00:00
|
|
|
}
|
|
|
|
|
else
|
2013-07-27 22:28:41 +00:00
|
|
|
buf << "$" << Base::HEX2 << addr;
|
2013-05-19 20:55:25 +00:00
|
|
|
|
|
|
|
|
return true;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
case ADDR_ZPRAM:
|
|
|
|
|
{
|
|
|
|
|
// RAM can use user-defined labels; otherwise we default to
|
|
|
|
|
// standard mnemonics
|
|
|
|
|
AddrToLabel::const_iterator iter;
|
|
|
|
|
if((iter = myUserLabels.find(addr)) != myUserLabels.end())
|
|
|
|
|
{
|
|
|
|
|
buf << iter->second;
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
uInt16 a = addr & 0xFF, offset = addr & 0xFF00;
|
|
|
|
|
if((iter = myUserLabels.find(a)) != myUserLabels.end())
|
|
|
|
|
buf << iter->second;
|
|
|
|
|
else
|
|
|
|
|
buf << ourZPMnemonic[a - 0x80];
|
|
|
|
|
if(offset > 0)
|
2013-07-27 22:28:41 +00:00
|
|
|
buf << "|$" << Base::HEX2 << offset;
|
2013-05-19 20:55:25 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return true;
|
2010-04-23 19:25:11 +00:00
|
|
|
}
|
OK, this is the first pass at a huge reorganization of the debugger
classes. First off, the distella code has been integrated into a
DiStella class. This code isn't yet tied to the debugger, but it does
at least compile and generate valid output.
The RamDebug class has been replaced by a CartDebug class, which
takes responsibility for the previous RamDebug stuff as well as
things related to Cart address space (read from write ports,
disassembly, etc).
Fixed E7 bankswitching when reading from the write port in the upper
256byte area.
Fixed 'read from write port functionality' in general for all carts
that supported it previously. Basically, if _rwport is enabled, the
address is checked to be an actual read (vs. one that's part of a
normal write cycle), *and* it's actually an illegal access (each
cart/bankswitch type now provides a hint to indicate this condition).
Still TODO is clean up the rework, properly integrate DiStella, and
fix labels and defines (which seem to be completely broken).
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1922 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-01-17 16:48:45 +00:00
|
|
|
|
|
|
|
|
case ADDR_ROM:
|
2010-02-28 17:12:16 +00:00
|
|
|
{
|
OK, this is the first pass at a huge reorganization of the debugger
classes. First off, the distella code has been integrated into a
DiStella class. This code isn't yet tied to the debugger, but it does
at least compile and generate valid output.
The RamDebug class has been replaced by a CartDebug class, which
takes responsibility for the previous RamDebug stuff as well as
things related to Cart address space (read from write ports,
disassembly, etc).
Fixed E7 bankswitching when reading from the write port in the upper
256byte area.
Fixed 'read from write port functionality' in general for all carts
that supported it previously. Basically, if _rwport is enabled, the
address is checked to be an actual read (vs. one that's part of a
normal write cycle), *and* it's actually an illegal access (each
cart/bankswitch type now provides a hint to indicate this condition).
Still TODO is clean up the rework, properly integrate DiStella, and
fix labels and defines (which seem to be completely broken).
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1922 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-01-17 16:48:45 +00:00
|
|
|
// These addresses can never be in the system labels list
|
2010-02-28 17:12:16 +00:00
|
|
|
AddrToLabel::const_iterator iter;
|
OK, this is the first pass at a huge reorganization of the debugger
classes. First off, the distella code has been integrated into a
DiStella class. This code isn't yet tied to the debugger, but it does
at least compile and generate valid output.
The RamDebug class has been replaced by a CartDebug class, which
takes responsibility for the previous RamDebug stuff as well as
things related to Cart address space (read from write ports,
disassembly, etc).
Fixed E7 bankswitching when reading from the write port in the upper
256byte area.
Fixed 'read from write port functionality' in general for all carts
that supported it previously. Basically, if _rwport is enabled, the
address is checked to be an actual read (vs. one that's part of a
normal write cycle), *and* it's actually an illegal access (each
cart/bankswitch type now provides a hint to indicate this condition).
Still TODO is clean up the rework, properly integrate DiStella, and
fix labels and defines (which seem to be completely broken).
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1922 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-01-17 16:48:45 +00:00
|
|
|
if((iter = myUserLabels.find(addr)) != myUserLabels.end())
|
2013-05-19 20:55:25 +00:00
|
|
|
{
|
|
|
|
|
buf << iter->second;
|
|
|
|
|
return true;
|
|
|
|
|
}
|
OK, this is the first pass at a huge reorganization of the debugger
classes. First off, the distella code has been integrated into a
DiStella class. This code isn't yet tied to the debugger, but it does
at least compile and generate valid output.
The RamDebug class has been replaced by a CartDebug class, which
takes responsibility for the previous RamDebug stuff as well as
things related to Cart address space (read from write ports,
disassembly, etc).
Fixed E7 bankswitching when reading from the write port in the upper
256byte area.
Fixed 'read from write port functionality' in general for all carts
that supported it previously. Basically, if _rwport is enabled, the
address is checked to be an actual read (vs. one that's part of a
normal write cycle), *and* it's actually an illegal access (each
cart/bankswitch type now provides a hint to indicate this condition).
Still TODO is clean up the rework, properly integrate DiStella, and
fix labels and defines (which seem to be completely broken).
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1922 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-01-17 16:48:45 +00:00
|
|
|
break;
|
2010-02-28 17:12:16 +00:00
|
|
|
}
|
OK, this is the first pass at a huge reorganization of the debugger
classes. First off, the distella code has been integrated into a
DiStella class. This code isn't yet tied to the debugger, but it does
at least compile and generate valid output.
The RamDebug class has been replaced by a CartDebug class, which
takes responsibility for the previous RamDebug stuff as well as
things related to Cart address space (read from write ports,
disassembly, etc).
Fixed E7 bankswitching when reading from the write port in the upper
256byte area.
Fixed 'read from write port functionality' in general for all carts
that supported it previously. Basically, if _rwport is enabled, the
address is checked to be an actual read (vs. one that's part of a
normal write cycle), *and* it's actually an illegal access (each
cart/bankswitch type now provides a hint to indicate this condition).
Still TODO is clean up the rework, properly integrate DiStella, and
fix labels and defines (which seem to be completely broken).
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1922 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-01-17 16:48:45 +00:00
|
|
|
}
|
|
|
|
|
|
2013-08-20 14:00:25 +00:00
|
|
|
switch(places)
|
OK, this is the first pass at a huge reorganization of the debugger
classes. First off, the distella code has been integrated into a
DiStella class. This code isn't yet tied to the debugger, but it does
at least compile and generate valid output.
The RamDebug class has been replaced by a CartDebug class, which
takes responsibility for the previous RamDebug stuff as well as
things related to Cart address space (read from write ports,
disassembly, etc).
Fixed E7 bankswitching when reading from the write port in the upper
256byte area.
Fixed 'read from write port functionality' in general for all carts
that supported it previously. Basically, if _rwport is enabled, the
address is checked to be an actual read (vs. one that's part of a
normal write cycle), *and* it's actually an illegal access (each
cart/bankswitch type now provides a hint to indicate this condition).
Still TODO is clean up the rework, properly integrate DiStella, and
fix labels and defines (which seem to be completely broken).
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1922 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-01-17 16:48:45 +00:00
|
|
|
{
|
2013-08-20 14:00:25 +00:00
|
|
|
case 2:
|
|
|
|
|
buf << "$" << Base::HEX2 << addr;
|
|
|
|
|
return true;
|
|
|
|
|
case 4:
|
|
|
|
|
buf << "$" << Base::HEX4 << addr;
|
|
|
|
|
return true;
|
|
|
|
|
case 8:
|
|
|
|
|
buf << "$" << Base::HEX8 << addr;
|
|
|
|
|
return true;
|
OK, this is the first pass at a huge reorganization of the debugger
classes. First off, the distella code has been integrated into a
DiStella class. This code isn't yet tied to the debugger, but it does
at least compile and generate valid output.
The RamDebug class has been replaced by a CartDebug class, which
takes responsibility for the previous RamDebug stuff as well as
things related to Cart address space (read from write ports,
disassembly, etc).
Fixed E7 bankswitching when reading from the write port in the upper
256byte area.
Fixed 'read from write port functionality' in general for all carts
that supported it previously. Basically, if _rwport is enabled, the
address is checked to be an actual read (vs. one that's part of a
normal write cycle), *and* it's actually an illegal access (each
cart/bankswitch type now provides a hint to indicate this condition).
Still TODO is clean up the rework, properly integrate DiStella, and
fix labels and defines (which seem to be completely broken).
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1922 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-01-17 16:48:45 +00:00
|
|
|
}
|
|
|
|
|
|
2013-05-19 20:55:25 +00:00
|
|
|
return false;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
|
|
|
|
string CartDebug::getLabel(uInt16 addr, bool isRead, int places) const
|
|
|
|
|
{
|
|
|
|
|
ostringstream buf;
|
|
|
|
|
getLabel(buf, addr, isRead, places);
|
|
|
|
|
return buf.str();
|
OK, this is the first pass at a huge reorganization of the debugger
classes. First off, the distella code has been integrated into a
DiStella class. This code isn't yet tied to the debugger, but it does
at least compile and generate valid output.
The RamDebug class has been replaced by a CartDebug class, which
takes responsibility for the previous RamDebug stuff as well as
things related to Cart address space (read from write ports,
disassembly, etc).
Fixed E7 bankswitching when reading from the write port in the upper
256byte area.
Fixed 'read from write port functionality' in general for all carts
that supported it previously. Basically, if _rwport is enabled, the
address is checked to be an actual read (vs. one that's part of a
normal write cycle), *and* it's actually an illegal access (each
cart/bankswitch type now provides a hint to indicate this condition).
Still TODO is clean up the rework, properly integrate DiStella, and
fix labels and defines (which seem to be completely broken).
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1922 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-01-17 16:48:45 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
|
|
|
|
int CartDebug::getAddress(const string& label) const
|
|
|
|
|
{
|
|
|
|
|
LabelToAddr::const_iterator iter;
|
|
|
|
|
|
|
|
|
|
if((iter = mySystemAddresses.find(label)) != mySystemAddresses.end())
|
2010-04-03 12:45:20 +00:00
|
|
|
return iter->second;
|
OK, this is the first pass at a huge reorganization of the debugger
classes. First off, the distella code has been integrated into a
DiStella class. This code isn't yet tied to the debugger, but it does
at least compile and generate valid output.
The RamDebug class has been replaced by a CartDebug class, which
takes responsibility for the previous RamDebug stuff as well as
things related to Cart address space (read from write ports,
disassembly, etc).
Fixed E7 bankswitching when reading from the write port in the upper
256byte area.
Fixed 'read from write port functionality' in general for all carts
that supported it previously. Basically, if _rwport is enabled, the
address is checked to be an actual read (vs. one that's part of a
normal write cycle), *and* it's actually an illegal access (each
cart/bankswitch type now provides a hint to indicate this condition).
Still TODO is clean up the rework, properly integrate DiStella, and
fix labels and defines (which seem to be completely broken).
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1922 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-01-17 16:48:45 +00:00
|
|
|
else if((iter = myUserAddresses.find(label)) != myUserAddresses.end())
|
2010-04-03 12:45:20 +00:00
|
|
|
return iter->second;
|
OK, this is the first pass at a huge reorganization of the debugger
classes. First off, the distella code has been integrated into a
DiStella class. This code isn't yet tied to the debugger, but it does
at least compile and generate valid output.
The RamDebug class has been replaced by a CartDebug class, which
takes responsibility for the previous RamDebug stuff as well as
things related to Cart address space (read from write ports,
disassembly, etc).
Fixed E7 bankswitching when reading from the write port in the upper
256byte area.
Fixed 'read from write port functionality' in general for all carts
that supported it previously. Basically, if _rwport is enabled, the
address is checked to be an actual read (vs. one that's part of a
normal write cycle), *and* it's actually an illegal access (each
cart/bankswitch type now provides a hint to indicate this condition).
Still TODO is clean up the rework, properly integrate DiStella, and
fix labels and defines (which seem to be completely broken).
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1922 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-01-17 16:48:45 +00:00
|
|
|
else
|
|
|
|
|
return -1;
|
|
|
|
|
}
|
|
|
|
|
|
2013-08-15 16:07:58 +00:00
|
|
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
|
|
|
|
string CartDebug::loadListFile()
|
|
|
|
|
{
|
|
|
|
|
// Currently, the default naming/location for list files is:
|
|
|
|
|
// 1) ROM dir based on properties entry name
|
|
|
|
|
|
|
|
|
|
if(myListFile == "")
|
|
|
|
|
{
|
|
|
|
|
const string& propsname =
|
|
|
|
|
myConsole.properties().get(Cartridge_Name) + ".lst";
|
|
|
|
|
|
|
|
|
|
FilesystemNode case1(myOSystem.romFile().getParent().getPath() + propsname);
|
|
|
|
|
if(case1.isFile() && case1.isReadable())
|
|
|
|
|
myListFile = case1.getPath();
|
|
|
|
|
else
|
|
|
|
|
return DebuggerParser::red("list file not found in:\n " + case1.getShortPath());
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
FilesystemNode node(myListFile);
|
|
|
|
|
ifstream in(node.getPath().c_str());
|
|
|
|
|
if(!in.is_open())
|
|
|
|
|
return DebuggerParser::red("list file '" + node.getShortPath() + "' not readable");
|
|
|
|
|
|
|
|
|
|
myUserCLabels.clear();
|
|
|
|
|
|
|
|
|
|
while(!in.eof())
|
|
|
|
|
{
|
2013-08-22 21:34:22 +00:00
|
|
|
string line, addr_s;
|
2013-08-15 16:07:58 +00:00
|
|
|
|
|
|
|
|
getline(in, line);
|
|
|
|
|
|
|
|
|
|
if(line.length() == 0 || line[0] == '-')
|
|
|
|
|
continue;
|
|
|
|
|
else // Search for constants
|
|
|
|
|
{
|
|
|
|
|
stringstream buf(line);
|
|
|
|
|
|
2013-08-22 21:34:22 +00:00
|
|
|
// Swallow first value, then get actual numerical value for address
|
|
|
|
|
// We need to read the address as a string, since it may contain 'U'
|
2014-10-26 18:46:17 +00:00
|
|
|
int addr = -1;
|
2013-08-22 21:34:22 +00:00
|
|
|
buf >> addr >> addr_s;
|
|
|
|
|
if(addr_s.length() == 0)
|
|
|
|
|
continue;
|
|
|
|
|
const char* p = addr_s[0] == 'U' ? addr_s.c_str() + 1 : addr_s.c_str();
|
2014-06-16 16:34:48 +00:00
|
|
|
addr = (int)strtoul(p, NULL, 16);
|
2013-08-15 16:07:58 +00:00
|
|
|
|
2013-08-22 21:34:22 +00:00
|
|
|
// For now, completely ignore ROM addresses
|
|
|
|
|
if(!(addr & 0x1000))
|
2013-08-15 16:07:58 +00:00
|
|
|
{
|
|
|
|
|
// Search for pattern 'xx yy CONSTANT ='
|
2013-08-22 21:34:22 +00:00
|
|
|
buf.seekg(20); // skip potential '????'
|
2013-08-15 16:07:58 +00:00
|
|
|
int xx = -1, yy = -1;
|
|
|
|
|
char eq = '\0';
|
|
|
|
|
buf >> hex >> xx >> hex >> yy >> line >> eq;
|
2013-08-22 21:34:22 +00:00
|
|
|
if(xx >= 0 && yy >= 0 && eq == '=')
|
|
|
|
|
myUserCLabels.insert(make_pair(xx*256+yy, line));
|
2013-08-15 16:07:58 +00:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
in.close();
|
|
|
|
|
myDebugger.rom().invalidate();
|
|
|
|
|
|
|
|
|
|
return "loaded " + node.getShortPath() + " OK";
|
|
|
|
|
}
|
|
|
|
|
|
OK, this is the first pass at a huge reorganization of the debugger
classes. First off, the distella code has been integrated into a
DiStella class. This code isn't yet tied to the debugger, but it does
at least compile and generate valid output.
The RamDebug class has been replaced by a CartDebug class, which
takes responsibility for the previous RamDebug stuff as well as
things related to Cart address space (read from write ports,
disassembly, etc).
Fixed E7 bankswitching when reading from the write port in the upper
256byte area.
Fixed 'read from write port functionality' in general for all carts
that supported it previously. Basically, if _rwport is enabled, the
address is checked to be an actual read (vs. one that's part of a
normal write cycle), *and* it's actually an illegal access (each
cart/bankswitch type now provides a hint to indicate this condition).
Still TODO is clean up the rework, properly integrate DiStella, and
fix labels and defines (which seem to be completely broken).
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1922 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-01-17 16:48:45 +00:00
|
|
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
2013-05-16 19:11:44 +00:00
|
|
|
string CartDebug::loadSymbolFile()
|
OK, this is the first pass at a huge reorganization of the debugger
classes. First off, the distella code has been integrated into a
DiStella class. This code isn't yet tied to the debugger, but it does
at least compile and generate valid output.
The RamDebug class has been replaced by a CartDebug class, which
takes responsibility for the previous RamDebug stuff as well as
things related to Cart address space (read from write ports,
disassembly, etc).
Fixed E7 bankswitching when reading from the write port in the upper
256byte area.
Fixed 'read from write port functionality' in general for all carts
that supported it previously. Basically, if _rwport is enabled, the
address is checked to be an actual read (vs. one that's part of a
normal write cycle), *and* it's actually an illegal access (each
cart/bankswitch type now provides a hint to indicate this condition).
Still TODO is clean up the rework, properly integrate DiStella, and
fix labels and defines (which seem to be completely broken).
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1922 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-01-17 16:48:45 +00:00
|
|
|
{
|
2013-05-16 19:11:44 +00:00
|
|
|
// Currently, the default naming/location for symbol files is:
|
|
|
|
|
// 1) ROM dir based on properties entry name
|
2010-09-06 23:29:05 +00:00
|
|
|
|
2013-05-16 19:11:44 +00:00
|
|
|
if(mySymbolFile == "")
|
OK, this is the first pass at a huge reorganization of the debugger
classes. First off, the distella code has been integrated into a
DiStella class. This code isn't yet tied to the debugger, but it does
at least compile and generate valid output.
The RamDebug class has been replaced by a CartDebug class, which
takes responsibility for the previous RamDebug stuff as well as
things related to Cart address space (read from write ports,
disassembly, etc).
Fixed E7 bankswitching when reading from the write port in the upper
256byte area.
Fixed 'read from write port functionality' in general for all carts
that supported it previously. Basically, if _rwport is enabled, the
address is checked to be an actual read (vs. one that's part of a
normal write cycle), *and* it's actually an illegal access (each
cart/bankswitch type now provides a hint to indicate this condition).
Still TODO is clean up the rework, properly integrate DiStella, and
fix labels and defines (which seem to be completely broken).
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1922 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-01-17 16:48:45 +00:00
|
|
|
{
|
2013-05-16 19:11:44 +00:00
|
|
|
const string& propsname =
|
|
|
|
|
myConsole.properties().get(Cartridge_Name) + ".sym";
|
OK, this is the first pass at a huge reorganization of the debugger
classes. First off, the distella code has been integrated into a
DiStella class. This code isn't yet tied to the debugger, but it does
at least compile and generate valid output.
The RamDebug class has been replaced by a CartDebug class, which
takes responsibility for the previous RamDebug stuff as well as
things related to Cart address space (read from write ports,
disassembly, etc).
Fixed E7 bankswitching when reading from the write port in the upper
256byte area.
Fixed 'read from write port functionality' in general for all carts
that supported it previously. Basically, if _rwport is enabled, the
address is checked to be an actual read (vs. one that's part of a
normal write cycle), *and* it's actually an illegal access (each
cart/bankswitch type now provides a hint to indicate this condition).
Still TODO is clean up the rework, properly integrate DiStella, and
fix labels and defines (which seem to be completely broken).
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1922 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-01-17 16:48:45 +00:00
|
|
|
|
2013-06-21 12:15:32 +00:00
|
|
|
FilesystemNode case1(myOSystem.romFile().getParent().getPath() + propsname);
|
2013-05-16 19:11:44 +00:00
|
|
|
if(case1.isFile() && case1.isReadable())
|
|
|
|
|
mySymbolFile = case1.getPath();
|
|
|
|
|
else
|
|
|
|
|
return DebuggerParser::red("symbol file not found in:\n " + case1.getShortPath());
|
|
|
|
|
}
|
OK, this is the first pass at a huge reorganization of the debugger
classes. First off, the distella code has been integrated into a
DiStella class. This code isn't yet tied to the debugger, but it does
at least compile and generate valid output.
The RamDebug class has been replaced by a CartDebug class, which
takes responsibility for the previous RamDebug stuff as well as
things related to Cart address space (read from write ports,
disassembly, etc).
Fixed E7 bankswitching when reading from the write port in the upper
256byte area.
Fixed 'read from write port functionality' in general for all carts
that supported it previously. Basically, if _rwport is enabled, the
address is checked to be an actual read (vs. one that's part of a
normal write cycle), *and* it's actually an illegal access (each
cart/bankswitch type now provides a hint to indicate this condition).
Still TODO is clean up the rework, properly integrate DiStella, and
fix labels and defines (which seem to be completely broken).
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1922 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-01-17 16:48:45 +00:00
|
|
|
|
2013-05-16 19:11:44 +00:00
|
|
|
FilesystemNode node(mySymbolFile);
|
|
|
|
|
ifstream in(node.getPath().c_str());
|
|
|
|
|
if(!in.is_open())
|
|
|
|
|
return DebuggerParser::red("symbol file '" + node.getShortPath() + "' not readable");
|
2010-11-04 19:29:12 +00:00
|
|
|
|
2013-05-16 19:11:44 +00:00
|
|
|
myUserAddresses.clear();
|
|
|
|
|
myUserLabels.clear();
|
2010-11-04 19:29:12 +00:00
|
|
|
|
2013-05-16 19:11:44 +00:00
|
|
|
while(!in.eof())
|
|
|
|
|
{
|
|
|
|
|
string label;
|
|
|
|
|
int value = -1;
|
|
|
|
|
|
|
|
|
|
getline(in, label);
|
2013-08-15 16:07:58 +00:00
|
|
|
stringstream buf(label);
|
2013-05-16 19:11:44 +00:00
|
|
|
buf >> label >> hex >> value;
|
|
|
|
|
|
|
|
|
|
if(label.length() > 0 && label[0] != '-' && value >= 0)
|
2013-08-15 16:07:58 +00:00
|
|
|
{
|
|
|
|
|
// Make sure the value doesn't represent a constant
|
|
|
|
|
// For now, we simply ignore constants completely
|
2014-11-02 23:40:20 +00:00
|
|
|
const auto& iter = myUserCLabels.find(value);
|
2013-08-15 16:07:58 +00:00
|
|
|
if(iter == myUserCLabels.end() || !BSPF_equalsIgnoreCase(label, iter->second))
|
2013-08-20 14:29:28 +00:00
|
|
|
{
|
|
|
|
|
// Check for period, and strip leading number
|
|
|
|
|
if(string::size_type pos = label.find_first_of(".", 0) != string::npos)
|
|
|
|
|
addLabel(label.substr(pos), value);
|
|
|
|
|
else
|
|
|
|
|
addLabel(label, value);
|
|
|
|
|
}
|
2013-08-15 16:07:58 +00:00
|
|
|
}
|
OK, this is the first pass at a huge reorganization of the debugger
classes. First off, the distella code has been integrated into a
DiStella class. This code isn't yet tied to the debugger, but it does
at least compile and generate valid output.
The RamDebug class has been replaced by a CartDebug class, which
takes responsibility for the previous RamDebug stuff as well as
things related to Cart address space (read from write ports,
disassembly, etc).
Fixed E7 bankswitching when reading from the write port in the upper
256byte area.
Fixed 'read from write port functionality' in general for all carts
that supported it previously. Basically, if _rwport is enabled, the
address is checked to be an actual read (vs. one that's part of a
normal write cycle), *and* it's actually an illegal access (each
cart/bankswitch type now provides a hint to indicate this condition).
Still TODO is clean up the rework, properly integrate DiStella, and
fix labels and defines (which seem to be completely broken).
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1922 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-01-17 16:48:45 +00:00
|
|
|
}
|
2013-05-16 19:11:44 +00:00
|
|
|
in.close();
|
|
|
|
|
myDebugger.rom().invalidate();
|
|
|
|
|
|
|
|
|
|
return "loaded " + node.getShortPath() + " OK";
|
OK, this is the first pass at a huge reorganization of the debugger
classes. First off, the distella code has been integrated into a
DiStella class. This code isn't yet tied to the debugger, but it does
at least compile and generate valid output.
The RamDebug class has been replaced by a CartDebug class, which
takes responsibility for the previous RamDebug stuff as well as
things related to Cart address space (read from write ports,
disassembly, etc).
Fixed E7 bankswitching when reading from the write port in the upper
256byte area.
Fixed 'read from write port functionality' in general for all carts
that supported it previously. Basically, if _rwport is enabled, the
address is checked to be an actual read (vs. one that's part of a
normal write cycle), *and* it's actually an illegal access (each
cart/bankswitch type now provides a hint to indicate this condition).
Still TODO is clean up the rework, properly integrate DiStella, and
fix labels and defines (which seem to be completely broken).
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1922 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-01-17 16:48:45 +00:00
|
|
|
}
|
|
|
|
|
|
Many big improvements to disassembler directives. Directives are no
longer simply added to a list, but intelligently 'merged' (so that
the entire range represented by all directives contains no overlap).
This makes the disassembly a little faster, since it doesn't have to
iterate redundantly. Still TODO in this area is intelligent insertion
for the same type (ie, if inserting in between like blocks, the
blocks should coalesce, instead of being clipped and then a new range
inserted in between).
Added 'loadconfig' and 'saveconfig' debugger prompt commands, which
will eventually access Distella-like config files. No implementation
is present yet.
Added 'listconfig' debugger command, which lists all directives
currently defined by the user, as well as the directives resulting
from a disassembly of a bank (taking into account extra knowledge
that Stella has WRT cached entry points). This command can show
information for a specified bank, or all banks in the cart.
User-defined directives can now be removed; simply issue the same
command that caused an insertion (ie, attempting to insert the same
type and range will remove it instead).
Fixed bug in Distella processing of directives; similar to the
standalone Distella, directives should be processed *before* any
automatic code determination is done.
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@2121 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-08-31 16:37:27 +00:00
|
|
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
2013-05-16 19:11:44 +00:00
|
|
|
string CartDebug::loadConfigFile()
|
Many big improvements to disassembler directives. Directives are no
longer simply added to a list, but intelligently 'merged' (so that
the entire range represented by all directives contains no overlap).
This makes the disassembly a little faster, since it doesn't have to
iterate redundantly. Still TODO in this area is intelligent insertion
for the same type (ie, if inserting in between like blocks, the
blocks should coalesce, instead of being clipped and then a new range
inserted in between).
Added 'loadconfig' and 'saveconfig' debugger prompt commands, which
will eventually access Distella-like config files. No implementation
is present yet.
Added 'listconfig' debugger command, which lists all directives
currently defined by the user, as well as the directives resulting
from a disassembly of a bank (taking into account extra knowledge
that Stella has WRT cached entry points). This command can show
information for a specified bank, or all banks in the cart.
User-defined directives can now be removed; simply issue the same
command that caused an insertion (ie, attempting to insert the same
type and range will remove it instead).
Fixed bug in Distella processing of directives; similar to the
standalone Distella, directives should be processed *before* any
automatic code determination is done.
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@2121 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-08-31 16:37:27 +00:00
|
|
|
{
|
2013-05-16 22:05:14 +00:00
|
|
|
if(myConsole.cartridge().bankCount() > 1)
|
2013-06-26 16:03:08 +00:00
|
|
|
return DebuggerParser::red("config file for multi-bank ROM not yet supported");
|
2013-05-16 22:05:14 +00:00
|
|
|
|
2013-05-16 19:11:44 +00:00
|
|
|
// There are two possible locations for loading config files
|
|
|
|
|
// (in order of decreasing relevance):
|
|
|
|
|
// 1) ROM dir based on properties entry name
|
|
|
|
|
// 2) CFG dir based on properties entry name
|
2010-09-06 00:17:51 +00:00
|
|
|
|
2013-05-16 19:11:44 +00:00
|
|
|
if(myCfgFile == "")
|
2010-09-06 00:17:51 +00:00
|
|
|
{
|
2010-09-06 23:29:05 +00:00
|
|
|
const string& propsname =
|
|
|
|
|
myConsole.properties().get(Cartridge_Name) + ".cfg";
|
|
|
|
|
|
2013-06-21 12:15:32 +00:00
|
|
|
FilesystemNode case1(myOSystem.romFile().getParent().getPath() + propsname);
|
2013-05-16 19:11:44 +00:00
|
|
|
FilesystemNode case2(myOSystem.cfgDir() + propsname);
|
|
|
|
|
|
|
|
|
|
if(case1.isFile() && case1.isReadable())
|
|
|
|
|
myCfgFile = case1.getPath();
|
|
|
|
|
else if(case2.isFile() && case2.isReadable())
|
|
|
|
|
myCfgFile = case2.getPath();
|
2010-09-06 23:29:05 +00:00
|
|
|
else
|
2013-05-16 19:11:44 +00:00
|
|
|
return DebuggerParser::red("config file not found in:\n " +
|
|
|
|
|
case1.getShortPath() + "\n " + case2.getShortPath());
|
2010-09-06 00:17:51 +00:00
|
|
|
}
|
|
|
|
|
|
2013-05-16 19:11:44 +00:00
|
|
|
FilesystemNode node(myCfgFile);
|
|
|
|
|
ifstream in(node.getPath().c_str());
|
|
|
|
|
if(!in.is_open())
|
|
|
|
|
return "Unable to load directives from " + node.getPath();
|
|
|
|
|
|
|
|
|
|
// Erase all previous directives
|
2014-11-02 23:40:20 +00:00
|
|
|
for(auto& bi: myBankInfo)
|
|
|
|
|
bi.directiveList.clear();
|
2010-09-06 23:29:05 +00:00
|
|
|
|
2013-05-16 19:11:44 +00:00
|
|
|
int currentbank = 0;
|
|
|
|
|
while(!in.eof())
|
|
|
|
|
{
|
|
|
|
|
// Skip leading space
|
|
|
|
|
int c = in.peek();
|
|
|
|
|
while(c == ' ' && c == '\t')
|
2010-09-06 23:29:05 +00:00
|
|
|
{
|
2013-05-16 19:11:44 +00:00
|
|
|
in.get();
|
|
|
|
|
c = in.peek();
|
2010-09-06 23:29:05 +00:00
|
|
|
}
|
2010-09-06 00:17:51 +00:00
|
|
|
|
2013-05-16 19:11:44 +00:00
|
|
|
string line;
|
|
|
|
|
c = in.peek();
|
|
|
|
|
if(c == '/') // Comment, swallow line and continue
|
|
|
|
|
{
|
|
|
|
|
getline(in, line);
|
|
|
|
|
continue;
|
|
|
|
|
}
|
|
|
|
|
else if(c == '[')
|
|
|
|
|
{
|
|
|
|
|
in.get();
|
|
|
|
|
getline(in, line, ']');
|
|
|
|
|
stringstream buf(line);
|
|
|
|
|
buf >> currentbank;
|
|
|
|
|
}
|
|
|
|
|
else // Should be commands from this point on
|
2010-09-06 00:17:51 +00:00
|
|
|
{
|
2013-05-16 19:11:44 +00:00
|
|
|
getline(in, line);
|
|
|
|
|
stringstream buf;
|
|
|
|
|
buf << line;
|
|
|
|
|
|
|
|
|
|
string directive;
|
|
|
|
|
uInt16 start = 0, end = 0;
|
|
|
|
|
buf >> directive;
|
|
|
|
|
if(BSPF_startsWithIgnoreCase(directive, "ORG"))
|
2010-09-06 00:17:51 +00:00
|
|
|
{
|
2013-05-16 19:11:44 +00:00
|
|
|
// TODO - figure out what to do with this
|
|
|
|
|
buf >> hex >> start;
|
2010-09-06 00:17:51 +00:00
|
|
|
}
|
2013-05-16 19:11:44 +00:00
|
|
|
else if(BSPF_startsWithIgnoreCase(directive, "CODE"))
|
2010-09-06 00:17:51 +00:00
|
|
|
{
|
2013-05-16 19:11:44 +00:00
|
|
|
buf >> hex >> start >> hex >> end;
|
|
|
|
|
addDirective(CartDebug::CODE, start, end, currentbank);
|
2010-09-06 00:17:51 +00:00
|
|
|
}
|
2013-05-16 19:11:44 +00:00
|
|
|
else if(BSPF_startsWithIgnoreCase(directive, "GFX"))
|
2010-09-06 00:17:51 +00:00
|
|
|
{
|
2013-05-16 19:11:44 +00:00
|
|
|
buf >> hex >> start >> hex >> end;
|
|
|
|
|
addDirective(CartDebug::GFX, start, end, currentbank);
|
2010-09-06 00:17:51 +00:00
|
|
|
}
|
2013-05-16 19:11:44 +00:00
|
|
|
else if(BSPF_startsWithIgnoreCase(directive, "PGFX"))
|
2010-09-06 00:17:51 +00:00
|
|
|
{
|
2013-05-16 19:11:44 +00:00
|
|
|
buf >> hex >> start >> hex >> end;
|
|
|
|
|
addDirective(CartDebug::PGFX, start, end, currentbank);
|
|
|
|
|
}
|
|
|
|
|
else if(BSPF_startsWithIgnoreCase(directive, "DATA"))
|
|
|
|
|
{
|
|
|
|
|
buf >> hex >> start >> hex >> end;
|
|
|
|
|
addDirective(CartDebug::DATA, start, end, currentbank);
|
|
|
|
|
}
|
|
|
|
|
else if(BSPF_startsWithIgnoreCase(directive, "ROW"))
|
|
|
|
|
{
|
|
|
|
|
buf >> hex >> start;
|
|
|
|
|
buf >> hex >> end;
|
|
|
|
|
addDirective(CartDebug::ROW, start, end, currentbank);
|
2010-09-06 00:17:51 +00:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
2013-05-16 19:11:44 +00:00
|
|
|
in.close();
|
|
|
|
|
myDebugger.rom().invalidate();
|
|
|
|
|
|
|
|
|
|
return "loaded " + node.getShortPath() + " OK";
|
Many big improvements to disassembler directives. Directives are no
longer simply added to a list, but intelligently 'merged' (so that
the entire range represented by all directives contains no overlap).
This makes the disassembly a little faster, since it doesn't have to
iterate redundantly. Still TODO in this area is intelligent insertion
for the same type (ie, if inserting in between like blocks, the
blocks should coalesce, instead of being clipped and then a new range
inserted in between).
Added 'loadconfig' and 'saveconfig' debugger prompt commands, which
will eventually access Distella-like config files. No implementation
is present yet.
Added 'listconfig' debugger command, which lists all directives
currently defined by the user, as well as the directives resulting
from a disassembly of a bank (taking into account extra knowledge
that Stella has WRT cached entry points). This command can show
information for a specified bank, or all banks in the cart.
User-defined directives can now be removed; simply issue the same
command that caused an insertion (ie, attempting to insert the same
type and range will remove it instead).
Fixed bug in Distella processing of directives; similar to the
standalone Distella, directives should be processed *before* any
automatic code determination is done.
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@2121 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-08-31 16:37:27 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
2013-05-16 19:11:44 +00:00
|
|
|
string CartDebug::saveConfigFile()
|
Many big improvements to disassembler directives. Directives are no
longer simply added to a list, but intelligently 'merged' (so that
the entire range represented by all directives contains no overlap).
This makes the disassembly a little faster, since it doesn't have to
iterate redundantly. Still TODO in this area is intelligent insertion
for the same type (ie, if inserting in between like blocks, the
blocks should coalesce, instead of being clipped and then a new range
inserted in between).
Added 'loadconfig' and 'saveconfig' debugger prompt commands, which
will eventually access Distella-like config files. No implementation
is present yet.
Added 'listconfig' debugger command, which lists all directives
currently defined by the user, as well as the directives resulting
from a disassembly of a bank (taking into account extra knowledge
that Stella has WRT cached entry points). This command can show
information for a specified bank, or all banks in the cart.
User-defined directives can now be removed; simply issue the same
command that caused an insertion (ie, attempting to insert the same
type and range will remove it instead).
Fixed bug in Distella processing of directives; similar to the
standalone Distella, directives should be processed *before* any
automatic code determination is done.
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@2121 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-08-31 16:37:27 +00:00
|
|
|
{
|
2013-05-16 22:05:14 +00:00
|
|
|
if(myConsole.cartridge().bankCount() > 1)
|
2013-06-26 16:03:08 +00:00
|
|
|
return DebuggerParser::red("config file for multi-bank ROM not yet supported");
|
2013-05-16 22:05:14 +00:00
|
|
|
|
2013-05-16 19:11:44 +00:00
|
|
|
// While there are two possible locations for loading config files,
|
|
|
|
|
// the main 'config' directory is used whenever possible when saving,
|
|
|
|
|
// unless the rom-specific file already exists
|
2010-09-06 23:29:05 +00:00
|
|
|
|
2013-05-16 19:11:44 +00:00
|
|
|
FilesystemNode node;
|
2010-09-06 23:29:05 +00:00
|
|
|
|
2013-05-16 19:11:44 +00:00
|
|
|
FilesystemNode case0(myCfgFile);
|
|
|
|
|
if(myCfgFile != "" && case0.isFile() && case0.isWritable())
|
|
|
|
|
node = case0;
|
|
|
|
|
else
|
2010-09-06 23:29:05 +00:00
|
|
|
{
|
2013-05-16 19:11:44 +00:00
|
|
|
const string& propsname =
|
|
|
|
|
myConsole.properties().get(Cartridge_Name) + ".cfg";
|
|
|
|
|
|
|
|
|
|
node = FilesystemNode(myOSystem.cfgDir() + propsname);
|
2010-09-06 23:29:05 +00:00
|
|
|
}
|
|
|
|
|
|
2013-05-16 19:11:44 +00:00
|
|
|
const string& name = myConsole.properties().get(Cartridge_Name);
|
|
|
|
|
const string& md5 = myConsole.properties().get(Cartridge_MD5);
|
2010-09-06 23:29:05 +00:00
|
|
|
|
2013-05-16 19:11:44 +00:00
|
|
|
ofstream out(node.getPath().c_str());
|
|
|
|
|
if(!out.is_open())
|
|
|
|
|
return "Unable to save directives to " + node.getShortPath();
|
|
|
|
|
|
|
|
|
|
// Store all bank information
|
|
|
|
|
out << "//Stella.pro: \"" << name << "\"" << endl
|
|
|
|
|
<< "//MD5: " << md5 << endl
|
|
|
|
|
<< endl;
|
|
|
|
|
for(uInt32 b = 0; b < myConsole.cartridge().bankCount(); ++b)
|
|
|
|
|
{
|
|
|
|
|
out << "[" << b << "]" << endl;
|
|
|
|
|
getBankDirectives(out, myBankInfo[b]);
|
2010-09-06 23:29:05 +00:00
|
|
|
}
|
2013-05-16 19:11:44 +00:00
|
|
|
out.close();
|
|
|
|
|
|
|
|
|
|
return "saved " + node.getShortPath() + " OK";
|
Many big improvements to disassembler directives. Directives are no
longer simply added to a list, but intelligently 'merged' (so that
the entire range represented by all directives contains no overlap).
This makes the disassembly a little faster, since it doesn't have to
iterate redundantly. Still TODO in this area is intelligent insertion
for the same type (ie, if inserting in between like blocks, the
blocks should coalesce, instead of being clipped and then a new range
inserted in between).
Added 'loadconfig' and 'saveconfig' debugger prompt commands, which
will eventually access Distella-like config files. No implementation
is present yet.
Added 'listconfig' debugger command, which lists all directives
currently defined by the user, as well as the directives resulting
from a disassembly of a bank (taking into account extra knowledge
that Stella has WRT cached entry points). This command can show
information for a specified bank, or all banks in the cart.
User-defined directives can now be removed; simply issue the same
command that caused an insertion (ie, attempting to insert the same
type and range will remove it instead).
Fixed bug in Distella processing of directives; similar to the
standalone Distella, directives should be processed *before* any
automatic code determination is done.
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@2121 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-08-31 16:37:27 +00:00
|
|
|
}
|
|
|
|
|
|
2013-03-04 23:35:26 +00:00
|
|
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
2013-05-16 19:11:44 +00:00
|
|
|
string CartDebug::saveDisassembly()
|
2013-03-04 23:35:26 +00:00
|
|
|
{
|
|
|
|
|
if(myConsole.cartridge().bankCount() > 1)
|
2013-06-26 16:03:08 +00:00
|
|
|
return DebuggerParser::red("disassembly for multi-bank ROM not yet supported");
|
2013-03-04 23:35:26 +00:00
|
|
|
|
2013-05-20 21:53:25 +00:00
|
|
|
// Currently, the default naming/location for disassembly files is:
|
|
|
|
|
// 1) ROM dir based on properties entry name
|
2013-03-05 18:01:55 +00:00
|
|
|
|
2013-05-20 21:53:25 +00:00
|
|
|
if(myDisasmFile == "")
|
2013-05-19 20:55:25 +00:00
|
|
|
{
|
2013-05-20 21:53:25 +00:00
|
|
|
const string& propsname =
|
|
|
|
|
myConsole.properties().get(Cartridge_Name) + ".asm";
|
2013-05-19 20:55:25 +00:00
|
|
|
|
2013-06-21 12:15:32 +00:00
|
|
|
FilesystemNode case0(myOSystem.romFile().getParent().getPath() + propsname);
|
2013-05-20 21:53:25 +00:00
|
|
|
if(case0.getParent().isWritable())
|
|
|
|
|
myDisasmFile = case0.getPath();
|
|
|
|
|
else
|
2013-05-21 16:57:12 +00:00
|
|
|
return DebuggerParser::red("disassembly file not writable:\n " +
|
|
|
|
|
case0.getShortPath());
|
2013-05-19 20:55:25 +00:00
|
|
|
}
|
|
|
|
|
|
2013-05-20 21:53:25 +00:00
|
|
|
FilesystemNode node(myDisasmFile);
|
|
|
|
|
ofstream out(node.getPath().c_str());
|
|
|
|
|
if(!out.is_open())
|
|
|
|
|
return "Unable to save disassembly to " + node.getShortPath();
|
2013-03-11 19:43:19 +00:00
|
|
|
|
2013-05-20 21:53:25 +00:00
|
|
|
#define ALIGN(x) setfill(' ') << left << setw(x)
|
|
|
|
|
|
|
|
|
|
// We can't print the header to the disassembly until it's actually
|
|
|
|
|
// been processed; therefore buffer output to a string first
|
|
|
|
|
ostringstream buf;
|
2013-05-19 20:55:25 +00:00
|
|
|
buf << "\n;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\n;\n"
|
|
|
|
|
<< "; MAIN PROGRAM\n"
|
|
|
|
|
<< ";\n;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\n\n";
|
2013-03-05 18:01:55 +00:00
|
|
|
|
2013-03-04 23:35:26 +00:00
|
|
|
// Use specific settings for disassembly output
|
|
|
|
|
// This will most likely differ from what you see in the debugger
|
|
|
|
|
DiStella::Settings settings;
|
|
|
|
|
settings.gfx_format = DiStella::settings.gfx_format;
|
2013-06-17 15:57:41 +00:00
|
|
|
settings.resolve_code = true;
|
2013-03-04 23:35:26 +00:00
|
|
|
settings.show_addresses = false;
|
2013-03-10 22:12:37 +00:00
|
|
|
settings.aflag = false; // Otherwise DASM gets confused
|
2013-03-04 23:35:26 +00:00
|
|
|
settings.fflag = DiStella::settings.fflag;
|
|
|
|
|
settings.rflag = DiStella::settings.rflag;
|
2013-03-10 22:12:37 +00:00
|
|
|
settings.bwidth = 17; // default from Distella
|
2013-03-04 23:35:26 +00:00
|
|
|
|
|
|
|
|
Disassembly disasm;
|
|
|
|
|
disasm.list.reserve(2048);
|
|
|
|
|
for(int bank = 0; bank < myConsole.cartridge().bankCount(); ++bank)
|
|
|
|
|
{
|
|
|
|
|
BankInfo& info = myBankInfo[bank];
|
|
|
|
|
// Disassemble bank
|
2014-11-07 23:28:40 +00:00
|
|
|
disasm.list.clear();
|
2013-03-04 23:35:26 +00:00
|
|
|
DiStella distella(*this, disasm.list, info, settings,
|
2013-06-17 15:57:41 +00:00
|
|
|
myDisLabels, myDisDirectives, myReserved);
|
2013-03-04 23:35:26 +00:00
|
|
|
|
2013-05-19 20:55:25 +00:00
|
|
|
buf << " SEG CODE\n"
|
2013-07-27 22:28:41 +00:00
|
|
|
<< " ORG $" << Base::HEX4 << info.offset << "\n\n";
|
2013-03-04 23:35:26 +00:00
|
|
|
|
|
|
|
|
// Format in 'distella' style
|
|
|
|
|
for(uInt32 i = 0; i < disasm.list.size(); ++i)
|
|
|
|
|
{
|
|
|
|
|
const DisassemblyTag& tag = disasm.list[i];
|
|
|
|
|
|
|
|
|
|
// Add label (if any)
|
|
|
|
|
if(tag.label != "")
|
2013-05-19 20:55:25 +00:00
|
|
|
buf << ALIGN(7) << (tag.label+":") << endl;
|
|
|
|
|
buf << " ";
|
2013-03-04 23:35:26 +00:00
|
|
|
|
|
|
|
|
switch(tag.type)
|
|
|
|
|
{
|
|
|
|
|
case CartDebug::CODE:
|
|
|
|
|
{
|
2013-05-19 20:55:25 +00:00
|
|
|
buf << ALIGN(25) << tag.disasm << tag.ccount << "\n";
|
2013-03-04 23:35:26 +00:00
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
case CartDebug::NONE:
|
|
|
|
|
{
|
|
|
|
|
buf << "\n";
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
case CartDebug::ROW:
|
|
|
|
|
{
|
|
|
|
|
buf << tag.disasm << "\n";
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
case CartDebug::GFX:
|
|
|
|
|
{
|
2013-07-27 22:28:41 +00:00
|
|
|
buf << ".byte " << (settings.gfx_format == Base::F_2 ? "%" : "$")
|
2013-05-29 16:27:12 +00:00
|
|
|
<< tag.bytes << " ; |";
|
2013-03-04 23:35:26 +00:00
|
|
|
for(int i = 12; i < 20; ++i)
|
2013-03-05 18:01:55 +00:00
|
|
|
buf << ((tag.disasm[i] == '\x1e') ? "#" : " ");
|
2013-07-27 22:28:41 +00:00
|
|
|
buf << "| $" << Base::HEX4 << tag.address << " (G)\n";
|
2013-03-04 23:35:26 +00:00
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
case CartDebug::PGFX:
|
|
|
|
|
{
|
2013-07-27 22:28:41 +00:00
|
|
|
buf << ".byte " << (settings.gfx_format == Base::F_2 ? "%" : "$")
|
2013-05-29 16:27:12 +00:00
|
|
|
<< tag.bytes << " ; |";
|
2013-03-04 23:35:26 +00:00
|
|
|
for(int i = 12; i < 20; ++i)
|
2013-03-05 18:01:55 +00:00
|
|
|
buf << ((tag.disasm[i] == '\x1f') ? "*" : " ");
|
2013-07-27 22:28:41 +00:00
|
|
|
buf << "| $" << Base::HEX4 << tag.address << " (P)\n";
|
2013-03-04 23:35:26 +00:00
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
case CartDebug::DATA:
|
|
|
|
|
{
|
2013-07-27 22:28:41 +00:00
|
|
|
buf << tag.disasm.substr(0, 9) << " ; $" << Base::HEX4 << tag.address << " (D)\n";
|
2013-03-04 23:35:26 +00:00
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
default:
|
|
|
|
|
{
|
|
|
|
|
buf << "\n";
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2013-05-20 21:53:25 +00:00
|
|
|
// Some boilerplate, similar to what DiStella adds
|
|
|
|
|
time_t currtime;
|
|
|
|
|
time(&currtime);
|
2013-06-21 12:15:32 +00:00
|
|
|
out << "; Disassembly of " << myOSystem.romFile().getShortPath() << "\n"
|
2013-05-20 21:53:25 +00:00
|
|
|
<< "; Disassembled " << ctime(&currtime)
|
|
|
|
|
<< "; Using Stella " << STELLA_VERSION << "\n;\n"
|
|
|
|
|
<< "; ROM properties name : " << myConsole.properties().get(Cartridge_Name) << "\n"
|
|
|
|
|
<< "; ROM properties MD5 : " << myConsole.properties().get(Cartridge_MD5) << "\n"
|
|
|
|
|
<< "; Bankswitch type : " << myConsole.cartridge().about() << "\n;\n"
|
2013-05-29 16:27:12 +00:00
|
|
|
<< "; Legend: * = CODE not yet run (tentative code)\n"
|
2013-05-20 21:53:25 +00:00
|
|
|
<< "; D = DATA directive (referenced in some way)\n"
|
|
|
|
|
<< "; G = GFX directive, shown as '#' (stored in player, missile, ball)\n"
|
|
|
|
|
<< "; P = PGFX directive, shown as '*' (stored in playfield)\n\n"
|
|
|
|
|
<< " processor 6502\n\n";
|
2013-03-04 23:35:26 +00:00
|
|
|
|
2013-05-21 16:57:12 +00:00
|
|
|
bool addrUsed = false;
|
2013-05-20 21:53:25 +00:00
|
|
|
for(uInt16 addr = 0x00; addr <= 0x0F; ++addr)
|
2013-05-21 16:57:12 +00:00
|
|
|
addrUsed = addrUsed || myReserved.TIARead[addr];
|
2013-05-20 21:53:25 +00:00
|
|
|
for(uInt16 addr = 0x00; addr <= 0x3F; ++addr)
|
2013-05-21 16:57:12 +00:00
|
|
|
addrUsed = addrUsed || myReserved.TIAWrite[addr];
|
2013-05-20 21:53:25 +00:00
|
|
|
for(uInt16 addr = 0x00; addr <= 0x17; ++addr)
|
2013-05-21 16:57:12 +00:00
|
|
|
addrUsed = addrUsed || myReserved.IOReadWrite[addr];
|
|
|
|
|
if(addrUsed)
|
|
|
|
|
{
|
|
|
|
|
out << ";;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\n"
|
|
|
|
|
<< "; TIA AND IO CONSTANTS\n"
|
|
|
|
|
<< ";;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\n\n";
|
|
|
|
|
for(uInt16 addr = 0x00; addr <= 0x0F; ++addr)
|
|
|
|
|
if(myReserved.TIARead[addr] && ourTIAMnemonicR[addr])
|
|
|
|
|
out << ALIGN(6) << ourTIAMnemonicR[addr] << " = $"
|
2013-07-27 22:28:41 +00:00
|
|
|
<< Base::HEX2 << right << addr << " ; (R)\n";
|
2013-05-21 16:57:12 +00:00
|
|
|
for(uInt16 addr = 0x00; addr <= 0x3F; ++addr)
|
|
|
|
|
if(myReserved.TIAWrite[addr] && ourTIAMnemonicW[addr])
|
|
|
|
|
out << ALIGN(6) << ourTIAMnemonicW[addr] << " = $"
|
2013-07-27 22:28:41 +00:00
|
|
|
<< Base::HEX2 << right << addr << " ; (W)\n";
|
2013-05-21 16:57:12 +00:00
|
|
|
for(uInt16 addr = 0x00; addr <= 0x17; ++addr)
|
|
|
|
|
if(myReserved.IOReadWrite[addr] && ourIOMnemonic[addr])
|
|
|
|
|
out << ALIGN(6) << ourIOMnemonic[addr] << " = $"
|
2013-07-27 22:28:41 +00:00
|
|
|
<< Base::HEX4 << right << (addr+0x280) << "\n";
|
2013-05-21 16:57:12 +00:00
|
|
|
}
|
2013-05-20 21:53:25 +00:00
|
|
|
|
2013-05-21 16:57:12 +00:00
|
|
|
addrUsed = false;
|
2013-05-20 21:53:25 +00:00
|
|
|
for(uInt16 addr = 0x80; addr <= 0xFF; ++addr)
|
2013-05-21 16:57:12 +00:00
|
|
|
addrUsed = addrUsed || myReserved.ZPRAM[addr-0x80];
|
|
|
|
|
if(addrUsed)
|
2013-05-20 21:53:25 +00:00
|
|
|
{
|
2013-05-21 16:57:12 +00:00
|
|
|
out << "\n;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\n"
|
|
|
|
|
<< "; RIOT RAM (zero-page)\n"
|
|
|
|
|
<< ";;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\n\n";
|
|
|
|
|
for(uInt16 addr = 0x80; addr <= 0xFF; ++addr)
|
2013-05-20 21:53:25 +00:00
|
|
|
{
|
2013-05-21 16:57:12 +00:00
|
|
|
if(myReserved.ZPRAM[addr-0x80] &&
|
|
|
|
|
myUserLabels.find(addr) == myUserLabels.end())
|
|
|
|
|
{
|
|
|
|
|
out << ALIGN(6) << ourZPMnemonic[addr-0x80] << " = $"
|
2013-07-27 22:28:41 +00:00
|
|
|
<< Base::HEX2 << right << (addr) << "\n";
|
2013-05-21 16:57:12 +00:00
|
|
|
}
|
2013-05-20 21:53:25 +00:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if(myReserved.Label.size() > 0)
|
|
|
|
|
{
|
|
|
|
|
out << "\n;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\n"
|
|
|
|
|
<< "; NON LOCATABLE\n"
|
|
|
|
|
<< ";;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\n\n";
|
2014-11-02 23:40:20 +00:00
|
|
|
for(const auto& iter: myReserved.Label)
|
|
|
|
|
out << ALIGN(10) << iter.second << " = $" << iter.first << "\n";
|
2013-05-20 21:53:25 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if(myUserLabels.size() > 0)
|
|
|
|
|
{
|
|
|
|
|
out << "\n;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\n"
|
|
|
|
|
<< "; USER DEFINED\n"
|
|
|
|
|
<< ";;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\n\n";
|
|
|
|
|
int max_len = 0;
|
2014-11-02 23:40:20 +00:00
|
|
|
for(const auto& iter: myUserLabels)
|
|
|
|
|
max_len = BSPF_max(max_len, (int)iter.second.size());
|
|
|
|
|
for(const auto& iter: myUserLabels)
|
|
|
|
|
out << ALIGN(max_len) << iter.second << " = $" << iter.first << "\n";
|
2013-05-20 21:53:25 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// And finally, output the disassembly
|
|
|
|
|
out << buf.str();
|
|
|
|
|
|
|
|
|
|
out.close();
|
|
|
|
|
|
|
|
|
|
return "saved " + node.getShortPath() + " OK";
|
2013-03-04 23:35:26 +00:00
|
|
|
}
|
|
|
|
|
|
2013-05-16 19:11:44 +00:00
|
|
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
|
|
|
|
string CartDebug::saveRom()
|
|
|
|
|
{
|
|
|
|
|
const string& path = "~" BSPF_PATH_SEPARATOR +
|
|
|
|
|
myConsole.properties().get(Cartridge_Name) + ".a26";
|
|
|
|
|
|
|
|
|
|
FilesystemNode node(path);
|
|
|
|
|
ofstream out(node.getPath().c_str(), ios::out | ios::binary);
|
|
|
|
|
if(out.is_open() && myConsole.cartridge().save(out))
|
|
|
|
|
return "saved ROM as " + node.getShortPath();
|
|
|
|
|
else
|
|
|
|
|
return DebuggerParser::red("failed to save ROM");
|
|
|
|
|
}
|
|
|
|
|
|
Many big improvements to disassembler directives. Directives are no
longer simply added to a list, but intelligently 'merged' (so that
the entire range represented by all directives contains no overlap).
This makes the disassembly a little faster, since it doesn't have to
iterate redundantly. Still TODO in this area is intelligent insertion
for the same type (ie, if inserting in between like blocks, the
blocks should coalesce, instead of being clipped and then a new range
inserted in between).
Added 'loadconfig' and 'saveconfig' debugger prompt commands, which
will eventually access Distella-like config files. No implementation
is present yet.
Added 'listconfig' debugger command, which lists all directives
currently defined by the user, as well as the directives resulting
from a disassembly of a bank (taking into account extra knowledge
that Stella has WRT cached entry points). This command can show
information for a specified bank, or all banks in the cart.
User-defined directives can now be removed; simply issue the same
command that caused an insertion (ie, attempting to insert the same
type and range will remove it instead).
Fixed bug in Distella processing of directives; similar to the
standalone Distella, directives should be processed *before* any
automatic code determination is done.
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@2121 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-08-31 16:37:27 +00:00
|
|
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
|
|
|
|
string CartDebug::listConfig(int bank)
|
|
|
|
|
{
|
2013-05-16 22:05:14 +00:00
|
|
|
if(myConsole.cartridge().bankCount() > 1)
|
2013-06-26 16:03:08 +00:00
|
|
|
return DebuggerParser::red("config file for multi-bank ROM not yet supported");
|
2013-05-16 22:05:14 +00:00
|
|
|
|
Many big improvements to disassembler directives. Directives are no
longer simply added to a list, but intelligently 'merged' (so that
the entire range represented by all directives contains no overlap).
This makes the disassembly a little faster, since it doesn't have to
iterate redundantly. Still TODO in this area is intelligent insertion
for the same type (ie, if inserting in between like blocks, the
blocks should coalesce, instead of being clipped and then a new range
inserted in between).
Added 'loadconfig' and 'saveconfig' debugger prompt commands, which
will eventually access Distella-like config files. No implementation
is present yet.
Added 'listconfig' debugger command, which lists all directives
currently defined by the user, as well as the directives resulting
from a disassembly of a bank (taking into account extra knowledge
that Stella has WRT cached entry points). This command can show
information for a specified bank, or all banks in the cart.
User-defined directives can now be removed; simply issue the same
command that caused an insertion (ie, attempting to insert the same
type and range will remove it instead).
Fixed bug in Distella processing of directives; similar to the
standalone Distella, directives should be processed *before* any
automatic code determination is done.
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@2121 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-08-31 16:37:27 +00:00
|
|
|
uInt32 startbank = 0, endbank = bankCount();
|
|
|
|
|
if(bank >= 0 && bank < bankCount())
|
|
|
|
|
{
|
|
|
|
|
startbank = bank;
|
|
|
|
|
endbank = startbank + 1;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
ostringstream buf;
|
|
|
|
|
buf << "(items marked '*' are user-defined)" << endl;
|
|
|
|
|
for(uInt32 b = startbank; b < endbank; ++b)
|
|
|
|
|
{
|
|
|
|
|
BankInfo& info = myBankInfo[b];
|
|
|
|
|
buf << "[" << b << "]" << endl;
|
2014-11-02 23:40:20 +00:00
|
|
|
for(const auto& i: info.directiveList)
|
Many big improvements to disassembler directives. Directives are no
longer simply added to a list, but intelligently 'merged' (so that
the entire range represented by all directives contains no overlap).
This makes the disassembly a little faster, since it doesn't have to
iterate redundantly. Still TODO in this area is intelligent insertion
for the same type (ie, if inserting in between like blocks, the
blocks should coalesce, instead of being clipped and then a new range
inserted in between).
Added 'loadconfig' and 'saveconfig' debugger prompt commands, which
will eventually access Distella-like config files. No implementation
is present yet.
Added 'listconfig' debugger command, which lists all directives
currently defined by the user, as well as the directives resulting
from a disassembly of a bank (taking into account extra knowledge
that Stella has WRT cached entry points). This command can show
information for a specified bank, or all banks in the cart.
User-defined directives can now be removed; simply issue the same
command that caused an insertion (ie, attempting to insert the same
type and range will remove it instead).
Fixed bug in Distella processing of directives; similar to the
standalone Distella, directives should be processed *before* any
automatic code determination is done.
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@2121 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-08-31 16:37:27 +00:00
|
|
|
{
|
2014-11-02 23:40:20 +00:00
|
|
|
if(i.type != CartDebug::NONE)
|
2010-09-06 23:29:05 +00:00
|
|
|
{
|
|
|
|
|
buf << "(*) ";
|
2014-11-02 23:40:20 +00:00
|
|
|
disasmTypeAsString(buf, i.type);
|
|
|
|
|
buf << " " << Base::HEX4 << i.start << " " << Base::HEX4 << i.end << endl;
|
2010-09-06 23:29:05 +00:00
|
|
|
}
|
Many big improvements to disassembler directives. Directives are no
longer simply added to a list, but intelligently 'merged' (so that
the entire range represented by all directives contains no overlap).
This makes the disassembly a little faster, since it doesn't have to
iterate redundantly. Still TODO in this area is intelligent insertion
for the same type (ie, if inserting in between like blocks, the
blocks should coalesce, instead of being clipped and then a new range
inserted in between).
Added 'loadconfig' and 'saveconfig' debugger prompt commands, which
will eventually access Distella-like config files. No implementation
is present yet.
Added 'listconfig' debugger command, which lists all directives
currently defined by the user, as well as the directives resulting
from a disassembly of a bank (taking into account extra knowledge
that Stella has WRT cached entry points). This command can show
information for a specified bank, or all banks in the cart.
User-defined directives can now be removed; simply issue the same
command that caused an insertion (ie, attempting to insert the same
type and range will remove it instead).
Fixed bug in Distella processing of directives; similar to the
standalone Distella, directives should be processed *before* any
automatic code determination is done.
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@2121 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-08-31 16:37:27 +00:00
|
|
|
}
|
|
|
|
|
getBankDirectives(buf, info);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return buf.str();
|
|
|
|
|
}
|
|
|
|
|
|
2010-09-07 22:03:20 +00:00
|
|
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
|
|
|
|
string CartDebug::clearConfig(int bank)
|
|
|
|
|
{
|
|
|
|
|
uInt32 startbank = 0, endbank = bankCount();
|
|
|
|
|
if(bank >= 0 && bank < bankCount())
|
|
|
|
|
{
|
|
|
|
|
startbank = bank;
|
|
|
|
|
endbank = startbank + 1;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
uInt32 count = 0;
|
|
|
|
|
for(uInt32 b = startbank; b < endbank; ++b)
|
|
|
|
|
{
|
|
|
|
|
count += myBankInfo[b].directiveList.size();
|
|
|
|
|
myBankInfo[b].directiveList.clear();
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
ostringstream buf;
|
|
|
|
|
if(count > 0)
|
|
|
|
|
buf << "removed " << dec << count << " directives from "
|
|
|
|
|
<< dec << (endbank - startbank) << " banks";
|
|
|
|
|
else
|
|
|
|
|
buf << "no directives present";
|
|
|
|
|
return buf.str();
|
|
|
|
|
}
|
|
|
|
|
|
OK, this is the first pass at a huge reorganization of the debugger
classes. First off, the distella code has been integrated into a
DiStella class. This code isn't yet tied to the debugger, but it does
at least compile and generate valid output.
The RamDebug class has been replaced by a CartDebug class, which
takes responsibility for the previous RamDebug stuff as well as
things related to Cart address space (read from write ports,
disassembly, etc).
Fixed E7 bankswitching when reading from the write port in the upper
256byte area.
Fixed 'read from write port functionality' in general for all carts
that supported it previously. Basically, if _rwport is enabled, the
address is checked to be an actual read (vs. one that's part of a
normal write cycle), *and* it's actually an illegal access (each
cart/bankswitch type now provides a hint to indicate this condition).
Still TODO is clean up the rework, properly integrate DiStella, and
fix labels and defines (which seem to be completely broken).
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1922 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-01-17 16:48:45 +00:00
|
|
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
2010-04-08 18:21:00 +00:00
|
|
|
void CartDebug::getCompletions(const char* in, StringList& completions) const
|
OK, this is the first pass at a huge reorganization of the debugger
classes. First off, the distella code has been integrated into a
DiStella class. This code isn't yet tied to the debugger, but it does
at least compile and generate valid output.
The RamDebug class has been replaced by a CartDebug class, which
takes responsibility for the previous RamDebug stuff as well as
things related to Cart address space (read from write ports,
disassembly, etc).
Fixed E7 bankswitching when reading from the write port in the upper
256byte area.
Fixed 'read from write port functionality' in general for all carts
that supported it previously. Basically, if _rwport is enabled, the
address is checked to be an actual read (vs. one that's part of a
normal write cycle), *and* it's actually an illegal access (each
cart/bankswitch type now provides a hint to indicate this condition).
Still TODO is clean up the rework, properly integrate DiStella, and
fix labels and defines (which seem to be completely broken).
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1922 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-01-17 16:48:45 +00:00
|
|
|
{
|
2010-04-08 18:21:00 +00:00
|
|
|
// First scan system equates
|
2013-05-19 20:55:25 +00:00
|
|
|
for(uInt16 addr = 0x00; addr <= 0x0F; ++addr)
|
2013-05-20 16:48:31 +00:00
|
|
|
if(ourTIAMnemonicR[addr] && BSPF_startsWithIgnoreCase(ourTIAMnemonicR[addr], in))
|
2010-04-08 18:21:00 +00:00
|
|
|
completions.push_back(ourTIAMnemonicR[addr]);
|
2013-05-19 20:55:25 +00:00
|
|
|
for(uInt16 addr = 0x00; addr <= 0x3F; ++addr)
|
2013-05-20 16:48:31 +00:00
|
|
|
if(ourTIAMnemonicW[addr] && BSPF_startsWithIgnoreCase(ourTIAMnemonicW[addr], in))
|
2010-04-08 18:21:00 +00:00
|
|
|
completions.push_back(ourTIAMnemonicW[addr]);
|
|
|
|
|
for(uInt16 addr = 0; addr <= 0x297-0x280; ++addr)
|
2013-05-20 16:48:31 +00:00
|
|
|
if(ourIOMnemonic[addr] && BSPF_startsWithIgnoreCase(ourIOMnemonic[addr], in))
|
2010-04-08 18:21:00 +00:00
|
|
|
completions.push_back(ourIOMnemonic[addr]);
|
2013-05-20 16:48:31 +00:00
|
|
|
for(uInt16 addr = 0; addr <= 0x7F; ++addr)
|
|
|
|
|
if(ourZPMnemonic[addr] && BSPF_startsWithIgnoreCase(ourZPMnemonic[addr], in))
|
|
|
|
|
completions.push_back(ourZPMnemonic[addr]);
|
OK, this is the first pass at a huge reorganization of the debugger
classes. First off, the distella code has been integrated into a
DiStella class. This code isn't yet tied to the debugger, but it does
at least compile and generate valid output.
The RamDebug class has been replaced by a CartDebug class, which
takes responsibility for the previous RamDebug stuff as well as
things related to Cart address space (read from write ports,
disassembly, etc).
Fixed E7 bankswitching when reading from the write port in the upper
256byte area.
Fixed 'read from write port functionality' in general for all carts
that supported it previously. Basically, if _rwport is enabled, the
address is checked to be an actual read (vs. one that's part of a
normal write cycle), *and* it's actually an illegal access (each
cart/bankswitch type now provides a hint to indicate this condition).
Still TODO is clean up the rework, properly integrate DiStella, and
fix labels and defines (which seem to be completely broken).
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1922 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-01-17 16:48:45 +00:00
|
|
|
|
2010-04-08 18:21:00 +00:00
|
|
|
// Now scan user-defined labels
|
|
|
|
|
LabelToAddr::const_iterator iter;
|
2014-11-02 23:40:20 +00:00
|
|
|
for(const auto& iter: myUserAddresses)
|
OK, this is the first pass at a huge reorganization of the debugger
classes. First off, the distella code has been integrated into a
DiStella class. This code isn't yet tied to the debugger, but it does
at least compile and generate valid output.
The RamDebug class has been replaced by a CartDebug class, which
takes responsibility for the previous RamDebug stuff as well as
things related to Cart address space (read from write ports,
disassembly, etc).
Fixed E7 bankswitching when reading from the write port in the upper
256byte area.
Fixed 'read from write port functionality' in general for all carts
that supported it previously. Basically, if _rwport is enabled, the
address is checked to be an actual read (vs. one that's part of a
normal write cycle), *and* it's actually an illegal access (each
cart/bankswitch type now provides a hint to indicate this condition).
Still TODO is clean up the rework, properly integrate DiStella, and
fix labels and defines (which seem to be completely broken).
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1922 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-01-17 16:48:45 +00:00
|
|
|
{
|
2014-11-02 23:40:20 +00:00
|
|
|
const char* l = iter.first.c_str();
|
Many big improvements to disassembler directives. Directives are no
longer simply added to a list, but intelligently 'merged' (so that
the entire range represented by all directives contains no overlap).
This makes the disassembly a little faster, since it doesn't have to
iterate redundantly. Still TODO in this area is intelligent insertion
for the same type (ie, if inserting in between like blocks, the
blocks should coalesce, instead of being clipped and then a new range
inserted in between).
Added 'loadconfig' and 'saveconfig' debugger prompt commands, which
will eventually access Distella-like config files. No implementation
is present yet.
Added 'listconfig' debugger command, which lists all directives
currently defined by the user, as well as the directives resulting
from a disassembly of a bank (taking into account extra knowledge
that Stella has WRT cached entry points). This command can show
information for a specified bank, or all banks in the cart.
User-defined directives can now be removed; simply issue the same
command that caused an insertion (ie, attempting to insert the same
type and range will remove it instead).
Fixed bug in Distella processing of directives; similar to the
standalone Distella, directives should be processed *before* any
automatic code determination is done.
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@2121 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-08-31 16:37:27 +00:00
|
|
|
if(BSPF_startsWithIgnoreCase(l, in))
|
2010-04-08 18:21:00 +00:00
|
|
|
completions.push_back(l);
|
OK, this is the first pass at a huge reorganization of the debugger
classes. First off, the distella code has been integrated into a
DiStella class. This code isn't yet tied to the debugger, but it does
at least compile and generate valid output.
The RamDebug class has been replaced by a CartDebug class, which
takes responsibility for the previous RamDebug stuff as well as
things related to Cart address space (read from write ports,
disassembly, etc).
Fixed E7 bankswitching when reading from the write port in the upper
256byte area.
Fixed 'read from write port functionality' in general for all carts
that supported it previously. Basically, if _rwport is enabled, the
address is checked to be an actual read (vs. one that's part of a
normal write cycle), *and* it's actually an illegal access (each
cart/bankswitch type now provides a hint to indicate this condition).
Still TODO is clean up the rework, properly integrate DiStella, and
fix labels and defines (which seem to be completely broken).
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1922 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-01-17 16:48:45 +00:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2010-02-28 17:12:16 +00:00
|
|
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
|
|
|
|
CartDebug::AddrType CartDebug::addressType(uInt16 addr) const
|
|
|
|
|
{
|
|
|
|
|
// Determine the type of address to access the correct list
|
|
|
|
|
// These addresses were based on (and checked against) Kroko's 2600 memory
|
|
|
|
|
// map, found at http://www.qotile.net/minidig/docs/2600_mem_map.txt
|
|
|
|
|
if(addr % 0x2000 < 0x1000)
|
|
|
|
|
{
|
2013-05-19 20:55:25 +00:00
|
|
|
if((addr & 0x00ff) < 0x80)
|
|
|
|
|
return ADDR_TIA;
|
2010-02-28 17:12:16 +00:00
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
switch(addr & 0x0f00)
|
|
|
|
|
{
|
2013-05-20 21:53:25 +00:00
|
|
|
case 0x000: case 0x100: case 0x400: case 0x500:
|
|
|
|
|
case 0x800: case 0x900: case 0xc00: case 0xd00:
|
2013-05-19 20:55:25 +00:00
|
|
|
return ADDR_ZPRAM;
|
2013-05-20 21:53:25 +00:00
|
|
|
case 0x200: case 0x300: case 0x600: case 0x700:
|
|
|
|
|
case 0xa00: case 0xb00: case 0xe00: case 0xf00:
|
2013-05-19 20:55:25 +00:00
|
|
|
return ADDR_IO;
|
2010-02-28 17:12:16 +00:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
2013-05-19 20:55:25 +00:00
|
|
|
return ADDR_ROM;
|
2010-02-28 17:12:16 +00:00
|
|
|
}
|
|
|
|
|
|
Many big improvements to disassembler directives. Directives are no
longer simply added to a list, but intelligently 'merged' (so that
the entire range represented by all directives contains no overlap).
This makes the disassembly a little faster, since it doesn't have to
iterate redundantly. Still TODO in this area is intelligent insertion
for the same type (ie, if inserting in between like blocks, the
blocks should coalesce, instead of being clipped and then a new range
inserted in between).
Added 'loadconfig' and 'saveconfig' debugger prompt commands, which
will eventually access Distella-like config files. No implementation
is present yet.
Added 'listconfig' debugger command, which lists all directives
currently defined by the user, as well as the directives resulting
from a disassembly of a bank (taking into account extra knowledge
that Stella has WRT cached entry points). This command can show
information for a specified bank, or all banks in the cart.
User-defined directives can now be removed; simply issue the same
command that caused an insertion (ie, attempting to insert the same
type and range will remove it instead).
Fixed bug in Distella processing of directives; similar to the
standalone Distella, directives should be processed *before* any
automatic code determination is done.
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@2121 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-08-31 16:37:27 +00:00
|
|
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
2010-09-06 23:29:05 +00:00
|
|
|
void CartDebug::getBankDirectives(ostream& buf, BankInfo& info) const
|
Many big improvements to disassembler directives. Directives are no
longer simply added to a list, but intelligently 'merged' (so that
the entire range represented by all directives contains no overlap).
This makes the disassembly a little faster, since it doesn't have to
iterate redundantly. Still TODO in this area is intelligent insertion
for the same type (ie, if inserting in between like blocks, the
blocks should coalesce, instead of being clipped and then a new range
inserted in between).
Added 'loadconfig' and 'saveconfig' debugger prompt commands, which
will eventually access Distella-like config files. No implementation
is present yet.
Added 'listconfig' debugger command, which lists all directives
currently defined by the user, as well as the directives resulting
from a disassembly of a bank (taking into account extra knowledge
that Stella has WRT cached entry points). This command can show
information for a specified bank, or all banks in the cart.
User-defined directives can now be removed; simply issue the same
command that caused an insertion (ie, attempting to insert the same
type and range will remove it instead).
Fixed bug in Distella processing of directives; similar to the
standalone Distella, directives should be processed *before* any
automatic code determination is done.
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@2121 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-08-31 16:37:27 +00:00
|
|
|
{
|
2010-09-01 16:44:31 +00:00
|
|
|
// Start with the offset for this bank
|
2013-07-27 22:28:41 +00:00
|
|
|
buf << "ORG " << Base::HEX4 << info.offset << endl;
|
2010-09-01 16:44:31 +00:00
|
|
|
|
2013-05-16 22:05:14 +00:00
|
|
|
// Now consider each byte
|
|
|
|
|
uInt32 prev = info.offset, addr = prev + 1;
|
|
|
|
|
DisasmType prevType = disasmTypeAbsolute(mySystem.getAccessFlags(prev));
|
|
|
|
|
for( ; addr < info.offset + info.size; ++addr)
|
Many big improvements to disassembler directives. Directives are no
longer simply added to a list, but intelligently 'merged' (so that
the entire range represented by all directives contains no overlap).
This makes the disassembly a little faster, since it doesn't have to
iterate redundantly. Still TODO in this area is intelligent insertion
for the same type (ie, if inserting in between like blocks, the
blocks should coalesce, instead of being clipped and then a new range
inserted in between).
Added 'loadconfig' and 'saveconfig' debugger prompt commands, which
will eventually access Distella-like config files. No implementation
is present yet.
Added 'listconfig' debugger command, which lists all directives
currently defined by the user, as well as the directives resulting
from a disassembly of a bank (taking into account extra knowledge
that Stella has WRT cached entry points). This command can show
information for a specified bank, or all banks in the cart.
User-defined directives can now be removed; simply issue the same
command that caused an insertion (ie, attempting to insert the same
type and range will remove it instead).
Fixed bug in Distella processing of directives; similar to the
standalone Distella, directives should be processed *before* any
automatic code determination is done.
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@2121 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-08-31 16:37:27 +00:00
|
|
|
{
|
2013-05-16 22:05:14 +00:00
|
|
|
DisasmType currType = disasmTypeAbsolute(mySystem.getAccessFlags(addr));
|
Many big improvements to disassembler directives. Directives are no
longer simply added to a list, but intelligently 'merged' (so that
the entire range represented by all directives contains no overlap).
This makes the disassembly a little faster, since it doesn't have to
iterate redundantly. Still TODO in this area is intelligent insertion
for the same type (ie, if inserting in between like blocks, the
blocks should coalesce, instead of being clipped and then a new range
inserted in between).
Added 'loadconfig' and 'saveconfig' debugger prompt commands, which
will eventually access Distella-like config files. No implementation
is present yet.
Added 'listconfig' debugger command, which lists all directives
currently defined by the user, as well as the directives resulting
from a disassembly of a bank (taking into account extra knowledge
that Stella has WRT cached entry points). This command can show
information for a specified bank, or all banks in the cart.
User-defined directives can now be removed; simply issue the same
command that caused an insertion (ie, attempting to insert the same
type and range will remove it instead).
Fixed bug in Distella processing of directives; similar to the
standalone Distella, directives should be processed *before* any
automatic code determination is done.
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@2121 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-08-31 16:37:27 +00:00
|
|
|
|
2013-05-16 22:05:14 +00:00
|
|
|
// Have we changed to a new type?
|
|
|
|
|
if(currType != prevType)
|
Many big improvements to disassembler directives. Directives are no
longer simply added to a list, but intelligently 'merged' (so that
the entire range represented by all directives contains no overlap).
This makes the disassembly a little faster, since it doesn't have to
iterate redundantly. Still TODO in this area is intelligent insertion
for the same type (ie, if inserting in between like blocks, the
blocks should coalesce, instead of being clipped and then a new range
inserted in between).
Added 'loadconfig' and 'saveconfig' debugger prompt commands, which
will eventually access Distella-like config files. No implementation
is present yet.
Added 'listconfig' debugger command, which lists all directives
currently defined by the user, as well as the directives resulting
from a disassembly of a bank (taking into account extra knowledge
that Stella has WRT cached entry points). This command can show
information for a specified bank, or all banks in the cart.
User-defined directives can now be removed; simply issue the same
command that caused an insertion (ie, attempting to insert the same
type and range will remove it instead).
Fixed bug in Distella processing of directives; similar to the
standalone Distella, directives should be processed *before* any
automatic code determination is done.
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@2121 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-08-31 16:37:27 +00:00
|
|
|
{
|
2013-05-16 22:05:14 +00:00
|
|
|
disasmTypeAsString(buf, prevType);
|
2013-07-27 22:28:41 +00:00
|
|
|
buf << " " << Base::HEX4 << prev << " " << Base::HEX4 << (addr-1) << endl;
|
Many big improvements to disassembler directives. Directives are no
longer simply added to a list, but intelligently 'merged' (so that
the entire range represented by all directives contains no overlap).
This makes the disassembly a little faster, since it doesn't have to
iterate redundantly. Still TODO in this area is intelligent insertion
for the same type (ie, if inserting in between like blocks, the
blocks should coalesce, instead of being clipped and then a new range
inserted in between).
Added 'loadconfig' and 'saveconfig' debugger prompt commands, which
will eventually access Distella-like config files. No implementation
is present yet.
Added 'listconfig' debugger command, which lists all directives
currently defined by the user, as well as the directives resulting
from a disassembly of a bank (taking into account extra knowledge
that Stella has WRT cached entry points). This command can show
information for a specified bank, or all banks in the cart.
User-defined directives can now be removed; simply issue the same
command that caused an insertion (ie, attempting to insert the same
type and range will remove it instead).
Fixed bug in Distella processing of directives; similar to the
standalone Distella, directives should be processed *before* any
automatic code determination is done.
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@2121 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-08-31 16:37:27 +00:00
|
|
|
|
2013-05-16 22:05:14 +00:00
|
|
|
prev = addr;
|
|
|
|
|
prevType = currType;
|
Many big improvements to disassembler directives. Directives are no
longer simply added to a list, but intelligently 'merged' (so that
the entire range represented by all directives contains no overlap).
This makes the disassembly a little faster, since it doesn't have to
iterate redundantly. Still TODO in this area is intelligent insertion
for the same type (ie, if inserting in between like blocks, the
blocks should coalesce, instead of being clipped and then a new range
inserted in between).
Added 'loadconfig' and 'saveconfig' debugger prompt commands, which
will eventually access Distella-like config files. No implementation
is present yet.
Added 'listconfig' debugger command, which lists all directives
currently defined by the user, as well as the directives resulting
from a disassembly of a bank (taking into account extra knowledge
that Stella has WRT cached entry points). This command can show
information for a specified bank, or all banks in the cart.
User-defined directives can now be removed; simply issue the same
command that caused an insertion (ie, attempting to insert the same
type and range will remove it instead).
Fixed bug in Distella processing of directives; similar to the
standalone Distella, directives should be processed *before* any
automatic code determination is done.
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@2121 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-08-31 16:37:27 +00:00
|
|
|
}
|
|
|
|
|
}
|
2013-05-16 22:05:14 +00:00
|
|
|
|
Many big improvements to disassembler directives. Directives are no
longer simply added to a list, but intelligently 'merged' (so that
the entire range represented by all directives contains no overlap).
This makes the disassembly a little faster, since it doesn't have to
iterate redundantly. Still TODO in this area is intelligent insertion
for the same type (ie, if inserting in between like blocks, the
blocks should coalesce, instead of being clipped and then a new range
inserted in between).
Added 'loadconfig' and 'saveconfig' debugger prompt commands, which
will eventually access Distella-like config files. No implementation
is present yet.
Added 'listconfig' debugger command, which lists all directives
currently defined by the user, as well as the directives resulting
from a disassembly of a bank (taking into account extra knowledge
that Stella has WRT cached entry points). This command can show
information for a specified bank, or all banks in the cart.
User-defined directives can now be removed; simply issue the same
command that caused an insertion (ie, attempting to insert the same
type and range will remove it instead).
Fixed bug in Distella processing of directives; similar to the
standalone Distella, directives should be processed *before* any
automatic code determination is done.
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@2121 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-08-31 16:37:27 +00:00
|
|
|
// Grab the last directive, making sure it accounts for all remaining space
|
2013-05-16 22:05:14 +00:00
|
|
|
if(prev != addr)
|
|
|
|
|
{
|
|
|
|
|
disasmTypeAsString(buf, prevType);
|
2013-07-27 22:28:41 +00:00
|
|
|
buf << " " << Base::HEX4 << prev << " " << Base::HEX4 << (addr-1) << endl;
|
2013-05-16 22:05:14 +00:00
|
|
|
}
|
2010-09-06 23:29:05 +00:00
|
|
|
}
|
|
|
|
|
|
2010-11-07 18:10:58 +00:00
|
|
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
|
|
|
|
void CartDebug::addressTypeAsString(ostream& buf, uInt16 addr) const
|
|
|
|
|
{
|
|
|
|
|
if(!(addr & 0x1000))
|
|
|
|
|
{
|
|
|
|
|
buf << DebuggerParser::red("type only defined for cart address space");
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
uInt8 directive = myDisDirectives[addr & 0xFFF] & 0xFC,
|
2010-11-12 18:54:08 +00:00
|
|
|
debugger = myDebugger.getAccessFlags(addr) & 0xFC,
|
2010-11-07 18:10:58 +00:00
|
|
|
label = myDisLabels[addr & 0xFFF];
|
|
|
|
|
|
2013-07-27 22:28:41 +00:00
|
|
|
buf << endl << "directive: " << Base::toString(directive, Base::F_2_8) << " ";
|
2010-11-07 18:10:58 +00:00
|
|
|
disasmTypeAsString(buf, directive);
|
2013-07-27 22:28:41 +00:00
|
|
|
buf << endl << "emulation: " << Base::toString(debugger, Base::F_2_8) << " ";
|
2010-11-07 18:10:58 +00:00
|
|
|
disasmTypeAsString(buf, debugger);
|
2013-07-27 22:28:41 +00:00
|
|
|
buf << endl << "tentative: " << Base::toString(label, Base::F_2_8) << " ";
|
2010-11-07 18:10:58 +00:00
|
|
|
disasmTypeAsString(buf, label);
|
|
|
|
|
buf << endl;
|
|
|
|
|
}
|
|
|
|
|
|
2013-05-16 22:05:14 +00:00
|
|
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
|
|
|
|
CartDebug::DisasmType CartDebug::disasmTypeAbsolute(uInt8 flags) const
|
|
|
|
|
{
|
|
|
|
|
if(flags & CartDebug::CODE)
|
|
|
|
|
return CartDebug::CODE;
|
2013-05-29 16:27:12 +00:00
|
|
|
else if(flags & CartDebug::TCODE)
|
2013-05-17 01:05:50 +00:00
|
|
|
return CartDebug::CODE; // TODO - should this be separate??
|
2013-05-16 22:05:14 +00:00
|
|
|
else if(flags & CartDebug::GFX)
|
|
|
|
|
return CartDebug::GFX;
|
|
|
|
|
else if(flags & CartDebug::PGFX)
|
|
|
|
|
return CartDebug::PGFX;
|
|
|
|
|
else if(flags & CartDebug::DATA)
|
|
|
|
|
return CartDebug::DATA;
|
|
|
|
|
else if(flags & CartDebug::ROW)
|
|
|
|
|
return CartDebug::ROW;
|
|
|
|
|
else
|
|
|
|
|
return CartDebug::NONE;
|
|
|
|
|
}
|
|
|
|
|
|
2010-09-06 23:29:05 +00:00
|
|
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
|
|
|
|
void CartDebug::disasmTypeAsString(ostream& buf, DisasmType type) const
|
|
|
|
|
{
|
|
|
|
|
switch(type)
|
|
|
|
|
{
|
2010-10-07 22:34:22 +00:00
|
|
|
case CartDebug::CODE: buf << "CODE"; break;
|
2013-05-29 16:27:12 +00:00
|
|
|
case CartDebug::TCODE: buf << "TCODE"; break;
|
2010-10-07 22:34:22 +00:00
|
|
|
case CartDebug::GFX: buf << "GFX"; break;
|
2010-10-22 20:24:37 +00:00
|
|
|
case CartDebug::PGFX: buf << "PGFX"; break;
|
2010-10-07 22:34:22 +00:00
|
|
|
case CartDebug::DATA: buf << "DATA"; break;
|
|
|
|
|
case CartDebug::ROW: buf << "ROW"; break;
|
2010-10-22 20:24:37 +00:00
|
|
|
case CartDebug::REFERENCED:
|
|
|
|
|
case CartDebug::VALID_ENTRY:
|
|
|
|
|
case CartDebug::NONE: break;
|
2010-09-06 23:29:05 +00:00
|
|
|
}
|
Many big improvements to disassembler directives. Directives are no
longer simply added to a list, but intelligently 'merged' (so that
the entire range represented by all directives contains no overlap).
This makes the disassembly a little faster, since it doesn't have to
iterate redundantly. Still TODO in this area is intelligent insertion
for the same type (ie, if inserting in between like blocks, the
blocks should coalesce, instead of being clipped and then a new range
inserted in between).
Added 'loadconfig' and 'saveconfig' debugger prompt commands, which
will eventually access Distella-like config files. No implementation
is present yet.
Added 'listconfig' debugger command, which lists all directives
currently defined by the user, as well as the directives resulting
from a disassembly of a bank (taking into account extra knowledge
that Stella has WRT cached entry points). This command can show
information for a specified bank, or all banks in the cart.
User-defined directives can now be removed; simply issue the same
command that caused an insertion (ie, attempting to insert the same
type and range will remove it instead).
Fixed bug in Distella processing of directives; similar to the
standalone Distella, directives should be processed *before* any
automatic code determination is done.
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@2121 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-08-31 16:37:27 +00:00
|
|
|
}
|
|
|
|
|
|
2010-11-07 18:10:58 +00:00
|
|
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
|
|
|
|
void CartDebug::disasmTypeAsString(ostream& buf, uInt8 flags) const
|
|
|
|
|
{
|
|
|
|
|
if(flags)
|
|
|
|
|
{
|
|
|
|
|
if(flags & CartDebug::CODE)
|
|
|
|
|
buf << "CODE ";
|
2013-05-29 16:27:12 +00:00
|
|
|
if(flags & CartDebug::TCODE)
|
|
|
|
|
buf << "TCODE ";
|
2010-11-07 18:10:58 +00:00
|
|
|
if(flags & CartDebug::GFX)
|
|
|
|
|
buf << "GFX ";
|
|
|
|
|
if(flags & CartDebug::PGFX)
|
|
|
|
|
buf << "PGFX ";
|
|
|
|
|
if(flags & CartDebug::DATA)
|
|
|
|
|
buf << "DATA ";
|
|
|
|
|
if(flags & CartDebug::ROW)
|
|
|
|
|
buf << "ROW ";
|
|
|
|
|
if(flags & CartDebug::REFERENCED)
|
|
|
|
|
buf << "*REFERENCED ";
|
|
|
|
|
if(flags & CartDebug::VALID_ENTRY)
|
|
|
|
|
buf << "*VALID_ENTRY ";
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
buf << "no flags set";
|
|
|
|
|
}
|
|
|
|
|
|
2010-02-28 17:12:16 +00:00
|
|
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
2013-05-19 20:55:25 +00:00
|
|
|
const char* CartDebug::ourTIAMnemonicR[16] = {
|
2010-02-28 17:12:16 +00:00
|
|
|
"CXM0P", "CXM1P", "CXP0FB", "CXP1FB", "CXM0FB", "CXM1FB", "CXBLPF", "CXPPMM",
|
2013-05-19 20:55:25 +00:00
|
|
|
"INPT0", "INPT1", "INPT2", "INPT3", "INPT4", "INPT5", 0, 0
|
2010-02-28 17:12:16 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
2013-05-19 20:55:25 +00:00
|
|
|
const char* CartDebug::ourTIAMnemonicW[64] = {
|
2010-02-28 17:12:16 +00:00
|
|
|
"VSYNC", "VBLANK", "WSYNC", "RSYNC", "NUSIZ0", "NUSIZ1", "COLUP0", "COLUP1",
|
|
|
|
|
"COLUPF", "COLUBK", "CTRLPF", "REFP0", "REFP1", "PF0", "PF1", "PF2",
|
|
|
|
|
"RESP0", "RESP1", "RESM0", "RESM1", "RESBL", "AUDC0", "AUDC1", "AUDF0",
|
|
|
|
|
"AUDF1", "AUDV0", "AUDV1", "GRP0", "GRP1", "ENAM0", "ENAM1", "ENABL",
|
|
|
|
|
"HMP0", "HMP1", "HMM0", "HMM1", "HMBL", "VDELP0", "VDELP1", "VDELBL",
|
2013-05-19 20:55:25 +00:00
|
|
|
"RESMP0", "RESMP1", "HMOVE", "HMCLR", "CXCLR", 0, 0, 0,
|
|
|
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
|
2010-02-28 17:12:16 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
|
|
|
|
const char* CartDebug::ourIOMnemonic[24] = {
|
2013-05-19 20:55:25 +00:00
|
|
|
"SWCHA", "SWACNT", "SWCHB", "SWBCNT", "INTIM", "TIMINT", 0, 0, 0, 0, 0,
|
|
|
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, "TIM1T", "TIM8T", "TIM64T", "T1024T"
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
|
|
|
|
const char* CartDebug::ourZPMnemonic[128] = {
|
|
|
|
|
"ram_80", "ram_81", "ram_82", "ram_83", "ram_84", "ram_85", "ram_86", "ram_87",
|
|
|
|
|
"ram_88", "ram_89", "ram_8A", "ram_8B", "ram_8C", "ram_8D", "ram_8E", "ram_8F",
|
|
|
|
|
"ram_90", "ram_91", "ram_92", "ram_93", "ram_94", "ram_95", "ram_96", "ram_97",
|
|
|
|
|
"ram_98", "ram_99", "ram_9A", "ram_9B", "ram_9C", "ram_9D", "ram_9E", "ram_9F",
|
|
|
|
|
"ram_A0", "ram_A1", "ram_A2", "ram_A3", "ram_A4", "ram_A5", "ram_A6", "ram_A7",
|
|
|
|
|
"ram_A8", "ram_A9", "ram_AA", "ram_AB", "ram_AC", "ram_AD", "ram_AE", "ram_AF",
|
|
|
|
|
"ram_B0", "ram_B1", "ram_B2", "ram_B3", "ram_B4", "ram_B5", "ram_B6", "ram_B7",
|
|
|
|
|
"ram_B8", "ram_B9", "ram_BA", "ram_BB", "ram_BC", "ram_BD", "ram_BE", "ram_BF",
|
|
|
|
|
"ram_C0", "ram_C1", "ram_C2", "ram_C3", "ram_C4", "ram_C5", "ram_C6", "ram_C7",
|
|
|
|
|
"ram_C8", "ram_C9", "ram_CA", "ram_CB", "ram_CC", "ram_CD", "ram_CE", "ram_CF",
|
|
|
|
|
"ram_D0", "ram_D1", "ram_D2", "ram_D3", "ram_D4", "ram_D5", "ram_D6", "ram_D7",
|
|
|
|
|
"ram_D8", "ram_D9", "ram_DA", "ram_DB", "ram_DC", "ram_DD", "ram_DE", "ram_DF",
|
|
|
|
|
"ram_E0", "ram_E1", "ram_E2", "ram_E3", "ram_E4", "ram_E5", "ram_E6", "ram_E7",
|
|
|
|
|
"ram_E8", "ram_E9", "ram_EA", "ram_EB", "ram_EC", "ram_ED", "ram_EE", "ram_EF",
|
|
|
|
|
"ram_F0", "ram_F1", "ram_F2", "ram_F3", "ram_F4", "ram_F5", "ram_F6", "ram_F7",
|
|
|
|
|
"ram_F8", "ram_F9", "ram_FA", "ram_FB", "ram_FC", "ram_FD", "ram_FE", "ram_FF"
|
2010-02-28 17:12:16 +00:00
|
|
|
};
|