OK, this is the first pass at a huge reorganization of the debugger
classes. First off, the distella code has been integrated into a
DiStella class. This code isn't yet tied to the debugger, but it does
at least compile and generate valid output.
The RamDebug class has been replaced by a CartDebug class, which
takes responsibility for the previous RamDebug stuff as well as
things related to Cart address space (read from write ports,
disassembly, etc).
Fixed E7 bankswitching when reading from the write port in the upper
256byte area.
Fixed 'read from write port functionality' in general for all carts
that supported it previously. Basically, if _rwport is enabled, the
address is checked to be an actual read (vs. one that's part of a
normal write cycle), *and* it's actually an illegal access (each
cart/bankswitch type now provides a hint to indicate this condition).
Still TODO is clean up the rework, properly integrate DiStella, and
fix labels and defines (which seem to be completely broken).
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1922 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-01-17 16:48:45 +00:00
|
|
|
//============================================================================
|
|
|
|
//
|
|
|
|
// SSSS tt lll lll
|
|
|
|
// SS SS tt ll ll
|
|
|
|
// SS tttttt eeee ll ll aaaa
|
|
|
|
// SSSS tt ee ee ll ll aa
|
|
|
|
// SS tt eeeeee ll ll aaaaa -- "An Atari 2600 VCS Emulator"
|
|
|
|
// SS SS tt ee ll ll aa aa
|
|
|
|
// SSSS ttt eeeee llll llll aaaaa
|
|
|
|
//
|
|
|
|
// Copyright (c) 1995-2009 by Bradford W. Mott and the Stella team
|
|
|
|
//
|
|
|
|
// See the file "license" for information on usage and redistribution of
|
|
|
|
// this file, and for a DISCLAIMER OF ALL WARRANTIES.
|
|
|
|
//
|
|
|
|
// $Id$
|
|
|
|
//============================================================================
|
|
|
|
|
|
|
|
#include "bspf.hxx"
|
|
|
|
#include "Array.hxx"
|
|
|
|
#include "System.hxx"
|
2010-02-01 20:00:50 +00:00
|
|
|
#include "DiStella.hxx"
|
2010-03-05 22:02:12 +00:00
|
|
|
#include "CpuDebug.hxx"
|
OK, this is the first pass at a huge reorganization of the debugger
classes. First off, the distella code has been integrated into a
DiStella class. This code isn't yet tied to the debugger, but it does
at least compile and generate valid output.
The RamDebug class has been replaced by a CartDebug class, which
takes responsibility for the previous RamDebug stuff as well as
things related to Cart address space (read from write ports,
disassembly, etc).
Fixed E7 bankswitching when reading from the write port in the upper
256byte area.
Fixed 'read from write port functionality' in general for all carts
that supported it previously. Basically, if _rwport is enabled, the
address is checked to be an actual read (vs. one that's part of a
normal write cycle), *and* it's actually an illegal access (each
cart/bankswitch type now provides a hint to indicate this condition).
Still TODO is clean up the rework, properly integrate DiStella, and
fix labels and defines (which seem to be completely broken).
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1922 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-01-17 16:48:45 +00:00
|
|
|
#include "CartDebug.hxx"
|
|
|
|
|
|
|
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
|
|
|
CartDebug::CartDebug(Debugger& dbg, Console& console, const RamAreaList& areas)
|
|
|
|
: DebuggerSystem(dbg, console),
|
|
|
|
myRWPortAddress(0)
|
|
|
|
{
|
|
|
|
// Zero-page RAM is always present
|
|
|
|
addRamArea(0x80, 128, 0, 0);
|
|
|
|
|
|
|
|
// Add extended RAM
|
|
|
|
myRamAreas = areas;
|
|
|
|
for(RamAreaList::const_iterator i = areas.begin(); i != areas.end(); ++i)
|
|
|
|
addRamArea(i->start, i->size, i->roffset, i->woffset);
|
2010-03-05 22:02:12 +00:00
|
|
|
|
|
|
|
// We need a start address for each potential bank
|
|
|
|
myStartAddresses = new uInt16[myConsole.cartridge().bankCount()];
|
|
|
|
for(int i = 0; i < myConsole.cartridge().bankCount(); ++i)
|
|
|
|
myStartAddresses[i] = 0;
|
|
|
|
|
|
|
|
// We know the address for the startup bank right now
|
|
|
|
myStartAddresses[myConsole.cartridge().startBank()] = myDebugger.dpeek(0xfffc);
|
|
|
|
}
|
|
|
|
|
|
|
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
|
|
|
CartDebug::~CartDebug()
|
|
|
|
{
|
|
|
|
delete[] myStartAddresses;
|
OK, this is the first pass at a huge reorganization of the debugger
classes. First off, the distella code has been integrated into a
DiStella class. This code isn't yet tied to the debugger, but it does
at least compile and generate valid output.
The RamDebug class has been replaced by a CartDebug class, which
takes responsibility for the previous RamDebug stuff as well as
things related to Cart address space (read from write ports,
disassembly, etc).
Fixed E7 bankswitching when reading from the write port in the upper
256byte area.
Fixed 'read from write port functionality' in general for all carts
that supported it previously. Basically, if _rwport is enabled, the
address is checked to be an actual read (vs. one that's part of a
normal write cycle), *and* it's actually an illegal access (each
cart/bankswitch type now provides a hint to indicate this condition).
Still TODO is clean up the rework, properly integrate DiStella, and
fix labels and defines (which seem to be completely broken).
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1922 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-01-17 16:48:45 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
|
|
|
void CartDebug::addRamArea(uInt16 start, uInt16 size,
|
|
|
|
uInt16 roffset, uInt16 woffset)
|
|
|
|
{
|
|
|
|
// First make sure this area isn't already present
|
|
|
|
for(uInt32 i = 0; i < myState.rport.size(); ++i)
|
|
|
|
if(myState.rport[i] == start + roffset ||
|
|
|
|
myState.wport[i] == start + woffset)
|
|
|
|
return;
|
|
|
|
|
|
|
|
// Otherwise, add a new area
|
|
|
|
for(uInt32 i = 0; i < size; ++i)
|
|
|
|
{
|
|
|
|
myState.rport.push_back(i + start + roffset);
|
|
|
|
myState.wport.push_back(i + start + woffset);
|
|
|
|
|
|
|
|
myOldState.rport.push_back(i + start + roffset);
|
|
|
|
myOldState.wport.push_back(i + start + woffset);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
|
|
|
const DebuggerState& CartDebug::getState()
|
|
|
|
{
|
|
|
|
myState.ram.clear();
|
|
|
|
for(uInt32 i = 0; i < myState.rport.size(); ++i)
|
|
|
|
myState.ram.push_back(read(myState.rport[i]));
|
|
|
|
|
|
|
|
return myState;
|
|
|
|
}
|
|
|
|
|
|
|
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
|
|
|
void CartDebug::saveOldState()
|
|
|
|
{
|
|
|
|
myOldState.ram.clear();
|
|
|
|
for(uInt32 i = 0; i < myOldState.rport.size(); ++i)
|
|
|
|
myOldState.ram.push_back(read(myOldState.rport[i]));
|
|
|
|
}
|
|
|
|
|
|
|
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
|
|
|
uInt8 CartDebug::read(uInt16 addr)
|
|
|
|
{
|
|
|
|
return mySystem.peek(addr);
|
|
|
|
}
|
|
|
|
|
|
|
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
|
|
|
void CartDebug::write(uInt16 addr, uInt8 value)
|
|
|
|
{
|
|
|
|
mySystem.poke(addr, value);
|
|
|
|
}
|
|
|
|
|
|
|
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
|
|
|
int CartDebug::readFromWritePort()
|
|
|
|
{
|
|
|
|
uInt16 peekAddress = myRWPortAddress;
|
|
|
|
myRWPortAddress = 0;
|
|
|
|
|
|
|
|
// A read from the write port occurs when the read is actually in the write
|
|
|
|
// port address space AND the last access was actually a read (the latter
|
|
|
|
// differentiates between reads that are normally part of a write cycle vs.
|
2010-02-28 17:12:16 +00:00
|
|
|
// ones that are illegal)
|
OK, this is the first pass at a huge reorganization of the debugger
classes. First off, the distella code has been integrated into a
DiStella class. This code isn't yet tied to the debugger, but it does
at least compile and generate valid output.
The RamDebug class has been replaced by a CartDebug class, which
takes responsibility for the previous RamDebug stuff as well as
things related to Cart address space (read from write ports,
disassembly, etc).
Fixed E7 bankswitching when reading from the write port in the upper
256byte area.
Fixed 'read from write port functionality' in general for all carts
that supported it previously. Basically, if _rwport is enabled, the
address is checked to be an actual read (vs. one that's part of a
normal write cycle), *and* it's actually an illegal access (each
cart/bankswitch type now provides a hint to indicate this condition).
Still TODO is clean up the rework, properly integrate DiStella, and
fix labels and defines (which seem to be completely broken).
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1922 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-01-17 16:48:45 +00:00
|
|
|
if(mySystem.m6502().lastReadAddress() && peekAddress & 0x1000)
|
|
|
|
{
|
|
|
|
uInt16 addr = peekAddress & 0x0FFF;
|
|
|
|
for(RamAreaList::const_iterator i = myRamAreas.begin(); i != myRamAreas.end(); ++i)
|
|
|
|
{
|
|
|
|
uInt16 start = (i->start + i->woffset) & 0x0FFF;
|
|
|
|
uInt16 end = (i->start + i->woffset + i->size) & 0x0FFF;
|
|
|
|
if(addr >= start && addr < end)
|
|
|
|
return peekAddress;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
|
|
|
string CartDebug::toString()
|
|
|
|
{
|
|
|
|
string result;
|
|
|
|
char buf[128];
|
|
|
|
uInt32 bytesPerLine;
|
|
|
|
|
|
|
|
switch(myDebugger.parser().base())
|
|
|
|
{
|
|
|
|
case kBASE_16:
|
|
|
|
case kBASE_10:
|
|
|
|
bytesPerLine = 0x10;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case kBASE_2:
|
|
|
|
bytesPerLine = 0x04;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case kBASE_DEFAULT:
|
|
|
|
default:
|
|
|
|
return DebuggerParser::red("invalid base, this is a BUG");
|
|
|
|
}
|
|
|
|
|
|
|
|
const CartState& state = (CartState&) getState();
|
|
|
|
const CartState& oldstate = (CartState&) getOldState();
|
|
|
|
|
|
|
|
uInt32 curraddr = 0, bytesSoFar = 0;
|
|
|
|
for(uInt32 i = 0; i < state.ram.size(); i += bytesPerLine, bytesSoFar += bytesPerLine)
|
|
|
|
{
|
|
|
|
// We detect different 'pages' of RAM when the addresses jump by
|
|
|
|
// more than the number of bytes on the previous line, or when 256
|
|
|
|
// bytes have been previously output
|
|
|
|
if(state.rport[i] - curraddr > bytesPerLine || bytesSoFar >= 256)
|
|
|
|
{
|
|
|
|
sprintf(buf, "%04x: (rport = %04x, wport = %04x)\n",
|
|
|
|
state.rport[i], state.rport[i], state.wport[i]);
|
|
|
|
buf[2] = buf[3] = 'x';
|
|
|
|
result += DebuggerParser::red(buf);
|
|
|
|
bytesSoFar = 0;
|
|
|
|
}
|
|
|
|
curraddr = state.rport[i];
|
|
|
|
sprintf(buf, "%.2x: ", curraddr & 0x00ff);
|
|
|
|
result += buf;
|
|
|
|
|
|
|
|
for(uInt8 j = 0; j < bytesPerLine; ++j)
|
|
|
|
{
|
|
|
|
result += myDebugger.invIfChanged(state.ram[i+j], oldstate.ram[i+j]);
|
|
|
|
result += " ";
|
|
|
|
|
|
|
|
if(j == 0x07) result += " ";
|
|
|
|
}
|
|
|
|
result += "\n";
|
|
|
|
}
|
|
|
|
|
|
|
|
return result;
|
|
|
|
}
|
|
|
|
|
|
|
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
2010-02-07 21:23:26 +00:00
|
|
|
bool CartDebug::disassemble(bool autocode)
|
OK, this is the first pass at a huge reorganization of the debugger
classes. First off, the distella code has been integrated into a
DiStella class. This code isn't yet tied to the debugger, but it does
at least compile and generate valid output.
The RamDebug class has been replaced by a CartDebug class, which
takes responsibility for the previous RamDebug stuff as well as
things related to Cart address space (read from write ports,
disassembly, etc).
Fixed E7 bankswitching when reading from the write port in the upper
256byte area.
Fixed 'read from write port functionality' in general for all carts
that supported it previously. Basically, if _rwport is enabled, the
address is checked to be an actual read (vs. one that's part of a
normal write cycle), *and* it's actually an illegal access (each
cart/bankswitch type now provides a hint to indicate this condition).
Still TODO is clean up the rework, properly integrate DiStella, and
fix labels and defines (which seem to be completely broken).
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1922 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-01-17 16:48:45 +00:00
|
|
|
{
|
2010-02-07 21:23:26 +00:00
|
|
|
// Test current disassembly; don't re-disassemble if it hasn't changed
|
|
|
|
// ...
|
2010-03-06 18:56:36 +00:00
|
|
|
bool changed = myConsole.cartridge().bankChanged();
|
2010-02-07 21:23:26 +00:00
|
|
|
if(changed)
|
|
|
|
{
|
|
|
|
myDisassembly.clear();
|
|
|
|
myAddrToLineList.clear();
|
OK, this is the first pass at a huge reorganization of the debugger
classes. First off, the distella code has been integrated into a
DiStella class. This code isn't yet tied to the debugger, but it does
at least compile and generate valid output.
The RamDebug class has been replaced by a CartDebug class, which
takes responsibility for the previous RamDebug stuff as well as
things related to Cart address space (read from write ports,
disassembly, etc).
Fixed E7 bankswitching when reading from the write port in the upper
256byte area.
Fixed 'read from write port functionality' in general for all carts
that supported it previously. Basically, if _rwport is enabled, the
address is checked to be an actual read (vs. one that's part of a
normal write cycle), *and* it's actually an illegal access (each
cart/bankswitch type now provides a hint to indicate this condition).
Still TODO is clean up the rework, properly integrate DiStella, and
fix labels and defines (which seem to be completely broken).
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1922 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-01-17 16:48:45 +00:00
|
|
|
|
2010-03-05 22:02:12 +00:00
|
|
|
// We only use the reset vector when we're actually in the startup bank
|
|
|
|
// Otherwise, we look at previous accesses to this bank to begin
|
|
|
|
// If no previous address exists, use the current program counter
|
|
|
|
uInt16 start = myStartAddresses[getBank()];
|
|
|
|
|
|
|
|
cerr << "start addresses: ";
|
|
|
|
for(int i = 0; i < myConsole.cartridge().bankCount(); ++i) cerr << " " << setw(4) << hex << myStartAddresses[i];
|
|
|
|
cerr << endl;
|
|
|
|
cerr << "current bank = " << getBank() << ", start bank = " << myConsole.cartridge().startBank() << endl
|
|
|
|
<< "reset = " << hex << 0xfffc << ", pc = " << hex << myDebugger.cpuDebug().pc() << endl
|
|
|
|
<< "start = " << hex << start << endl;
|
|
|
|
if(start == 0)
|
|
|
|
start = myStartAddresses[getBank()] = myDebugger.cpuDebug().pc();
|
|
|
|
cerr << "actual start = " << hex << start << endl << endl;
|
|
|
|
|
|
|
|
// For now, DiStella can't handle address space below 0x1000
|
|
|
|
if(!(start & 0x1000))
|
|
|
|
return true;
|
|
|
|
|
|
|
|
autocode = false;
|
2010-02-07 21:23:26 +00:00
|
|
|
DiStella distella(myDisassembly, start, autocode);
|
OK, this is the first pass at a huge reorganization of the debugger
classes. First off, the distella code has been integrated into a
DiStella class. This code isn't yet tied to the debugger, but it does
at least compile and generate valid output.
The RamDebug class has been replaced by a CartDebug class, which
takes responsibility for the previous RamDebug stuff as well as
things related to Cart address space (read from write ports,
disassembly, etc).
Fixed E7 bankswitching when reading from the write port in the upper
256byte area.
Fixed 'read from write port functionality' in general for all carts
that supported it previously. Basically, if _rwport is enabled, the
address is checked to be an actual read (vs. one that's part of a
normal write cycle), *and* it's actually an illegal access (each
cart/bankswitch type now provides a hint to indicate this condition).
Still TODO is clean up the rework, properly integrate DiStella, and
fix labels and defines (which seem to be completely broken).
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1922 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-01-17 16:48:45 +00:00
|
|
|
|
2010-02-07 21:23:26 +00:00
|
|
|
// Parts of the disassembly will be accessed later in different ways
|
|
|
|
// We place those parts in separate maps, to speed up access
|
|
|
|
for(uInt32 i = 0; i < myDisassembly.size(); ++i)
|
|
|
|
{
|
|
|
|
const DisassemblyTag& tag = myDisassembly[i];
|
OK, this is the first pass at a huge reorganization of the debugger
classes. First off, the distella code has been integrated into a
DiStella class. This code isn't yet tied to the debugger, but it does
at least compile and generate valid output.
The RamDebug class has been replaced by a CartDebug class, which
takes responsibility for the previous RamDebug stuff as well as
things related to Cart address space (read from write ports,
disassembly, etc).
Fixed E7 bankswitching when reading from the write port in the upper
256byte area.
Fixed 'read from write port functionality' in general for all carts
that supported it previously. Basically, if _rwport is enabled, the
address is checked to be an actual read (vs. one that's part of a
normal write cycle), *and* it's actually an illegal access (each
cart/bankswitch type now provides a hint to indicate this condition).
Still TODO is clean up the rework, properly integrate DiStella, and
fix labels and defines (which seem to be completely broken).
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1922 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-01-17 16:48:45 +00:00
|
|
|
|
2010-02-07 21:23:26 +00:00
|
|
|
// Create a mapping from addresses to line numbers
|
|
|
|
if(tag.address != 0)
|
|
|
|
myAddrToLineList.insert(make_pair(tag.address, i));
|
OK, this is the first pass at a huge reorganization of the debugger
classes. First off, the distella code has been integrated into a
DiStella class. This code isn't yet tied to the debugger, but it does
at least compile and generate valid output.
The RamDebug class has been replaced by a CartDebug class, which
takes responsibility for the previous RamDebug stuff as well as
things related to Cart address space (read from write ports,
disassembly, etc).
Fixed E7 bankswitching when reading from the write port in the upper
256byte area.
Fixed 'read from write port functionality' in general for all carts
that supported it previously. Basically, if _rwport is enabled, the
address is checked to be an actual read (vs. one that's part of a
normal write cycle), *and* it's actually an illegal access (each
cart/bankswitch type now provides a hint to indicate this condition).
Still TODO is clean up the rework, properly integrate DiStella, and
fix labels and defines (which seem to be completely broken).
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1922 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-01-17 16:48:45 +00:00
|
|
|
|
2010-02-07 21:23:26 +00:00
|
|
|
// TODO - look at list, extract address to label mappings
|
|
|
|
// we need these for label support in the UI and promptwidget
|
OK, this is the first pass at a huge reorganization of the debugger
classes. First off, the distella code has been integrated into a
DiStella class. This code isn't yet tied to the debugger, but it does
at least compile and generate valid output.
The RamDebug class has been replaced by a CartDebug class, which
takes responsibility for the previous RamDebug stuff as well as
things related to Cart address space (read from write ports,
disassembly, etc).
Fixed E7 bankswitching when reading from the write port in the upper
256byte area.
Fixed 'read from write port functionality' in general for all carts
that supported it previously. Basically, if _rwport is enabled, the
address is checked to be an actual read (vs. one that's part of a
normal write cycle), *and* it's actually an illegal access (each
cart/bankswitch type now provides a hint to indicate this condition).
Still TODO is clean up the rework, properly integrate DiStella, and
fix labels and defines (which seem to be completely broken).
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1922 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-01-17 16:48:45 +00:00
|
|
|
}
|
|
|
|
}
|
2010-02-07 21:23:26 +00:00
|
|
|
|
|
|
|
return changed;
|
OK, this is the first pass at a huge reorganization of the debugger
classes. First off, the distella code has been integrated into a
DiStella class. This code isn't yet tied to the debugger, but it does
at least compile and generate valid output.
The RamDebug class has been replaced by a CartDebug class, which
takes responsibility for the previous RamDebug stuff as well as
things related to Cart address space (read from write ports,
disassembly, etc).
Fixed E7 bankswitching when reading from the write port in the upper
256byte area.
Fixed 'read from write port functionality' in general for all carts
that supported it previously. Basically, if _rwport is enabled, the
address is checked to be an actual read (vs. one that's part of a
normal write cycle), *and* it's actually an illegal access (each
cart/bankswitch type now provides a hint to indicate this condition).
Still TODO is clean up the rework, properly integrate DiStella, and
fix labels and defines (which seem to be completely broken).
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1922 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-01-17 16:48:45 +00:00
|
|
|
}
|
|
|
|
|
2010-02-01 20:00:50 +00:00
|
|
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
2010-02-07 21:23:26 +00:00
|
|
|
int CartDebug::addressToLine(uInt16 address) const
|
2010-02-01 20:00:50 +00:00
|
|
|
{
|
2010-02-07 21:23:26 +00:00
|
|
|
map<uInt16, int>::const_iterator iter = myAddrToLineList.find(address);
|
|
|
|
return iter != myAddrToLineList.end() ? iter->second : 0;
|
2010-02-01 20:00:50 +00:00
|
|
|
}
|
|
|
|
|
OK, this is the first pass at a huge reorganization of the debugger
classes. First off, the distella code has been integrated into a
DiStella class. This code isn't yet tied to the debugger, but it does
at least compile and generate valid output.
The RamDebug class has been replaced by a CartDebug class, which
takes responsibility for the previous RamDebug stuff as well as
things related to Cart address space (read from write ports,
disassembly, etc).
Fixed E7 bankswitching when reading from the write port in the upper
256byte area.
Fixed 'read from write port functionality' in general for all carts
that supported it previously. Basically, if _rwport is enabled, the
address is checked to be an actual read (vs. one that's part of a
normal write cycle), *and* it's actually an illegal access (each
cart/bankswitch type now provides a hint to indicate this condition).
Still TODO is clean up the rework, properly integrate DiStella, and
fix labels and defines (which seem to be completely broken).
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1922 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-01-17 16:48:45 +00:00
|
|
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
2010-02-07 21:23:26 +00:00
|
|
|
string CartDebug::disassemble(uInt16 start, uInt16 lines) const
|
OK, this is the first pass at a huge reorganization of the debugger
classes. First off, the distella code has been integrated into a
DiStella class. This code isn't yet tied to the debugger, but it does
at least compile and generate valid output.
The RamDebug class has been replaced by a CartDebug class, which
takes responsibility for the previous RamDebug stuff as well as
things related to Cart address space (read from write ports,
disassembly, etc).
Fixed E7 bankswitching when reading from the write port in the upper
256byte area.
Fixed 'read from write port functionality' in general for all carts
that supported it previously. Basically, if _rwport is enabled, the
address is checked to be an actual read (vs. one that's part of a
normal write cycle), *and* it's actually an illegal access (each
cart/bankswitch type now provides a hint to indicate this condition).
Still TODO is clean up the rework, properly integrate DiStella, and
fix labels and defines (which seem to be completely broken).
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1922 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-01-17 16:48:45 +00:00
|
|
|
{
|
2010-02-07 21:23:26 +00:00
|
|
|
if(!(start & 0x1000))
|
2010-02-28 17:12:16 +00:00
|
|
|
return DebuggerParser::red("Disassembly below 0x1000 not yet supported");
|
OK, this is the first pass at a huge reorganization of the debugger
classes. First off, the distella code has been integrated into a
DiStella class. This code isn't yet tied to the debugger, but it does
at least compile and generate valid output.
The RamDebug class has been replaced by a CartDebug class, which
takes responsibility for the previous RamDebug stuff as well as
things related to Cart address space (read from write ports,
disassembly, etc).
Fixed E7 bankswitching when reading from the write port in the upper
256byte area.
Fixed 'read from write port functionality' in general for all carts
that supported it previously. Basically, if _rwport is enabled, the
address is checked to be an actual read (vs. one that's part of a
normal write cycle), *and* it's actually an illegal access (each
cart/bankswitch type now provides a hint to indicate this condition).
Still TODO is clean up the rework, properly integrate DiStella, and
fix labels and defines (which seem to be completely broken).
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1922 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-01-17 16:48:45 +00:00
|
|
|
|
2010-02-07 21:23:26 +00:00
|
|
|
DisassemblyList list;
|
|
|
|
DiStella distella(list, start, false);
|
OK, this is the first pass at a huge reorganization of the debugger
classes. First off, the distella code has been integrated into a
DiStella class. This code isn't yet tied to the debugger, but it does
at least compile and generate valid output.
The RamDebug class has been replaced by a CartDebug class, which
takes responsibility for the previous RamDebug stuff as well as
things related to Cart address space (read from write ports,
disassembly, etc).
Fixed E7 bankswitching when reading from the write port in the upper
256byte area.
Fixed 'read from write port functionality' in general for all carts
that supported it previously. Basically, if _rwport is enabled, the
address is checked to be an actual read (vs. one that's part of a
normal write cycle), *and* it's actually an illegal access (each
cart/bankswitch type now provides a hint to indicate this condition).
Still TODO is clean up the rework, properly integrate DiStella, and
fix labels and defines (which seem to be completely broken).
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1922 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-01-17 16:48:45 +00:00
|
|
|
|
2010-02-07 21:23:26 +00:00
|
|
|
// Fill the string with disassembled data
|
|
|
|
start &= 0xFFF;
|
|
|
|
ostringstream buffer;
|
2010-03-06 18:56:36 +00:00
|
|
|
for(uInt32 i = 0; i < list.size() && lines > 0; ++i, --lines)
|
OK, this is the first pass at a huge reorganization of the debugger
classes. First off, the distella code has been integrated into a
DiStella class. This code isn't yet tied to the debugger, but it does
at least compile and generate valid output.
The RamDebug class has been replaced by a CartDebug class, which
takes responsibility for the previous RamDebug stuff as well as
things related to Cart address space (read from write ports,
disassembly, etc).
Fixed E7 bankswitching when reading from the write port in the upper
256byte area.
Fixed 'read from write port functionality' in general for all carts
that supported it previously. Basically, if _rwport is enabled, the
address is checked to be an actual read (vs. one that's part of a
normal write cycle), *and* it's actually an illegal access (each
cart/bankswitch type now provides a hint to indicate this condition).
Still TODO is clean up the rework, properly integrate DiStella, and
fix labels and defines (which seem to be completely broken).
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1922 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-01-17 16:48:45 +00:00
|
|
|
{
|
2010-02-07 21:23:26 +00:00
|
|
|
const CartDebug::DisassemblyTag& tag = list[i];
|
|
|
|
if((tag.address & 0xfff) >= start)
|
|
|
|
{
|
|
|
|
buffer << uppercase << hex << setw(4) << setfill('0') << tag.address
|
|
|
|
<< ": " << tag.disasm << " " << tag.bytes << endl;
|
|
|
|
}
|
OK, this is the first pass at a huge reorganization of the debugger
classes. First off, the distella code has been integrated into a
DiStella class. This code isn't yet tied to the debugger, but it does
at least compile and generate valid output.
The RamDebug class has been replaced by a CartDebug class, which
takes responsibility for the previous RamDebug stuff as well as
things related to Cart address space (read from write ports,
disassembly, etc).
Fixed E7 bankswitching when reading from the write port in the upper
256byte area.
Fixed 'read from write port functionality' in general for all carts
that supported it previously. Basically, if _rwport is enabled, the
address is checked to be an actual read (vs. one that's part of a
normal write cycle), *and* it's actually an illegal access (each
cart/bankswitch type now provides a hint to indicate this condition).
Still TODO is clean up the rework, properly integrate DiStella, and
fix labels and defines (which seem to be completely broken).
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1922 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-01-17 16:48:45 +00:00
|
|
|
}
|
|
|
|
|
2010-02-07 21:23:26 +00:00
|
|
|
return buffer.str();
|
OK, this is the first pass at a huge reorganization of the debugger
classes. First off, the distella code has been integrated into a
DiStella class. This code isn't yet tied to the debugger, but it does
at least compile and generate valid output.
The RamDebug class has been replaced by a CartDebug class, which
takes responsibility for the previous RamDebug stuff as well as
things related to Cart address space (read from write ports,
disassembly, etc).
Fixed E7 bankswitching when reading from the write port in the upper
256byte area.
Fixed 'read from write port functionality' in general for all carts
that supported it previously. Basically, if _rwport is enabled, the
address is checked to be an actual read (vs. one that's part of a
normal write cycle), *and* it's actually an illegal access (each
cart/bankswitch type now provides a hint to indicate this condition).
Still TODO is clean up the rework, properly integrate DiStella, and
fix labels and defines (which seem to be completely broken).
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1922 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-01-17 16:48:45 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
|
|
|
int CartDebug::getBank()
|
|
|
|
{
|
|
|
|
return myConsole.cartridge().bank();
|
|
|
|
}
|
|
|
|
|
|
|
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
|
|
|
int CartDebug::bankCount()
|
|
|
|
{
|
|
|
|
return myConsole.cartridge().bankCount();
|
|
|
|
}
|
|
|
|
|
|
|
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
|
|
|
string CartDebug::getCartType()
|
|
|
|
{
|
|
|
|
return myConsole.cartridge().name();
|
|
|
|
}
|
|
|
|
|
|
|
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
|
|
|
void CartDebug::addLabel(const string& label, uInt16 address)
|
|
|
|
{
|
2010-02-28 17:12:16 +00:00
|
|
|
// Only user-defined labels can be added
|
|
|
|
switch(addressType(address))
|
|
|
|
{
|
|
|
|
case ADDR_TIA:
|
|
|
|
case ADDR_RIOT:
|
|
|
|
return;
|
|
|
|
default:
|
|
|
|
cerr << "addLabel: label = " << label << ", address = " << hex << address << endl;
|
|
|
|
removeLabel(label);
|
|
|
|
myUserAddresses.insert(make_pair(label, address));
|
|
|
|
myUserLabels.insert(make_pair(address, label));
|
|
|
|
break;
|
OK, this is the first pass at a huge reorganization of the debugger
classes. First off, the distella code has been integrated into a
DiStella class. This code isn't yet tied to the debugger, but it does
at least compile and generate valid output.
The RamDebug class has been replaced by a CartDebug class, which
takes responsibility for the previous RamDebug stuff as well as
things related to Cart address space (read from write ports,
disassembly, etc).
Fixed E7 bankswitching when reading from the write port in the upper
256byte area.
Fixed 'read from write port functionality' in general for all carts
that supported it previously. Basically, if _rwport is enabled, the
address is checked to be an actual read (vs. one that's part of a
normal write cycle), *and* it's actually an illegal access (each
cart/bankswitch type now provides a hint to indicate this condition).
Still TODO is clean up the rework, properly integrate DiStella, and
fix labels and defines (which seem to be completely broken).
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1922 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-01-17 16:48:45 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
|
|
|
bool CartDebug::removeLabel(const string& label)
|
|
|
|
{
|
2010-02-28 17:12:16 +00:00
|
|
|
// Only user-defined labels can be removed
|
OK, this is the first pass at a huge reorganization of the debugger
classes. First off, the distella code has been integrated into a
DiStella class. This code isn't yet tied to the debugger, but it does
at least compile and generate valid output.
The RamDebug class has been replaced by a CartDebug class, which
takes responsibility for the previous RamDebug stuff as well as
things related to Cart address space (read from write ports,
disassembly, etc).
Fixed E7 bankswitching when reading from the write port in the upper
256byte area.
Fixed 'read from write port functionality' in general for all carts
that supported it previously. Basically, if _rwport is enabled, the
address is checked to be an actual read (vs. one that's part of a
normal write cycle), *and* it's actually an illegal access (each
cart/bankswitch type now provides a hint to indicate this condition).
Still TODO is clean up the rework, properly integrate DiStella, and
fix labels and defines (which seem to be completely broken).
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1922 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-01-17 16:48:45 +00:00
|
|
|
LabelToAddr::iterator iter = myUserAddresses.find(label);
|
|
|
|
if(iter != myUserAddresses.end())
|
|
|
|
{
|
2010-02-28 17:12:16 +00:00
|
|
|
cerr << "removeLabel: label = " << label << endl;
|
OK, this is the first pass at a huge reorganization of the debugger
classes. First off, the distella code has been integrated into a
DiStella class. This code isn't yet tied to the debugger, but it does
at least compile and generate valid output.
The RamDebug class has been replaced by a CartDebug class, which
takes responsibility for the previous RamDebug stuff as well as
things related to Cart address space (read from write ports,
disassembly, etc).
Fixed E7 bankswitching when reading from the write port in the upper
256byte area.
Fixed 'read from write port functionality' in general for all carts
that supported it previously. Basically, if _rwport is enabled, the
address is checked to be an actual read (vs. one that's part of a
normal write cycle), *and* it's actually an illegal access (each
cart/bankswitch type now provides a hint to indicate this condition).
Still TODO is clean up the rework, properly integrate DiStella, and
fix labels and defines (which seem to be completely broken).
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1922 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-01-17 16:48:45 +00:00
|
|
|
// Erase the label
|
|
|
|
myUserAddresses.erase(iter);
|
|
|
|
|
|
|
|
// And also erase the address assigned to it
|
2010-02-28 17:12:16 +00:00
|
|
|
AddrToLabel::iterator iter2 = myUserLabels.find(iter->second);
|
OK, this is the first pass at a huge reorganization of the debugger
classes. First off, the distella code has been integrated into a
DiStella class. This code isn't yet tied to the debugger, but it does
at least compile and generate valid output.
The RamDebug class has been replaced by a CartDebug class, which
takes responsibility for the previous RamDebug stuff as well as
things related to Cart address space (read from write ports,
disassembly, etc).
Fixed E7 bankswitching when reading from the write port in the upper
256byte area.
Fixed 'read from write port functionality' in general for all carts
that supported it previously. Basically, if _rwport is enabled, the
address is checked to be an actual read (vs. one that's part of a
normal write cycle), *and* it's actually an illegal access (each
cart/bankswitch type now provides a hint to indicate this condition).
Still TODO is clean up the rework, properly integrate DiStella, and
fix labels and defines (which seem to be completely broken).
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1922 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-01-17 16:48:45 +00:00
|
|
|
if(iter2 != myUserLabels.end())
|
|
|
|
myUserLabels.erase(iter2);
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
|
|
|
const string& CartDebug::getLabel(uInt16 addr, bool isRead, int places) const
|
|
|
|
{
|
|
|
|
static string result;
|
|
|
|
|
2010-02-28 17:12:16 +00:00
|
|
|
switch(addressType(addr))
|
OK, this is the first pass at a huge reorganization of the debugger
classes. First off, the distella code has been integrated into a
DiStella class. This code isn't yet tied to the debugger, but it does
at least compile and generate valid output.
The RamDebug class has been replaced by a CartDebug class, which
takes responsibility for the previous RamDebug stuff as well as
things related to Cart address space (read from write ports,
disassembly, etc).
Fixed E7 bankswitching when reading from the write port in the upper
256byte area.
Fixed 'read from write port functionality' in general for all carts
that supported it previously. Basically, if _rwport is enabled, the
address is checked to be an actual read (vs. one that's part of a
normal write cycle), *and* it's actually an illegal access (each
cart/bankswitch type now provides a hint to indicate this condition).
Still TODO is clean up the rework, properly integrate DiStella, and
fix labels and defines (which seem to be completely broken).
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1922 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-01-17 16:48:45 +00:00
|
|
|
{
|
|
|
|
case ADDR_TIA:
|
2010-02-28 17:12:16 +00:00
|
|
|
return result =
|
|
|
|
(isRead ? ourTIAMnemonicR[addr&0x0f] : ourTIAMnemonicW[addr&0x3f]);
|
OK, this is the first pass at a huge reorganization of the debugger
classes. First off, the distella code has been integrated into a
DiStella class. This code isn't yet tied to the debugger, but it does
at least compile and generate valid output.
The RamDebug class has been replaced by a CartDebug class, which
takes responsibility for the previous RamDebug stuff as well as
things related to Cart address space (read from write ports,
disassembly, etc).
Fixed E7 bankswitching when reading from the write port in the upper
256byte area.
Fixed 'read from write port functionality' in general for all carts
that supported it previously. Basically, if _rwport is enabled, the
address is checked to be an actual read (vs. one that's part of a
normal write cycle), *and* it's actually an illegal access (each
cart/bankswitch type now provides a hint to indicate this condition).
Still TODO is clean up the rework, properly integrate DiStella, and
fix labels and defines (which seem to be completely broken).
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1922 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-01-17 16:48:45 +00:00
|
|
|
|
2010-02-28 17:12:16 +00:00
|
|
|
case ADDR_RIOT:
|
|
|
|
return result = ourIOMnemonic[(addr&0xf00)-280];
|
OK, this is the first pass at a huge reorganization of the debugger
classes. First off, the distella code has been integrated into a
DiStella class. This code isn't yet tied to the debugger, but it does
at least compile and generate valid output.
The RamDebug class has been replaced by a CartDebug class, which
takes responsibility for the previous RamDebug stuff as well as
things related to Cart address space (read from write ports,
disassembly, etc).
Fixed E7 bankswitching when reading from the write port in the upper
256byte area.
Fixed 'read from write port functionality' in general for all carts
that supported it previously. Basically, if _rwport is enabled, the
address is checked to be an actual read (vs. one that's part of a
normal write cycle), *and* it's actually an illegal access (each
cart/bankswitch type now provides a hint to indicate this condition).
Still TODO is clean up the rework, properly integrate DiStella, and
fix labels and defines (which seem to be completely broken).
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1922 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-01-17 16:48:45 +00:00
|
|
|
|
|
|
|
case ADDR_RAM:
|
|
|
|
case ADDR_ROM:
|
2010-02-28 17:12:16 +00:00
|
|
|
{
|
OK, this is the first pass at a huge reorganization of the debugger
classes. First off, the distella code has been integrated into a
DiStella class. This code isn't yet tied to the debugger, but it does
at least compile and generate valid output.
The RamDebug class has been replaced by a CartDebug class, which
takes responsibility for the previous RamDebug stuff as well as
things related to Cart address space (read from write ports,
disassembly, etc).
Fixed E7 bankswitching when reading from the write port in the upper
256byte area.
Fixed 'read from write port functionality' in general for all carts
that supported it previously. Basically, if _rwport is enabled, the
address is checked to be an actual read (vs. one that's part of a
normal write cycle), *and* it's actually an illegal access (each
cart/bankswitch type now provides a hint to indicate this condition).
Still TODO is clean up the rework, properly integrate DiStella, and
fix labels and defines (which seem to be completely broken).
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1922 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-01-17 16:48:45 +00:00
|
|
|
// These addresses can never be in the system labels list
|
2010-02-28 17:12:16 +00:00
|
|
|
AddrToLabel::const_iterator iter;
|
OK, this is the first pass at a huge reorganization of the debugger
classes. First off, the distella code has been integrated into a
DiStella class. This code isn't yet tied to the debugger, but it does
at least compile and generate valid output.
The RamDebug class has been replaced by a CartDebug class, which
takes responsibility for the previous RamDebug stuff as well as
things related to Cart address space (read from write ports,
disassembly, etc).
Fixed E7 bankswitching when reading from the write port in the upper
256byte area.
Fixed 'read from write port functionality' in general for all carts
that supported it previously. Basically, if _rwport is enabled, the
address is checked to be an actual read (vs. one that's part of a
normal write cycle), *and* it's actually an illegal access (each
cart/bankswitch type now provides a hint to indicate this condition).
Still TODO is clean up the rework, properly integrate DiStella, and
fix labels and defines (which seem to be completely broken).
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1922 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-01-17 16:48:45 +00:00
|
|
|
if((iter = myUserLabels.find(addr)) != myUserLabels.end())
|
2010-02-28 17:12:16 +00:00
|
|
|
return iter->second;
|
OK, this is the first pass at a huge reorganization of the debugger
classes. First off, the distella code has been integrated into a
DiStella class. This code isn't yet tied to the debugger, but it does
at least compile and generate valid output.
The RamDebug class has been replaced by a CartDebug class, which
takes responsibility for the previous RamDebug stuff as well as
things related to Cart address space (read from write ports,
disassembly, etc).
Fixed E7 bankswitching when reading from the write port in the upper
256byte area.
Fixed 'read from write port functionality' in general for all carts
that supported it previously. Basically, if _rwport is enabled, the
address is checked to be an actual read (vs. one that's part of a
normal write cycle), *and* it's actually an illegal access (each
cart/bankswitch type now provides a hint to indicate this condition).
Still TODO is clean up the rework, properly integrate DiStella, and
fix labels and defines (which seem to be completely broken).
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1922 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-01-17 16:48:45 +00:00
|
|
|
break;
|
2010-02-28 17:12:16 +00:00
|
|
|
}
|
OK, this is the first pass at a huge reorganization of the debugger
classes. First off, the distella code has been integrated into a
DiStella class. This code isn't yet tied to the debugger, but it does
at least compile and generate valid output.
The RamDebug class has been replaced by a CartDebug class, which
takes responsibility for the previous RamDebug stuff as well as
things related to Cart address space (read from write ports,
disassembly, etc).
Fixed E7 bankswitching when reading from the write port in the upper
256byte area.
Fixed 'read from write port functionality' in general for all carts
that supported it previously. Basically, if _rwport is enabled, the
address is checked to be an actual read (vs. one that's part of a
normal write cycle), *and* it's actually an illegal access (each
cart/bankswitch type now provides a hint to indicate this condition).
Still TODO is clean up the rework, properly integrate DiStella, and
fix labels and defines (which seem to be completely broken).
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1922 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-01-17 16:48:45 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
if(places > -1)
|
|
|
|
{
|
|
|
|
ostringstream buf;
|
|
|
|
buf << "$" << setw(places) << hex << addr;
|
|
|
|
return result = buf.str();
|
|
|
|
}
|
|
|
|
|
|
|
|
return EmptyString;
|
|
|
|
}
|
|
|
|
|
|
|
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
|
|
|
int CartDebug::getAddress(const string& label) const
|
|
|
|
{
|
2010-02-28 17:12:16 +00:00
|
|
|
/* FIXME
|
OK, this is the first pass at a huge reorganization of the debugger
classes. First off, the distella code has been integrated into a
DiStella class. This code isn't yet tied to the debugger, but it does
at least compile and generate valid output.
The RamDebug class has been replaced by a CartDebug class, which
takes responsibility for the previous RamDebug stuff as well as
things related to Cart address space (read from write ports,
disassembly, etc).
Fixed E7 bankswitching when reading from the write port in the upper
256byte area.
Fixed 'read from write port functionality' in general for all carts
that supported it previously. Basically, if _rwport is enabled, the
address is checked to be an actual read (vs. one that's part of a
normal write cycle), *and* it's actually an illegal access (each
cart/bankswitch type now provides a hint to indicate this condition).
Still TODO is clean up the rework, properly integrate DiStella, and
fix labels and defines (which seem to be completely broken).
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1922 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-01-17 16:48:45 +00:00
|
|
|
LabelToAddr::const_iterator iter;
|
|
|
|
|
|
|
|
if((iter = mySystemAddresses.find(label)) != mySystemAddresses.end())
|
|
|
|
return iter->second.address;
|
|
|
|
else if((iter = myUserAddresses.find(label)) != myUserAddresses.end())
|
|
|
|
return iter->second.address;
|
|
|
|
else
|
|
|
|
return -1;
|
2010-02-28 17:12:16 +00:00
|
|
|
*/
|
|
|
|
return -1;
|
OK, this is the first pass at a huge reorganization of the debugger
classes. First off, the distella code has been integrated into a
DiStella class. This code isn't yet tied to the debugger, but it does
at least compile and generate valid output.
The RamDebug class has been replaced by a CartDebug class, which
takes responsibility for the previous RamDebug stuff as well as
things related to Cart address space (read from write ports,
disassembly, etc).
Fixed E7 bankswitching when reading from the write port in the upper
256byte area.
Fixed 'read from write port functionality' in general for all carts
that supported it previously. Basically, if _rwport is enabled, the
address is checked to be an actual read (vs. one that's part of a
normal write cycle), *and* it's actually an illegal access (each
cart/bankswitch type now provides a hint to indicate this condition).
Still TODO is clean up the rework, properly integrate DiStella, and
fix labels and defines (which seem to be completely broken).
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1922 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-01-17 16:48:45 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
|
|
|
string CartDebug::loadSymbolFile(const string& f)
|
|
|
|
{
|
|
|
|
string file = f;
|
|
|
|
string::size_type spos;
|
|
|
|
if( (spos = file.find_last_of('.')) != string::npos )
|
|
|
|
file.replace(spos, file.size(), ".sym");
|
|
|
|
else
|
|
|
|
file += ".sym";
|
|
|
|
|
2010-02-28 17:12:16 +00:00
|
|
|
cerr << "loadSymbolFile: " << file << endl;
|
|
|
|
|
OK, this is the first pass at a huge reorganization of the debugger
classes. First off, the distella code has been integrated into a
DiStella class. This code isn't yet tied to the debugger, but it does
at least compile and generate valid output.
The RamDebug class has been replaced by a CartDebug class, which
takes responsibility for the previous RamDebug stuff as well as
things related to Cart address space (read from write ports,
disassembly, etc).
Fixed E7 bankswitching when reading from the write port in the upper
256byte area.
Fixed 'read from write port functionality' in general for all carts
that supported it previously. Basically, if _rwport is enabled, the
address is checked to be an actual read (vs. one that's part of a
normal write cycle), *and* it's actually an illegal access (each
cart/bankswitch type now provides a hint to indicate this condition).
Still TODO is clean up the rework, properly integrate DiStella, and
fix labels and defines (which seem to be completely broken).
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1922 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-01-17 16:48:45 +00:00
|
|
|
int pos = 0, lines = 0, curVal;
|
|
|
|
string curLabel;
|
|
|
|
char line[1024];
|
|
|
|
|
|
|
|
ifstream in(file.c_str());
|
|
|
|
if(!in.is_open())
|
|
|
|
return "Unable to read symbols from " + file;
|
|
|
|
|
|
|
|
myUserAddresses.clear();
|
|
|
|
myUserLabels.clear();
|
|
|
|
|
|
|
|
while( !in.eof() )
|
|
|
|
{
|
|
|
|
curVal = 0;
|
|
|
|
curLabel = "";
|
|
|
|
|
|
|
|
int got = in.get();
|
|
|
|
|
|
|
|
if(got == -1 || got == '\r' || got == '\n' || pos == 1023) {
|
|
|
|
line[pos] = '\0';
|
|
|
|
pos = 0;
|
|
|
|
|
|
|
|
if(strlen(line) > 0 && line[0] != '-')
|
|
|
|
{
|
|
|
|
curLabel = extractLabel(line);
|
|
|
|
if((curVal = extractValue(line)) < 0)
|
|
|
|
return "invalid symbol file";
|
|
|
|
|
|
|
|
addLabel(curLabel, curVal);
|
|
|
|
|
|
|
|
lines++;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
line[pos++] = got;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
in.close();
|
|
|
|
return "loaded " + file + " OK";
|
|
|
|
}
|
|
|
|
|
|
|
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
|
|
|
int CartDebug::countCompletions(const char *in)
|
|
|
|
{
|
2010-02-28 17:12:16 +00:00
|
|
|
/* FIXME
|
OK, this is the first pass at a huge reorganization of the debugger
classes. First off, the distella code has been integrated into a
DiStella class. This code isn't yet tied to the debugger, but it does
at least compile and generate valid output.
The RamDebug class has been replaced by a CartDebug class, which
takes responsibility for the previous RamDebug stuff as well as
things related to Cart address space (read from write ports,
disassembly, etc).
Fixed E7 bankswitching when reading from the write port in the upper
256byte area.
Fixed 'read from write port functionality' in general for all carts
that supported it previously. Basically, if _rwport is enabled, the
address is checked to be an actual read (vs. one that's part of a
normal write cycle), *and* it's actually an illegal access (each
cart/bankswitch type now provides a hint to indicate this condition).
Still TODO is clean up the rework, properly integrate DiStella, and
fix labels and defines (which seem to be completely broken).
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1922 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-01-17 16:48:45 +00:00
|
|
|
myCompletions = myCompPrefix = "";
|
|
|
|
return countCompletions(in, mySystemAddresses) +
|
|
|
|
countCompletions(in, myUserAddresses);
|
2010-02-28 17:12:16 +00:00
|
|
|
*/
|
|
|
|
return 0;
|
OK, this is the first pass at a huge reorganization of the debugger
classes. First off, the distella code has been integrated into a
DiStella class. This code isn't yet tied to the debugger, but it does
at least compile and generate valid output.
The RamDebug class has been replaced by a CartDebug class, which
takes responsibility for the previous RamDebug stuff as well as
things related to Cart address space (read from write ports,
disassembly, etc).
Fixed E7 bankswitching when reading from the write port in the upper
256byte area.
Fixed 'read from write port functionality' in general for all carts
that supported it previously. Basically, if _rwport is enabled, the
address is checked to be an actual read (vs. one that's part of a
normal write cycle), *and* it's actually an illegal access (each
cart/bankswitch type now provides a hint to indicate this condition).
Still TODO is clean up the rework, properly integrate DiStella, and
fix labels and defines (which seem to be completely broken).
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1922 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-01-17 16:48:45 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
|
|
|
int CartDebug::countCompletions(const char *in, LabelToAddr& addresses)
|
|
|
|
{
|
|
|
|
int count = 0;
|
|
|
|
|
|
|
|
LabelToAddr::iterator iter;
|
|
|
|
for(iter = addresses.begin(); iter != addresses.end(); iter++)
|
|
|
|
{
|
|
|
|
const char *l = iter->first.c_str();
|
|
|
|
|
|
|
|
if(BSPF_strncasecmp(l, in, strlen(in)) == 0)
|
|
|
|
{
|
|
|
|
if(myCompPrefix == "")
|
|
|
|
myCompPrefix += l;
|
|
|
|
else
|
|
|
|
{
|
|
|
|
int nonMatch = 0;
|
|
|
|
const char *c = myCompPrefix.c_str();
|
|
|
|
while(*c != '\0' && tolower(*c) == tolower(l[nonMatch]))
|
|
|
|
{
|
|
|
|
c++;
|
|
|
|
nonMatch++;
|
|
|
|
}
|
|
|
|
myCompPrefix.erase(nonMatch, myCompPrefix.length());
|
|
|
|
}
|
|
|
|
|
|
|
|
if(count++) myCompletions += " ";
|
|
|
|
myCompletions += l;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return count;
|
|
|
|
}
|
|
|
|
|
2010-02-28 17:12:16 +00:00
|
|
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
|
|
|
CartDebug::AddrType CartDebug::addressType(uInt16 addr) const
|
|
|
|
{
|
|
|
|
// Determine the type of address to access the correct list
|
|
|
|
// These addresses were based on (and checked against) Kroko's 2600 memory
|
|
|
|
// map, found at http://www.qotile.net/minidig/docs/2600_mem_map.txt
|
|
|
|
AddrType type = ADDR_ROM;
|
|
|
|
if(addr % 0x2000 < 0x1000)
|
|
|
|
{
|
|
|
|
uInt16 z = addr & 0x00ff;
|
|
|
|
if(z < 0x80)
|
|
|
|
type = ADDR_TIA;
|
|
|
|
else
|
|
|
|
{
|
|
|
|
switch(addr & 0x0f00)
|
|
|
|
{
|
|
|
|
case 0x000:
|
|
|
|
case 0x100:
|
|
|
|
case 0x400:
|
|
|
|
case 0x500:
|
|
|
|
case 0x800:
|
|
|
|
case 0x900:
|
|
|
|
case 0xc00:
|
|
|
|
case 0xd00:
|
|
|
|
type = ADDR_RAM;
|
|
|
|
break;
|
|
|
|
case 0x200:
|
|
|
|
case 0x300:
|
|
|
|
case 0x600:
|
|
|
|
case 0x700:
|
|
|
|
case 0xa00:
|
|
|
|
case 0xb00:
|
|
|
|
case 0xe00:
|
|
|
|
case 0xf00:
|
|
|
|
type = ADDR_RIOT;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return type;
|
|
|
|
}
|
|
|
|
|
OK, this is the first pass at a huge reorganization of the debugger
classes. First off, the distella code has been integrated into a
DiStella class. This code isn't yet tied to the debugger, but it does
at least compile and generate valid output.
The RamDebug class has been replaced by a CartDebug class, which
takes responsibility for the previous RamDebug stuff as well as
things related to Cart address space (read from write ports,
disassembly, etc).
Fixed E7 bankswitching when reading from the write port in the upper
256byte area.
Fixed 'read from write port functionality' in general for all carts
that supported it previously. Basically, if _rwport is enabled, the
address is checked to be an actual read (vs. one that's part of a
normal write cycle), *and* it's actually an illegal access (each
cart/bankswitch type now provides a hint to indicate this condition).
Still TODO is clean up the rework, properly integrate DiStella, and
fix labels and defines (which seem to be completely broken).
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1922 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-01-17 16:48:45 +00:00
|
|
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
|
|
|
string CartDebug::extractLabel(char *c) const
|
|
|
|
{
|
|
|
|
string l = "";
|
|
|
|
while(*c != ' ')
|
|
|
|
l += *c++;
|
|
|
|
|
|
|
|
return l;
|
|
|
|
}
|
|
|
|
|
|
|
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
|
|
|
int CartDebug::extractValue(char *c) const
|
|
|
|
{
|
|
|
|
while(*c != ' ')
|
|
|
|
{
|
|
|
|
if(*c == '\0')
|
|
|
|
return -1;
|
|
|
|
c++;
|
|
|
|
}
|
|
|
|
|
|
|
|
while(*c == ' ')
|
|
|
|
{
|
|
|
|
if(*c == '\0')
|
|
|
|
return -1;
|
|
|
|
c++;
|
|
|
|
}
|
|
|
|
|
|
|
|
int ret = 0;
|
|
|
|
for(int i=0; i<4; i++)
|
|
|
|
{
|
|
|
|
if(*c >= '0' && *c <= '9')
|
|
|
|
ret = (ret << 4) + (*c) - '0';
|
|
|
|
else if(*c >= 'a' && *c <= 'f')
|
|
|
|
ret = (ret << 4) + (*c) - 'a' + 10;
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else
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return -1;
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c++;
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}
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return ret;
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}
|
2010-02-28 17:12:16 +00:00
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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const char* CartDebug::ourTIAMnemonicR[16] = {
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"CXM0P", "CXM1P", "CXP0FB", "CXP1FB", "CXM0FB", "CXM1FB", "CXBLPF", "CXPPMM",
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"INPT0", "INPT1", "INPT2", "INPT3", "INPT4", "INPT5", "$0E", "$0F"
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};
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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const char* CartDebug::ourTIAMnemonicW[64] = {
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"VSYNC", "VBLANK", "WSYNC", "RSYNC", "NUSIZ0", "NUSIZ1", "COLUP0", "COLUP1",
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"COLUPF", "COLUBK", "CTRLPF", "REFP0", "REFP1", "PF0", "PF1", "PF2",
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"RESP0", "RESP1", "RESM0", "RESM1", "RESBL", "AUDC0", "AUDC1", "AUDF0",
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"AUDF1", "AUDV0", "AUDV1", "GRP0", "GRP1", "ENAM0", "ENAM1", "ENABL",
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"HMP0", "HMP1", "HMM0", "HMM1", "HMBL", "VDELP0", "VDELP1", "VDELBL",
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"RESMP0", "RESMP1", "HMOVE", "HMCLR", "CXCLR", "$2D", "$2E", "$2F",
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"$30", "$31", "$32", "$33", "$34", "$35", "$36", "$37",
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"$38", "$39", "$3A", "$3B", "$3C", "$3D", "$3E", "$3F"
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};
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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|
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const char* CartDebug::ourIOMnemonic[24] = {
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|
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"SWCHA", "SWACNT", "SWCHB", "SWBCNT", "INTIM", "TIMINT", "$0286", "$0287",
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|
"$0288", "$0289", "$028A", "$028B", "$028C", "$028D", "$028E", "$028F",
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"$0290", "$0291", "$0292", "$0293", "TIM1T", "TIM8T", "TIM64T", "T1024T"
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};
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