Commit Graph

1578 Commits

Author SHA1 Message Date
Summate 65a9097980
Allowing a paste into a number field to be trimmed automatically (#2414)
The specific issue I experienced is that Excel/LibreOffice Calc add a newline when you copy the contents of a single cell. This is bad behavior and they should provide a copy option that does not do that, but alas, it's much harder to get that into those applications. This behavior made it impossible to paste an otherwise-valid hex address into the Project64 fields without first putting it into Notepad, deleting the newline, recopying, and then doing the paste from there. If the field was simply text, you can go into the field edit and shift + home to select all and then do a copy, but that does not work for a formula. When you edit the file, it shows the formula instead. Therefore, you have absolutely no way of working around this except pasting it somewhere else and removing the newline manually.

In principle, there's no reason why you wouldn't trim the ends at least. Whitespace on either end is useless to you. However, content being after the newline should be rejected as it was before.

There were two secondary issues in the pasting code that are fixed here: One is that it only sort of collapsed single spaces. So if you had more than one space, spaces still would have ended up in the result. Actually I think the semantics were slightly more insidious, <space><number> would have turned into <number><same number> effectively. The only thing it did was remove the space by duplicating the number. If you had two spaces, then it would have ended up with e.g. <space><number><same number>. The only case where this wouldn't have happened is a space at the end which would have been preserved in the paste.

Secondly, it mutated the clipboard data directly. This would have lead to confusing results where multiple pastes would have had clipboard data in the clipboard itself move from, for example, two spaces to a single space to no spaces at all. The better solution is to preprocess to figure out how big we ultimately want our space-less result to be and stamp out the copy ourselves skipping anything we don't want. Leave the clipboard alone.

If it's desired to preserve single spaces only in the middle, the code will need to be modified a bit.

Co-authored-by: Summate <summate.ssbm@gmail.com>
2024-06-06 14:22:26 +09:30
zilmar 91f9cdaaa7 Core: Change the Program counter to be 64bit 2024-06-06 14:09:12 +09:30
zilmar 703a09d034 Core: Remove protecting memory option 2024-05-09 17:56:28 +09:30
zilmar c786bc3251 Core: Force Fpu exception in recompiler 2024-05-02 16:34:13 +09:30
zilmar 8e3fb3e302 Core: Have R4300iInstruction::WritesGPR return the register written to instead of passing a variable by reference 2023-12-21 10:26:10 +10:30
zilmar 5fec3f8d31 Core: remove the global of g_TLB 2023-12-14 12:09:24 +10:30
Derek "Turtle" Roe acbb8f85a8
Fix typo in support window code (#2395)
* Fix typo in support window

* Fix the typo for real
2023-11-23 22:54:19 +10:30
zilmar 8f4f434820 Core: Get Fast tlb to just be 32bit 2023-11-16 17:11:05 +10:30
zilmar a0130ff896 Core: Convert %I64U to %llx 2023-11-16 09:03:32 +10:30
zilmar ae0097550f Core: Make R4300iOp opcodes not static 2023-10-19 11:43:32 +10:30
zilmar 9f07fe2aac Core: Get tlb addresses to be 64bit 2023-10-05 13:42:31 +10:30
zilmar 4b844495b7 Core: Have save states handle COP0/TLB being 64bit now
Core: Clean up tlb class
2023-10-05 13:10:45 +10:30
zilmar f559aed2ad Core: Get CRegisters::DoAddressError, CRegisters::DoTLBReadMiss, CRegisters::DoTLBWriteMiss to use TriggerException function 2023-09-14 16:23:26 +09:30
zilmar fcd7257adc Core: Change COP0 Status register to a struct breaking up the bits 2023-09-14 10:23:36 +09:30
zilmar c28c6bb4a1 Core: Add fpu exceptions to COP1_S_ADD 2023-08-31 10:08:49 +09:30
Squall Leonhart 562d4d4e56
Make the FPU Register Caching checkbox functional (#2377)
Adds missing line from SettingsPage-Game-Recompiler.h
Corrects entry in SettingsPage-Game-Recompiler.cpp to Game_FPURegCache
Removes : from Language file entry.
2023-07-27 09:07:14 +09:30
zilmar ef24ec11d8 Rename RSP to Project64-rsp 2023-06-15 14:45:27 +09:30
zilmar ab8b004b71 Core: Add a setting for fpu reg caching 2023-04-17 18:47:33 +09:30
zilmar 7f7aee7232 Core: remove FAKE_CAUSE_REGISTER 2023-03-14 12:14:10 +10:30
David Benepe 96792b18c8
Fixed DPI scaling issue in some debugger windows (#2353) 2023-03-12 16:58:32 +10:30
zilmar a25e5ca4c0 x64: Fix rom browser showing columns 2023-03-04 07:19:35 +10:30
zilmar ea70218d1c Clean up warnings 2023-02-28 10:09:08 +10:30
jarupxx 3aef396007
Add editbox to choose directory dialog (#2340) 2023-02-14 08:12:38 +10:30
zilmar 4390a0926c Remove _Pairib usage 2023-02-13 08:55:56 +10:30
zilmar 210ebd42de Core: have an option for rdram to be different between known and unknown roms 2023-01-16 20:53:48 +10:30
zilmar f6e4443dda Core: Revert Unaligned DMA to fix some hacks 2022-12-26 15:15:28 +10:30
zilmar 620aabcf9e Core: Add clang script and check on building release 2022-12-19 15:51:02 +10:30
zilmar c0341bb759 Core: Code clean up for clang 2022-12-19 15:35:17 +10:30
zilmar ae62981aef Core: Remove unaligned dma 2022-12-19 10:15:31 +10:30
zilmar cbacddb65e Core: Make 32bit CPU recompiler only setting 2022-12-19 09:07:26 +10:30
Johan Mattsson c100d527fc
Small fixes (#2314)
* Assign the null pointer

* Initialize variable

* Fix while-conditions
2022-12-05 19:33:48 +10:30
zilmar d35d2e6abe Core: Move ReadsGPR, WritesGPR, ReadsHI(), ReadsLO(), WritesHI(), WritesLO() out of OpInfo and into R4300iInstruction 2022-12-05 12:23:09 +10:30
zilmar 529812fdca Core: Switch to use asmjit registers in recompiler 2022-11-07 21:03:32 +10:30
zilmar c16307ec0f Core: Move Pifram code into PifRamHandler 2022-10-17 08:27:52 +10:30
zilmar 761a1ee52a Code clean up 2022-10-10 10:52:17 +10:30
zilmar 3f681101f6 Project64: Missed some files in code cleanup 2022-09-26 12:02:33 +09:30
zilmar 179282043f Project64: Code cleanup 2022-09-26 12:01:54 +09:30
zilmar a65086579f Project64: Code clean up 2022-09-21 14:46:07 +09:30
zilmar a2981ff4d8 Core: Make Load/Store use 64bit vaddr 2022-09-19 21:36:36 +09:30
zilmar 1c77f6f0fd Core: Make Cop0 64bit 2022-09-19 16:36:44 +09:30
zilmar 8a01017ef5 UI: Update rombrowser windows so controls are vertical 2022-09-05 17:55:43 +09:30
zilmar f7b1891c91 Core: Add base 64bit Recompiler classes 2022-08-29 17:57:17 +09:30
zilmar 52a30b78fb Core: Handle div/0 better 2022-08-22 22:13:53 +09:30
Squall Leonhart cc2aa4783a
add [f] to good name in lines with goodtool codes, and updates rom information window for M-type carts. (#2275)
* add [f] to good name in lines with goodtool codes.

* added M type media to Rom Information.

so it doesn't show (Unknown)
2022-08-15 21:25:14 +09:30
Squall Leonhart 630778a41e
media id patched dragon sword 64 U added to rdb (#2274)
* media id patched dragon sword 64 U added to rdb

* adds M Type Cartridge media as N64 Development Cartridge

* adds unpatched Dragon Sword U and differentiates the two
2022-08-11 12:35:27 +09:30
zilmar cd3b326a83 Project64: Move menu options from notification to r43000 2022-08-08 18:51:09 +09:30
zilmar 0419ba232e Core: Add option to step code at break opcode 2022-08-01 11:43:17 +09:30
zilmar 4b60f4f3e9 UI: Always show rom information 2022-08-01 11:25:32 +09:30
zilmar b987a1693c Core: Do not end emulation by default on perm loop 2022-08-01 10:59:16 +09:30
zilmar 10d23486c6 Core: Add option to break on address exception 2022-08-01 10:38:12 +09:30