MegaMech
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0761ad4a83
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Fix implementation of quad3d for f3dex 0.95 on pj64 video plugin (#2427)
* Update ucode01.cpp
* Fix quad3d implementation for f3dex 0.95
* Fix compile
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2024-06-06 14:20:46 +09:30 |
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zilmar
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91f9cdaaa7
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Core: Change the Program counter to be 64bit
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2024-06-06 14:09:12 +09:30 |
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zilmar
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77ac4744a5
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Core: Make sure fpu stack is being cleared
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2024-05-23 11:52:58 +09:30 |
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zilmar
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0ff0d5234c
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Core: In R4300iOp::CheckFPUInput64 check values directly instead of using fpclassify
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2024-05-23 11:43:19 +09:30 |
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zilmar
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ec714cd90d
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Core: in CX86RecompilerOps::CompileCheckFPUResult64 protect RegPointer before Map_TempReg(asmjit::x86::eax)
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2024-05-23 11:41:15 +09:30 |
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zilmar
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3baaa829de
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Core: Remove g_TLBLoadAddress, g_TLBStoreAddress global variables
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2024-05-16 16:34:17 +09:30 |
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zilmar
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ae21e10a8d
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Core: Increase the minimal amount of free space in recompiler memory
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2024-05-16 16:15:28 +09:30 |
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zilmar
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a1f46356fb
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Core: remove usage of g_RecompPos
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2024-05-16 16:08:23 +09:30 |
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zilmar
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7f18773b5b
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Core: Add CX86RegInfo::GetFPStatusReg
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2024-05-16 15:51:04 +09:30 |
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zilmar
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13bd420b2a
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Core: Sync FP status register in advanced block linking
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2024-05-16 15:45:38 +09:30 |
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zilmar
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703a09d034
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Core: Remove protecting memory option
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2024-05-09 17:56:28 +09:30 |
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zilmar
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f478f16269
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Core: Clear FP Status flag in recompiler on BC1FL and BC1TL
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2024-05-09 10:55:38 +09:30 |
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zilmar
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4c23e7af2c
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Core: Remove ChangeFPURegFormat, Load_FPR_ToTop
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2024-05-02 17:21:01 +09:30 |
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zilmar
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c786bc3251
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Core: Force Fpu exception in recompiler
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2024-05-02 16:34:13 +09:30 |
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zilmar
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b3e8b760e6
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Core: get COP1_S_TRUNC_L, COP1_S_CEIL_L, COP1_S_FLOOR_L, COP1_W_CVT_S, COP1_W_CVT_D, COP1_L_CVT_S, COP1_L_CVT_D to use COP1_S_CVT function
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2024-05-02 15:48:43 +09:30 |
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zilmar
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dd0f7ad776
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Core: Have CX86RecompilerOps::COP1_S_CVT be able to handle the old format of FPU_Dword and FPU_Qword
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2024-05-02 15:46:03 +09:30 |
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zilmar
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046f27ce98
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Core: fix up some bugs in CX86RecompilerOps::COP1_S_CVT
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2024-04-25 20:47:02 +09:30 |
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zilmar
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627b4d6103
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Core: Get CompileCheckFPUInput check InvalidValueMax, InvalidMinValue in conv
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2024-04-25 20:41:03 +09:30 |
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zilmar
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b92e6bd752
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Core: get to COP1_S_ROUND_L and COP1_S_CVT_L to use COP1_S_CVT
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2024-04-25 20:22:47 +09:30 |
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zilmar
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d658477cf4
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Core: get CX86RecompilerOps::Compile_Branch to clear status flags
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2024-04-18 17:31:19 +09:30 |
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zilmar
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b313640831
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Core: In CX86RegInfo::Map_TempReg allow it to use FPStatusReg if it is unprotected
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2024-04-18 17:28:23 +09:30 |
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zilmar
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1172b6e04d
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Core: get CX86RecompilerOps::SW_Const on 0x04300000 to call MIPSInterfaceHandler directly
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2024-04-18 17:21:39 +09:30 |
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zilmar
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38738b783d
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Core: get CX86RecompilerOps::COP1_S_CVT to handle NewFormat == CRegInfo::FPU_Qword
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2024-04-18 17:11:45 +09:30 |
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zilmar
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7dc53e51cf
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Core: Get CompileCheckFPUInput to better handle 64bit value check
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2024-04-18 17:00:29 +09:30 |
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zilmar
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a9875b7d61
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Core: Get COP1_D_CMP to map eax before CompileInitFpuOperation
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2024-04-18 16:58:18 +09:30 |
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zilmar
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3203322d8b
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Core: Get COP1_D_CVT_L to use COP1_S_CVT
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2024-04-18 16:56:30 +09:30 |
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zilmar
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9e73771815
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Core: Use the new COP1_S_CVT in COP1_D_ROUND_L, COP1_D_TRUNC_L, COP1_D_CEIL_L, COP1_D_FLOOR_L
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2024-04-18 16:51:53 +09:30 |
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zilmar
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fe87142657
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Core: CX86RecompilerOps::COP1_S_CMP should allocate eax before calling CompileInitFpuOperation
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2024-04-18 16:42:48 +09:30 |
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zilmar
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4071b52810
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Core: CX86RegInfo::UnMap_X86reg should fail on a protected register
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2024-04-18 16:41:03 +09:30 |
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zilmar
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79f7aa9927
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Core: CX86RegInfo::UnMap_FPStatusReg should unprotect register before trying to free it
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2024-04-18 16:34:49 +09:30 |
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zilmar
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0cf4c7dc11
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Core: get COP1_D_CMP to work in recompiler
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2024-04-11 18:14:44 +09:30 |
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zilmar
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9272ac05f6
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Core: refactor S opcodes to one central function
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2024-04-11 18:09:30 +09:30 |
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zilmar
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e7178dbdec
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Core: Fix CX86RecompilerOps::COP1_D_CVT_S
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2024-03-28 20:05:27 +10:30 |
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zilmar
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8bb2445263
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Core: Have CX86RecompilerOps::CompileCheckFPUResult32 write to the high word
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2024-03-28 20:02:24 +10:30 |
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François Berder
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560c49ba2d
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Core: Fix N64 disk IPL load address check (#2401)
The IPL load address check always evaluated to false due
to a wrong operator.
Signed-off-by: Francois Berder <fberder@outlook.fr>
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2024-03-21 17:52:09 +10:30 |
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zilmar
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45fb2ad965
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Core: In X86RecompilerOps::CompileCheckFPUResult64 make sure RegPointer is protected
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2024-03-21 17:44:53 +10:30 |
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zilmar
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2811b63ff0
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Core: Update CX86RecompilerOps::COP1_D_CVT_S and CX86RecompilerOps::COP1_D_CVT_W
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2024-03-21 17:41:29 +10:30 |
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zilmar
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33d2722841
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Core: fix up CX86RecompilerOps::COP1_D_FLOOR_W
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2024-03-21 17:40:14 +10:30 |
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zilmar
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9a9c2e5439
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Core: Update CX86RecompilerOps::COP1_D_CEIL_W
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2024-03-21 17:32:12 +10:30 |
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zilmar
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401efae0d9
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Core: fix up CX86RecompilerOps::COP1_D_ROUND_W
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2024-03-21 17:28:16 +10:30 |
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zilmar
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772a20f07d
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Core: Update CX86RecompilerOps::COP1_D_SQRT
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2024-03-21 17:15:10 +10:30 |
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zilmar
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87c732b65d
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Core: update CX86RecompilerOps::COP1_D_NEG
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2024-03-21 17:14:00 +10:30 |
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zilmar
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ece5e30a80
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Core: create a function to handle .d recompiler opcodes that use fd and fs
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2024-03-21 17:13:16 +10:30 |
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zilmar
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5133d47502
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Core: Make the FPU double ops to be modularized so it is a simple function call for an opcode
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2024-03-14 18:12:58 +10:30 |
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zilmar
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98b1bddc64
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Core: Get COP1_D_ADD, COP1_D_SUB, COP1_D_DIV, COP1_D_ABS, COP1_D_SQRT
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2024-03-07 21:12:57 +10:30 |
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zilmar
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97ec1f533b
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Core: Make sure precision is set to 53bit
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2024-03-07 20:52:24 +10:30 |
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zilmar
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190c408019
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Core: Fix clang formatting in x86/x86RecompilerOps.cpp
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2024-02-29 16:06:56 +10:30 |
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zilmar
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f7aa6ef6cb
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Core: Fix up CX86RecompilerOps::COP1_D_MUL so it can work with exceptions
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2024-02-29 15:16:29 +10:30 |
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zilmar
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25dc3ed36f
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Core: CRegisters::TriggerAddressException should only generate a TLB_MOD on writes
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2024-02-29 15:13:14 +10:30 |
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zilmar
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d2649f7a13
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Core: Some clean up recompiler ops
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2024-02-22 19:56:23 +10:30 |