zilmar
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d35d2e6abe
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Core: Move ReadsGPR, WritesGPR, ReadsHI(), ReadsLO(), WritesHI(), WritesLO() out of OpInfo and into R4300iInstruction
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2022-12-05 12:23:09 +10:30 |
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zilmar
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761a1ee52a
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Code clean up
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2022-10-10 10:52:17 +10:30 |
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zilmar
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05d46c9487
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Core: Handle reserve instruction 31
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2022-09-19 12:12:08 +09:30 |
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zilmar
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4218cbad23
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Core: R4300iInstruction::DecodeSpecialName - Fix up SLL param
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2022-08-29 08:27:47 +09:30 |
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zilmar
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d37d0dc7a5
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Core: Dissasm of DMFC0 was showing the wrong reg
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2022-08-01 10:02:07 +09:30 |
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zilmar
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09b535551d
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Core: Move DelaySlotEffectsCompare into R4300iInstruction
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2022-07-25 16:35:42 +09:30 |
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zilmar
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0abc7ccaa4
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Core: Move OpHasDelaySlot into R4300iInstruction
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2022-07-25 14:23:12 +09:30 |
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zilmar
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1a8a4dd50f
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Core: Fix some bugs added to R4300iInstruction Param
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2022-07-25 11:57:19 +09:30 |
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zilmar
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7f3b8e3601
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Core: Start to add R4300iInstruction to do analysis of an opcode
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2022-07-18 18:01:00 +09:30 |