zilmar
|
eb985de132
|
RSP: Start to add CPU style HLE
|
2024-08-29 15:37:52 +09:30 |
|
zilmar
|
5eac210197
|
RSP: Start to have a RSP Settings class
|
2024-08-29 11:26:53 +09:30 |
|
zilmar
|
96080bfdd2
|
RSP: change CRSPSystem::m_Recompiler from a pointer to a member and initialize it at creation of system
|
2024-08-29 07:49:40 +09:30 |
|
zilmar
|
2b7975280e
|
RSP: Have NextInstruction and JumpTo members of RSP System instead of a global variable
|
2024-08-22 19:44:07 +09:30 |
|
zilmar
|
29c49a2063
|
RSP: Remove PrgCount as a global
|
2024-08-22 17:32:05 +09:30 |
|
zilmar
|
d9ae43b69d
|
RSP: have RSPRegisterHandlerPlugin as part of RSP System instead of a global
|
2024-08-22 16:30:20 +09:30 |
|
zilmar
|
4681f07bf8
|
RSP: Move rdp logging in to it's own class
|
2024-08-15 13:43:56 +09:30 |
|
zilmar
|
6ed1c3edfb
|
RSP: internalize RSP information in to interpter ops
|
2024-08-15 07:36:53 +09:30 |
|
zilmar
|
9f98f4d4cd
|
Rsp: Change RSPOpC to be a class member
|
2024-08-08 12:55:54 +09:30 |
|
zilmar
|
762d1b1566
|
RSP: Create CRSPRecompiler
|
2024-08-08 09:39:45 +09:30 |
|
zilmar
|
f7ab608976
|
RSP: Create CRSPRegisters
|
2024-08-08 07:26:15 +09:30 |
|
zilmar
|
1924030266
|
RSP: Move compile functions into CRSPRecompilerOps
|
2024-08-02 22:00:01 +09:30 |
|
zilmar
|
2904d3641d
|
RSP: Create RSP system class and move all interpter ops in to RSPOp class
|
2024-08-02 09:00:38 +09:30 |
|
zilmar
|
dab432e7bd
|
RSP: clean up LDV
|
2024-07-20 19:10:36 +09:30 |
|
zilmar
|
9d7b391487
|
RSP: Fix up LSV in the recompiler
|
2024-07-20 17:09:41 +09:30 |
|
zilmar
|
7c2655c544
|
RSP: Remove some unused functions and turn Reordering and Sections off by default
|
2024-07-20 17:08:20 +09:30 |
|
zilmar
|
6816ff4435
|
RSP: Disable a lot of ops that are not functioning correctly in the recompiler
|
2024-07-20 17:05:11 +09:30 |
|
zilmar
|
13fb8cd2da
|
RSP: In Compile_Opcode_SQV Cheat the op instead of causing an unknown opcode
|
2024-07-12 15:23:59 +09:30 |
|
zilmar
|
564926163c
|
RSP: in Compile_Opcode_SSV cheat the op instead of generating an unknown opcode
|
2024-07-12 15:07:23 +09:30 |
|
zilmar
|
8c6856f1c8
|
RSP: Have Compile_SW handle DMEM overflow better
|
2024-07-12 15:04:18 +09:30 |
|
zilmar
|
6e4852fc78
|
RSP: have Compile_LW handle DMEM overflow better
|
2024-07-12 15:02:46 +09:30 |
|
zilmar
|
e43d697476
|
RSP: Handle lwu inside IsRegisterConstant
|
2024-07-12 15:01:05 +09:30 |
|
zilmar
|
7b013c3deb
|
RSP: Reset secondary buffer to start on ResetJumpTables
|
2024-07-12 14:59:16 +09:30 |
|
zilmar
|
e2243fe8eb
|
RSP: Make sure RSP block ends with a ret
|
2024-07-06 19:36:10 +09:30 |
|
zilmar
|
9b38977b31
|
RSP: Fix up recompiler jumps JAL, BLTZAL, BGEZAL
|
2024-07-06 19:33:10 +09:30 |
|
zilmar
|
4125774be8
|
RSP: Add Vector_VRNDN and fix up compile jump table
|
2024-07-06 19:08:20 +09:30 |
|
zilmar
|
2a149beb69
|
RSP: Clean up #ifdef in Recompiler
|
2024-07-06 19:04:50 +09:30 |
|
zilmar
|
38599b79fe
|
RSP: Compile_Cop2_MF check for write to r0
|
2024-07-06 18:53:19 +09:30 |
|
zilmar
|
1af8570315
|
RSP: Set max log size as 300mb
|
2024-07-06 18:51:55 +09:30 |
|
zilmar
|
0e0f0f7618
|
RSP: JALR update rd after updating the PC
|
2024-06-27 16:57:31 +09:30 |
|
zilmar
|
06eea03d7d
|
RSP: DelaySlotAffectBranch should clamp PC
|
2024-06-27 16:34:19 +09:30 |
|
zilmar
|
661ec98bb3
|
RSP: User crc32 for crc of imem
|
2024-06-27 16:25:13 +09:30 |
|
zilmar
|
96a4c2c926
|
RSP: Used the wrong reg for write to r0 check on some ops
|
2024-06-20 21:41:52 +09:30 |
|
zilmar
|
abfb896142
|
RSP: Add Compile_Vector_VRNDP, Compile_Vector_VMULQ, Compile_Opcode_LWV
|
2024-06-20 19:22:57 +09:30 |
|
zilmar
|
90c0beb01e
|
RSP: Add Compile_Vector_Reserved
|
2024-06-20 17:34:37 +09:30 |
|
zilmar
|
35aeeb6285
|
RSP: Handle writing to r0 better in recompiler
|
2024-06-20 17:28:51 +09:30 |
|
zilmar
|
bb042406be
|
RSP: Add const to mmx and sse terms
|
2024-06-13 20:50:54 +09:30 |
|
zilmar
|
303af24bde
|
RSP: Better handle delay slot at 0xFFC
|
2024-06-13 14:54:44 +09:30 |
|
zilmar
|
c3d6ed1a0c
|
RSP: Have the code be able to loop
|
2024-06-13 14:23:59 +09:30 |
|
zilmar
|
7161a6f591
|
RSP: Handle break in delay slot
|
2024-06-13 12:55:23 +09:30 |
|
zilmar
|
d3411809f7
|
RSP: Get Recompiler to use LWU
|
2024-06-13 12:34:28 +09:30 |
|
zilmar
|
71067ccdc4
|
Rsp: Change how SP_SEMAPHORE_REG to how it use to be before adding multithread RSP
|
2024-01-11 18:17:05 +10:30 |
|
zilmar
|
5c56f9df83
|
RSP: Update the size of the skip in the length for DMA
|
2024-01-11 17:50:23 +10:30 |
|
zilmar
|
e46ffde6b3
|
fix clang formatting
|
2023-11-09 12:59:40 +10:30 |
|
zilmar
|
296b7cf1cf
|
Android: Force RSP to be interpret
|
2023-11-09 12:45:36 +10:30 |
|
zilmar
|
0c8b10bbc7
|
Android: Get RSP core to compile on android
|
2023-11-09 11:53:06 +10:30 |
|
zilmar
|
09cc3442a2
|
Android: fix compile bug
|
2023-11-02 20:27:38 +10:30 |
|
zilmar
|
6fbc5c0264
|
Android: Move hle audio code in to main rsp plugin
|
2023-11-02 20:06:58 +10:30 |
|
zilmar
|
a975af0e3c
|
Rsp: only use alignas for Visual Studio
|
2023-09-28 16:18:39 +09:30 |
|
zilmar
|
dd7ec63dd9
|
Rsp: Change usage of alignas to try and fix android build
|
2023-09-28 15:53:46 +09:30 |