zilmar
|
aaa6fc8082
|
Core: Add $(Platform) to the output directory
|
2024-09-05 17:54:58 +09:30 |
|
zilmar
|
6816ff4435
|
RSP: Disable a lot of ops that are not functioning correctly in the recompiler
|
2024-07-20 17:05:11 +09:30 |
|
zilmar
|
73c9174ce9
|
Core: Remove Memory exception filer
|
2024-06-13 11:50:06 +09:30 |
|
zilmar
|
91f9cdaaa7
|
Core: Change the Program counter to be 64bit
|
2024-06-06 14:09:12 +09:30 |
|
zilmar
|
77ac4744a5
|
Core: Make sure fpu stack is being cleared
|
2024-05-23 11:52:58 +09:30 |
|
zilmar
|
0ff0d5234c
|
Core: In R4300iOp::CheckFPUInput64 check values directly instead of using fpclassify
|
2024-05-23 11:43:19 +09:30 |
|
zilmar
|
ec714cd90d
|
Core: in CX86RecompilerOps::CompileCheckFPUResult64 protect RegPointer before Map_TempReg(asmjit::x86::eax)
|
2024-05-23 11:41:15 +09:30 |
|
zilmar
|
3baaa829de
|
Core: Remove g_TLBLoadAddress, g_TLBStoreAddress global variables
|
2024-05-16 16:34:17 +09:30 |
|
zilmar
|
ae21e10a8d
|
Core: Increase the minimal amount of free space in recompiler memory
|
2024-05-16 16:15:28 +09:30 |
|
zilmar
|
a1f46356fb
|
Core: remove usage of g_RecompPos
|
2024-05-16 16:08:23 +09:30 |
|
zilmar
|
7f18773b5b
|
Core: Add CX86RegInfo::GetFPStatusReg
|
2024-05-16 15:51:04 +09:30 |
|
zilmar
|
13bd420b2a
|
Core: Sync FP status register in advanced block linking
|
2024-05-16 15:45:38 +09:30 |
|
zilmar
|
703a09d034
|
Core: Remove protecting memory option
|
2024-05-09 17:56:28 +09:30 |
|
zilmar
|
f478f16269
|
Core: Clear FP Status flag in recompiler on BC1FL and BC1TL
|
2024-05-09 10:55:38 +09:30 |
|
zilmar
|
4c23e7af2c
|
Core: Remove ChangeFPURegFormat, Load_FPR_ToTop
|
2024-05-02 17:21:01 +09:30 |
|
zilmar
|
c786bc3251
|
Core: Force Fpu exception in recompiler
|
2024-05-02 16:34:13 +09:30 |
|
zilmar
|
b3e8b760e6
|
Core: get COP1_S_TRUNC_L, COP1_S_CEIL_L, COP1_S_FLOOR_L, COP1_W_CVT_S, COP1_W_CVT_D, COP1_L_CVT_S, COP1_L_CVT_D to use COP1_S_CVT function
|
2024-05-02 15:48:43 +09:30 |
|
zilmar
|
dd0f7ad776
|
Core: Have CX86RecompilerOps::COP1_S_CVT be able to handle the old format of FPU_Dword and FPU_Qword
|
2024-05-02 15:46:03 +09:30 |
|
zilmar
|
046f27ce98
|
Core: fix up some bugs in CX86RecompilerOps::COP1_S_CVT
|
2024-04-25 20:47:02 +09:30 |
|
zilmar
|
627b4d6103
|
Core: Get CompileCheckFPUInput check InvalidValueMax, InvalidMinValue in conv
|
2024-04-25 20:41:03 +09:30 |
|
zilmar
|
b92e6bd752
|
Core: get to COP1_S_ROUND_L and COP1_S_CVT_L to use COP1_S_CVT
|
2024-04-25 20:22:47 +09:30 |
|
zilmar
|
d658477cf4
|
Core: get CX86RecompilerOps::Compile_Branch to clear status flags
|
2024-04-18 17:31:19 +09:30 |
|
zilmar
|
b313640831
|
Core: In CX86RegInfo::Map_TempReg allow it to use FPStatusReg if it is unprotected
|
2024-04-18 17:28:23 +09:30 |
|
zilmar
|
1172b6e04d
|
Core: get CX86RecompilerOps::SW_Const on 0x04300000 to call MIPSInterfaceHandler directly
|
2024-04-18 17:21:39 +09:30 |
|
zilmar
|
38738b783d
|
Core: get CX86RecompilerOps::COP1_S_CVT to handle NewFormat == CRegInfo::FPU_Qword
|
2024-04-18 17:11:45 +09:30 |
|
zilmar
|
7dc53e51cf
|
Core: Get CompileCheckFPUInput to better handle 64bit value check
|
2024-04-18 17:00:29 +09:30 |
|
zilmar
|
a9875b7d61
|
Core: Get COP1_D_CMP to map eax before CompileInitFpuOperation
|
2024-04-18 16:58:18 +09:30 |
|
zilmar
|
3203322d8b
|
Core: Get COP1_D_CVT_L to use COP1_S_CVT
|
2024-04-18 16:56:30 +09:30 |
|
zilmar
|
9e73771815
|
Core: Use the new COP1_S_CVT in COP1_D_ROUND_L, COP1_D_TRUNC_L, COP1_D_CEIL_L, COP1_D_FLOOR_L
|
2024-04-18 16:51:53 +09:30 |
|
zilmar
|
fe87142657
|
Core: CX86RecompilerOps::COP1_S_CMP should allocate eax before calling CompileInitFpuOperation
|
2024-04-18 16:42:48 +09:30 |
|
zilmar
|
4071b52810
|
Core: CX86RegInfo::UnMap_X86reg should fail on a protected register
|
2024-04-18 16:41:03 +09:30 |
|
zilmar
|
79f7aa9927
|
Core: CX86RegInfo::UnMap_FPStatusReg should unprotect register before trying to free it
|
2024-04-18 16:34:49 +09:30 |
|
zilmar
|
0cf4c7dc11
|
Core: get COP1_D_CMP to work in recompiler
|
2024-04-11 18:14:44 +09:30 |
|
zilmar
|
9272ac05f6
|
Core: refactor S opcodes to one central function
|
2024-04-11 18:09:30 +09:30 |
|
zilmar
|
e7178dbdec
|
Core: Fix CX86RecompilerOps::COP1_D_CVT_S
|
2024-03-28 20:05:27 +10:30 |
|
zilmar
|
8bb2445263
|
Core: Have CX86RecompilerOps::CompileCheckFPUResult32 write to the high word
|
2024-03-28 20:02:24 +10:30 |
|
François Berder
|
560c49ba2d
|
Core: Fix N64 disk IPL load address check (#2401)
The IPL load address check always evaluated to false due
to a wrong operator.
Signed-off-by: Francois Berder <fberder@outlook.fr>
|
2024-03-21 17:52:09 +10:30 |
|
zilmar
|
45fb2ad965
|
Core: In X86RecompilerOps::CompileCheckFPUResult64 make sure RegPointer is protected
|
2024-03-21 17:44:53 +10:30 |
|
zilmar
|
2811b63ff0
|
Core: Update CX86RecompilerOps::COP1_D_CVT_S and CX86RecompilerOps::COP1_D_CVT_W
|
2024-03-21 17:41:29 +10:30 |
|
zilmar
|
33d2722841
|
Core: fix up CX86RecompilerOps::COP1_D_FLOOR_W
|
2024-03-21 17:40:14 +10:30 |
|
zilmar
|
9a9c2e5439
|
Core: Update CX86RecompilerOps::COP1_D_CEIL_W
|
2024-03-21 17:32:12 +10:30 |
|
zilmar
|
401efae0d9
|
Core: fix up CX86RecompilerOps::COP1_D_ROUND_W
|
2024-03-21 17:28:16 +10:30 |
|
zilmar
|
772a20f07d
|
Core: Update CX86RecompilerOps::COP1_D_SQRT
|
2024-03-21 17:15:10 +10:30 |
|
zilmar
|
87c732b65d
|
Core: update CX86RecompilerOps::COP1_D_NEG
|
2024-03-21 17:14:00 +10:30 |
|
zilmar
|
ece5e30a80
|
Core: create a function to handle .d recompiler opcodes that use fd and fs
|
2024-03-21 17:13:16 +10:30 |
|
zilmar
|
5133d47502
|
Core: Make the FPU double ops to be modularized so it is a simple function call for an opcode
|
2024-03-14 18:12:58 +10:30 |
|
zilmar
|
98b1bddc64
|
Core: Get COP1_D_ADD, COP1_D_SUB, COP1_D_DIV, COP1_D_ABS, COP1_D_SQRT
|
2024-03-07 21:12:57 +10:30 |
|
zilmar
|
97ec1f533b
|
Core: Make sure precision is set to 53bit
|
2024-03-07 20:52:24 +10:30 |
|
zilmar
|
190c408019
|
Core: Fix clang formatting in x86/x86RecompilerOps.cpp
|
2024-02-29 16:06:56 +10:30 |
|
zilmar
|
f7aa6ef6cb
|
Core: Fix up CX86RecompilerOps::COP1_D_MUL so it can work with exceptions
|
2024-02-29 15:16:29 +10:30 |