zilmar
|
b3c6858b69
|
Core: Change COP0 registers to use an enum
|
2022-11-07 09:24:58 +10:30 |
|
zilmar
|
fd71b2dfcb
|
Core: Handle branch/jump in a delay slot in the Interpreter
|
2022-11-01 08:59:15 +10:30 |
|
zilmar
|
65bbc375b9
|
Core: Fix R4300iOp::LWC1 to have 64bit address
|
2022-10-17 08:36:17 +10:30 |
|
zilmar
|
761a1ee52a
|
Code clean up
|
2022-10-10 10:52:17 +10:30 |
|
zilmar
|
179282043f
|
Project64: Code cleanup
|
2022-09-26 12:01:54 +09:30 |
|
zilmar
|
a2981ff4d8
|
Core: Make Load/Store use 64bit vaddr
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2022-09-19 21:36:36 +09:30 |
|
zilmar
|
1c77f6f0fd
|
Core: Make Cop0 64bit
|
2022-09-19 16:36:44 +09:30 |
|
zilmar
|
05d46c9487
|
Core: Handle reserve instruction 31
|
2022-09-19 12:12:08 +09:30 |
|
zilmar
|
524f56eda7
|
Core: fix srav in the interpter
|
2022-09-05 17:42:15 +09:30 |
|
zilmar
|
18b9892bc7
|
Core: Add handling of overflow exception
|
2022-09-05 16:35:13 +09:30 |
|
zilmar
|
52a30b78fb
|
Core: Handle div/0 better
|
2022-08-22 22:13:53 +09:30 |
|
zilmar
|
71ddfd885d
|
Core: Add BGEZALL to interrupter
|
2022-08-15 10:18:51 +09:30 |
|
zilmar
|
e724595ac2
|
Core: Add DADDI
|
2022-08-15 10:05:16 +09:30 |
|
zilmar
|
5ea06d958e
|
Core: have SB/SH be able to write to rom handler
|
2022-08-08 19:33:16 +09:30 |
|
zilmar
|
0419ba232e
|
Core: Add option to step code at break opcode
|
2022-08-01 11:43:17 +09:30 |
|
zilmar
|
d6a217ca86
|
Core: fix issue with R4300iOp::SPECIAL_SRA
|
2022-08-01 10:03:06 +09:30 |
|
zilmar
|
09b535551d
|
Core: Move DelaySlotEffectsCompare into R4300iInstruction
|
2022-07-25 16:35:42 +09:30 |
|
zilmar
|
c3cae358a1
|
Core: Open debugger on unknown opcode
|
2022-07-25 14:07:12 +09:30 |
|
zilmar
|
f62f8207ec
|
Core: Initiate PREVID
|
2022-07-18 18:56:52 +09:30 |
|
zilmar
|
7f3b8e3601
|
Core: Start to add R4300iInstruction to do analysis of an opcode
|
2022-07-18 18:01:00 +09:30 |
|
zilmar
|
86aa483a38
|
Core: Move memory exceptions out of interrupter ops and in to Memory Manager
|
2022-06-13 11:24:36 +09:30 |
|
zilmar
|
718d7e0359
|
[Core] Clean up load/store usage in MemoryVirtualMem
|
2022-05-09 10:06:10 +09:30 |
|
zilmar
|
b74a2dc69f
|
[Core] Change TranslateVaddr to VAddrToPAddr
|
2022-05-02 07:36:50 +09:30 |
|
zilmar
|
7fd239cf82
|
Core: Change NextInstruction to PipelineStage
|
2022-01-18 18:17:21 +10:30 |
|
zilmar
|
30a40ea0a8
|
Core: Remove the option to turn off tlb
|
2022-01-10 17:46:01 +10:30 |
|
zilmar
|
40683ecf79
|
Core: Remove legacy code
|
2022-01-05 08:59:12 +10:30 |
|
zilmar
|
ee864797ab
|
vgturtle127's Beautification 14 - Source\Project64-video directory and final cleanup
|
2021-05-18 21:21:36 +09:30 |
|
zilmar
|
c512a592a7
|
Move class out of file names
|
2021-04-14 15:04:15 +09:30 |
|
zilmar
|
cf58754414
|
Change NULL to nullptr
|
2021-04-12 21:05:39 +09:30 |
|
zilmar
|
5c60ea213f
|
Update copyright date
|
2021-03-02 12:43:17 +10:30 |
|
zilmar
|
cd16a8cc48
|
Clean up some warnings
|
2021-01-19 16:28:59 +10:30 |
|
zilmar
|
185c6586b4
|
Project64: Add TLB_WRITE_EXCEPTION
|
2020-03-04 10:33:18 +10:30 |
|
KrimtonZ
|
0baf3ef263
|
Fix Trap Interpreter Functions, add recompiler trap functions
|
2019-12-17 09:08:15 -06:00 |
|
KrimtonZ
|
0e5c771408
|
remove HaveDebugger requirement, remove redundant code
|
2019-12-16 14:59:40 -06:00 |
|
KrimtonZ
|
b9be612ac5
|
add remaining trap instructions, properly implement traps for the interpreter core
|
2019-12-16 14:15:26 -06:00 |
|
oddMLan
|
01d4ed0bc3
|
Change some error message boxes to warnings
|
2019-04-15 08:58:22 -07:00 |
|
zilmar
|
e1c464e309
|
[Debugger] If stepping ops already, ignore finding a memory BreakPoint
|
2018-03-02 18:23:47 +11:00 |
|
zilmar
|
622d5d5d3f
|
[Debugger] Fix Read break points
|
2018-02-05 17:43:46 +11:00 |
|
zilmar
|
076280b9ba
|
[Debugger] Add unaligned write breakpoints
|
2018-02-02 04:28:08 +11:00 |
|
zilmar
|
7e1e7bf39b
|
[Debugger] Change bHaveDebugger to HaveDebugger
|
2018-01-16 08:23:21 +11:00 |
|
zilmar
|
857f87116e
|
[Project64] Change g_Settings->LoadBool(Debugger_Enabled) to CDebugSettings::bHaveDebugger()
|
2017-09-13 20:08:47 +10:00 |
|
zilmar
|
10f662da94
|
[Project64] Better handling of div / 0
|
2017-08-31 09:43:58 +10:00 |
|
shygoo
|
47fd0632ff
|
Add debug features
|
2017-08-18 00:08:22 -05:00 |
|
zilmar
|
c3d89e8fc1
|
[Project64] Fix Round 0.5 in interpter
|
2017-04-24 07:36:40 +10:00 |
|
zilmar
|
42084371b7
|
[Project64] Get COP1_D_ROUND_L to use _FPR_D
|
2017-04-24 07:33:35 +10:00 |
|
zilmar
|
b4fa83e0ad
|
[Project64] Clean up eol blank space InterpreterOps.cpp
|
2017-04-24 07:30:49 +10:00 |
|
zilmar
|
812dae99f5
|
[Project64] Fix bug in Double_RoundToInteger32 for arm
|
2016-09-24 08:36:14 +10:00 |
|
zilmar
|
c8cd2914a6
|
{project64] Move compiling load/store instructions in to x86/x86RecompilerOps.cpp
|
2016-06-29 23:40:36 +10:00 |
|
LegendOfDragoon
|
32ade84138
|
Implement COP1_D_ROUND_L in cpu interpreter
|
2016-05-22 23:37:45 -07:00 |
|
LegendOfDragoon
|
b2b10969c9
|
Implement COP1_S_ROUND_L in cpu interpreter
|
2016-05-22 23:20:49 -07:00 |