zilmar
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befa57924d
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Core: Fix clang compile issues
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2023-10-05 15:01:09 +10:30 |
zilmar
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f73c3708a5
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Core: Fix up tlb Probe and call EXC_MOD when tlb is not dirty
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2023-10-05 14:45:17 +10:30 |
zilmar
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e74e8f6a23
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Core: Have load/store ops be able to use 64bit addresses
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2023-10-05 14:28:32 +10:30 |
zilmar
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9f07fe2aac
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Core: Get tlb addresses to be 64bit
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2023-10-05 13:42:31 +10:30 |
zilmar
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4b844495b7
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Core: Have save states handle COP0/TLB being 64bit now
Core: Clean up tlb class
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2023-10-05 13:10:45 +10:30 |
zilmar
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35105e814e
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Core: Remove CRegisters::DoTLBReadMiss and CRegisters::DoTLBWriteMiss
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2023-10-05 09:54:41 +10:30 |
zilmar
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b7311cc611
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Core: Change Non memory load/store to not use tlb
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2023-10-05 09:32:45 +10:30 |
zilmar
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a975af0e3c
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Rsp: only use alignas for Visual Studio
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2023-09-28 16:18:39 +09:30 |
zilmar
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dd7ec63dd9
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Rsp: Change usage of alignas to try and fix android build
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2023-09-28 15:53:46 +09:30 |
zilmar
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7e249d22b1
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Try to fix android build
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2023-09-28 15:25:34 +09:30 |
zilmar
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46e6e54f24
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RSP: improve running RSP multithreaded
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2023-09-28 14:46:36 +09:30 |
zilmar
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15e6e460d2
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Rsp: Clean up VRCP, VRCPL, VRCPH, VRSQ, VRSQL, VRSQH
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2023-09-28 13:39:23 +09:30 |
zilmar
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3c52d8e2e3
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RSP: use vt instead of rt when using RSP_Vect
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2023-09-28 11:57:29 +09:30 |
zilmar
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0bd6a96118
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RSP: fix display of VRCP instruction
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2023-09-28 11:54:50 +09:30 |
zilmar
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b1240072c6
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RSP: move Enter_RSP_Register_Window & UpdateRSPRegistersScreen function definition out of RSP core
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2023-09-28 11:53:57 +09:30 |
zilmar
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ac3e0f83d1
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Rsp: Use RSP Register Handler
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2023-09-28 11:52:06 +09:30 |
zilmar
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bd1ec4ff0f
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Core: Create a setting for RDRAM Size that plugins can read
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2023-09-28 07:29:11 +09:30 |
zilmar
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99417fc5d9
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Core: reset run event in CRSP_Plugin after rom close
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2023-09-28 07:19:20 +09:30 |
zilmar
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f817becf9c
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Core: Create a handler for RSP registers that is accessible to the core and the RSP
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2023-09-28 07:03:01 +09:30 |
zilmar
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03e13455f9
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Core: Update pipeline before sync in CX86RecompilerOps::OverflowDelaySlot
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2023-09-28 06:39:39 +09:30 |
zilmar
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2caa457d02
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Core: reset pipeline stage after CompileLoadMemoryValue and CompileStoreMemoryValue
Update counter before mfc0 x, count
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2023-09-22 11:01:46 +09:30 |
zilmar
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10d2b77d7c
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Core: Try to fix android build
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2023-09-21 20:13:41 +09:30 |
zilmar
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aadcca7528
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Core: Fix clang issue
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2023-09-21 18:40:27 +09:30 |
zilmar
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6307888be4
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Core: fix up exception generator functions
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2023-09-21 18:07:56 +09:30 |
zilmar
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32ff820a03
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RSP: clean up vector compare ops (VLT, VEQ, VNE, VGE, VCH)
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2023-09-21 15:51:16 +09:30 |
zilmar
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dc95d2f7a4
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RSP: Clean up vector ops (VADD, VSUB, VABS, VSUBC, VMRG, VAND, VNAND, VOR, VNOR, VXOR, VNXOR)
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2023-09-21 15:44:07 +09:30 |
zilmar
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174e751a4a
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RSP: Fix up load ops (LUV, LHV, LFV, LTV)
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2023-09-21 15:30:07 +09:30 |
zilmar
|
bdaf8cf78c
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RSP: Clean up store vector ops (SHV, SFV, STV, SWV)
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2023-09-21 15:25:45 +09:30 |
zilmar
|
5dcc7e200f
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Rsp: Move InitilizeRSPRegisters and InitilizeRSP into rsp-core
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2023-09-21 15:16:26 +09:30 |
zilmar
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42a944c660
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RSP: Setup option to run in a thread
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2023-09-21 14:25:07 +09:30 |
zilmar
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c4abebe201
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Core: Update <Project64-plugin-spec\ to <Project64-plugin-spec/
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2023-09-21 14:13:08 +09:30 |
zilmar
|
f3d6d3fc7c
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Core: for tlb miss only use special address when address is not defined
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2023-09-14 18:39:15 +09:30 |
zilmar
|
e0c125e837
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Core: Fix clang issue
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2023-09-14 16:33:20 +09:30 |
zilmar
|
c02858c7a0
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Core: Add LLD opcode
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2023-09-14 16:31:37 +09:30 |
zilmar
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f559aed2ad
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Core: Get CRegisters::DoAddressError, CRegisters::DoTLBReadMiss, CRegisters::DoTLBWriteMiss to use TriggerException function
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2023-09-14 16:23:26 +09:30 |
zilmar
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ae4af8746b
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Core: replace GenerateTLBReadException and void GenerateTLBWriteException with CRegisters::DoTLBReadMiss/CRegisters::DoTLBWriteMiss
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2023-09-14 13:09:11 +09:30 |
zilmar
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8b14b6d7d1
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Core: Move InitRegisters to register class
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2023-09-14 12:01:16 +09:30 |
zilmar
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a5a4873e84
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Core: Have CRegisters::DoAddressError to not directly modify program counter
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2023-09-14 11:37:21 +09:30 |
zilmar
|
2d09178449
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Core: Add calls to CPO1_UNIMPLEMENTED_OP for Cop1.w functions
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2023-09-14 11:15:42 +09:30 |
zilmar
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5da5dab3c5
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Core: Have CRegisters::DoTLBReadMiss set the target pipe line to jump, not directly modify the PC
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2023-09-14 11:09:28 +09:30 |
zilmar
|
fcd7257adc
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Core: Change COP0 Status register to a struct breaking up the bits
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2023-09-14 10:23:36 +09:30 |
zilmar
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9ffd87168a
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Core: DisplayControlRegHandler::Read32 read more of the registers
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2023-09-14 09:40:11 +09:30 |
zilmar
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002f2e17c3
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RSP: Clean up code for vector multiple ops
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2023-09-07 11:54:36 +09:30 |
zilmar
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4e9a692449
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RSP: Add RSP_Vector_VRNDP
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2023-09-07 11:41:17 +09:30 |
zilmar
|
0cadbe0f70
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RSP: Add clamp16
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2023-09-07 11:31:31 +09:30 |
zilmar
|
af1c0c2b55
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RSP: Add Vmulq
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2023-09-07 11:30:15 +09:30 |
zilmar
|
d468b863c2
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Rsp: add vnop for vnull
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2023-09-07 11:29:16 +09:30 |
zilmar
|
8b71ef3bc1
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RSP: Add RSP_Vector_Reserved
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2023-09-07 11:23:35 +09:30 |
zilmar
|
ab67374c8a
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RSP: Update the display of RSP opcodes in debugger
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2023-09-07 11:19:44 +09:30 |
zilmar
|
4f74dc4bb0
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Rsp: Update display of vector in debugger
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2023-09-07 11:17:08 +09:30 |