zilmar
5750d3df80
Core: Have only one function to do what R4300iOp::ExecuteOps and R4300iOp::ExecuteCPU was doing
2024-10-24 09:59:41 +10:30
zilmar
c39582b9ed
Core: Make sure CX86RecompilerOps::SPECIAL_AND can not write to R0
2024-10-17 18:42:45 +10:30
zilmar
a38467cc19
Core: Reset Memory Stack Pos In recompiler after running interpter code at non rdram location
2024-10-17 18:40:37 +10:30
zilmar
f708e5c0b2
Core: Check recompiler memory based on the function size
2024-10-17 15:05:48 +10:30
zilmar
45e52e1d2a
Core: in SPECIAL_SYSCALL, SPECIAL_BREAK only exit the block is the stage is PIPELINE_STAGE_NORMAL
2024-10-17 14:12:46 +10:30
zilmar
ccf708751f
Core: Fix up clang error
2024-10-11 07:09:03 +10:30
Squall Leonhart
0d95a0cd7f
quick dirty possible fix for MBC5 roms of 4 and 8MB size. ( #2442 )
2024-10-10 18:04:31 +10:30
zilmar
a2e479a705
Core: Handle paths with non-ASCII characters
2024-10-10 18:01:10 +10:30
zilmar
7aa77a3840
Merge branch 'develop' of https://github.com/project64/project64 into develop
2024-10-10 18:00:12 +10:30
zilmar
c176f61aac
Core: Normalize Plugin dir
2024-10-10 10:12:53 +10:30
Squall Leonhart
fc23fca43e
[RDB]Set SGB Emulator to 8MB ( #2440 )
...
since the defaults for rdram changed between 6058 and 6059, i had not accounted for this emulator rom actually needing 8MB
2024-10-03 22:20:51 +09:30
Tomas Mejia
edc54c425f
Fix spelling and clarity issues in CONTRIBUTING.md ( #2438 )
...
* Fix spelling and clarity issues in CONTRIBUTING.md
Reword in a few places for clarity without changing the original meaning.
Fix typos in words like "sensible" and "ensure."
Fix numbering (skipped from 5 to 7).
* Update CONTRIBUTING.md
Add newline to end of file
2024-10-03 21:40:53 +09:30
zilmar
30090e5db7
Core: in CX86Ops::CX86Ops set setLogger to nullptr if not logging
2024-10-03 16:22:42 +09:30
zilmar
9e53b161a4
Cote Update PeripheralInterfaceHandler::PI_DMA_WRITE to handle misaligned, end of page test
2024-10-03 14:38:04 +09:30
zilmar
08e1b3b39b
fix up clang formatting
2024-09-26 18:54:54 +09:30
zilmar
62bf10e505
Core: Have fpu ops check the input of fs and ft at the same time
2024-09-26 16:38:25 +09:30
zilmar
dc4fa211b0
Core: Clean up RDRAM/RI Registers
2024-09-26 12:59:32 +09:30
zilmar
544d6ba1b9
Core: Normalize Path for RomList_RomListCache
2024-09-26 07:30:26 +09:30
zilmar
cd9fc5984a
RSP: Make sure m_SyncSystem is valid before checking m_SyncSystem->m_BaseSystem on shutdown
2024-09-26 06:50:48 +09:30
zilmar
7cb0c258a1
GLideN64: Slight clean up of project file
2024-09-19 12:16:46 +09:30
zilmar
c098a6a464
RSP: Be able to compile sections based off tasks
2024-09-19 12:15:11 +09:30
zilmar
3340c032c3
RSP: Move CompilePC into RspRecompilerCPU
2024-09-19 08:31:28 +09:30
zilmar
df9b04bb5b
RSP: Change RunInterpreterCPU to ExecuteOps
2024-09-12 15:13:45 +09:30
zilmar
07e8f8b830
Gliden64: Get the new GlideN64 submodule to build as part of the normal build process
2024-09-12 09:44:38 +09:30
zilmar
02e816b9d4
Update package_zip.cmd to deal with platform in path
2024-09-05 19:22:25 +09:30
zilmar
ea199c5546
Update installer to have new binary path
2024-09-05 18:50:47 +09:30
zilmar
aaa6fc8082
Core: Add $(Platform) to the output directory
2024-09-05 17:54:58 +09:30
zilmar
00a92871c0
Gliden64: Add as a submodule
2024-09-05 11:17:26 +09:30
zilmar
eb985de132
RSP: Start to add CPU style HLE
2024-08-29 15:37:52 +09:30
zilmar
5eac210197
RSP: Start to have a RSP Settings class
2024-08-29 11:26:53 +09:30
zilmar
96080bfdd2
RSP: change CRSPSystem::m_Recompiler from a pointer to a member and initialize it at creation of system
2024-08-29 07:49:40 +09:30
zilmar
2b7975280e
RSP: Have NextInstruction and JumpTo members of RSP System instead of a global variable
2024-08-22 19:44:07 +09:30
zilmar
29c49a2063
RSP: Remove PrgCount as a global
2024-08-22 17:32:05 +09:30
zilmar
d9ae43b69d
RSP: have RSPRegisterHandlerPlugin as part of RSP System instead of a global
2024-08-22 16:30:20 +09:30
zilmar
4681f07bf8
RSP: Move rdp logging in to it's own class
2024-08-15 13:43:56 +09:30
zilmar
6ed1c3edfb
RSP: internalize RSP information in to interpter ops
2024-08-15 07:36:53 +09:30
zilmar
9f98f4d4cd
Rsp: Change RSPOpC to be a class member
2024-08-08 12:55:54 +09:30
zilmar
762d1b1566
RSP: Create CRSPRecompiler
2024-08-08 09:39:45 +09:30
zilmar
f7ab608976
RSP: Create CRSPRegisters
2024-08-08 07:26:15 +09:30
zilmar
1924030266
RSP: Move compile functions into CRSPRecompilerOps
2024-08-02 22:00:01 +09:30
zilmar
2904d3641d
RSP: Create RSP system class and move all interpter ops in to RSPOp class
2024-08-02 09:00:38 +09:30
zilmar
dab432e7bd
RSP: clean up LDV
2024-07-20 19:10:36 +09:30
zilmar
9d7b391487
RSP: Fix up LSV in the recompiler
2024-07-20 17:09:41 +09:30
zilmar
7c2655c544
RSP: Remove some unused functions and turn Reordering and Sections off by default
2024-07-20 17:08:20 +09:30
zilmar
6816ff4435
RSP: Disable a lot of ops that are not functioning correctly in the recompiler
2024-07-20 17:05:11 +09:30
zilmar
13fb8cd2da
RSP: In Compile_Opcode_SQV Cheat the op instead of causing an unknown opcode
2024-07-12 15:23:59 +09:30
zilmar
564926163c
RSP: in Compile_Opcode_SSV cheat the op instead of generating an unknown opcode
2024-07-12 15:07:23 +09:30
zilmar
8c6856f1c8
RSP: Have Compile_SW handle DMEM overflow better
2024-07-12 15:04:18 +09:30
zilmar
6e4852fc78
RSP: have Compile_LW handle DMEM overflow better
2024-07-12 15:02:46 +09:30
zilmar
e43d697476
RSP: Handle lwu inside IsRegisterConstant
2024-07-12 15:01:05 +09:30