zilmar
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5e1a40fffb
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Core: fix CX86RecompilerOps::CompileLoadMemoryValue Map_GPR_32bit when called from LWC1
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2024-11-21 11:10:01 +10:30 |
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zilmar
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97b2579b4b
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Core: Have the recompiler just deal with the Program Counter as 32bit
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2024-11-07 17:05:16 +10:30 |
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zilmar
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91f9cdaaa7
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Core: Change the Program counter to be 64bit
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2024-06-06 14:09:12 +09:30 |
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zilmar
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6610ae3058
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Core: Have R4300iInstruction in CRecompilerOpsBase
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2023-12-21 10:34:03 +10:30 |
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zilmar
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8e3fb3e302
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Core: Have R4300iInstruction::WritesGPR return the register written to instead of passing a variable by reference
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2023-12-21 10:26:10 +10:30 |
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zilmar
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b438fddf2e
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Core: Add CP2 handling
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2023-05-18 18:04:41 +09:30 |
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zilmar
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d35d2e6abe
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Core: Move ReadsGPR, WritesGPR, ReadsHI(), ReadsLO(), WritesHI(), WritesLO() out of OpInfo and into R4300iInstruction
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2022-12-05 12:23:09 +10:30 |
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zilmar
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761a1ee52a
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Code clean up
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2022-10-10 10:52:17 +10:30 |
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zilmar
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09b535551d
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Core: Move DelaySlotEffectsCompare into R4300iInstruction
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2022-07-25 16:35:42 +09:30 |
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zilmar
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0abc7ccaa4
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Core: Move OpHasDelaySlot into R4300iInstruction
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2022-07-25 14:23:12 +09:30 |
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zilmar
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7f3b8e3601
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Core: Start to add R4300iInstruction to do analysis of an opcode
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2022-07-18 18:01:00 +09:30 |