Jeffrey Pfau
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120b85713d
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Mode switching
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2013-04-07 02:36:41 -07:00 |
Jeffrey Pfau
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bda71cafc2
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ALU instructions can write to PC
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2013-04-07 02:01:14 -07:00 |
Jeffrey Pfau
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6e3a9a9508
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Fix writing to PC
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2013-04-07 01:57:04 -07:00 |
Jeffrey Pfau
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68f2eed84d
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Mini-test
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2013-04-07 01:39:49 -07:00 |
Jeffrey Pfau
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9575e7f0d2
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Fix B
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2013-04-07 01:39:08 -07:00 |
Jeffrey Pfau
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0e2394e7d5
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De-inline ARMStep
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2013-04-07 01:46:48 -07:00 |
Jeffrey Pfau
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b23f1ee3e3
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GBA ROM loading
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2013-04-07 01:46:28 -07:00 |
Jeffrey Pfau
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340d3ce6a7
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Implement B
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2013-04-06 20:16:14 -07:00 |
Jeffrey Pfau
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5c7b4a98c6
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Load from ARM table now that we have one
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2013-04-06 20:06:51 -07:00 |
Jeffrey Pfau
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6bd7a5ee53
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Fill remainder of table
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2013-04-06 20:01:32 -07:00 |
Jeffrey Pfau
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7a0fb72e7e
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Stub out SWI
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2013-04-06 19:58:01 -07:00 |
Jeffrey Pfau
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d620357ac8
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Stub out coprocessor
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2013-04-06 19:52:45 -07:00 |
Jeffrey Pfau
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5dd2379dd5
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Cleanup
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2013-04-06 19:38:14 -07:00 |
Jeffrey Pfau
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f2a1257fbb
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Stub out branch instructions
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2013-04-06 19:22:14 -07:00 |
Jeffrey Pfau
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1858dfeb1c
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Stub out LDM/STM
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2013-04-06 18:44:52 -07:00 |
Jeffrey Pfau
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7b82cc0040
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Fill in LDR/STR block
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2013-04-06 13:05:53 -07:00 |
Jeffrey Pfau
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befba57fe6
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Simple error checking
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2013-04-06 04:34:19 -07:00 |
Jeffrey Pfau
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9efc945f1b
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Add store callbacks
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2013-04-06 04:20:44 -07:00 |
Jeffrey Pfau
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96da9c7ef1
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Partially implement LDR/STR and friends
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2013-04-06 04:16:34 -07:00 |
Jeffrey Pfau
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92e74a78e1
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Apparently I can't count to 8
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2013-04-06 02:49:54 -07:00 |
Jeffrey Pfau
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cb2469c4f4
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Filler for more instructions
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2013-04-06 00:32:01 -07:00 |
Jeffrey Pfau
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a01fc986a3
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Begin GBA structure
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2013-04-05 02:17:22 -07:00 |
Jeffrey Pfau
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cd07dee7b1
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Implement immediate shifter
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2013-04-05 00:44:53 -07:00 |
Jeffrey Pfau
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c07df4a337
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Fill in immediates
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2013-04-04 03:12:22 -07:00 |
Jeffrey Pfau
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63f6f53a80
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Implement BIC, MOV, MVN, ORR
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2013-04-04 02:42:17 -07:00 |
Jeffrey Pfau
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dbee1e871e
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Add stubs, including for illegal instructions
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2013-04-04 02:36:53 -07:00 |
Jeffrey Pfau
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e093960316
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Fill in more opcodes, implement CMN, CMP, TEQ, TST
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2013-04-04 02:31:32 -07:00 |
Jeffrey Pfau
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fd4ee12eb5
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Implement ADD, ADC, RSB, RSC, SUB
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2013-04-04 02:04:51 -07:00 |
Jeffrey Pfau
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c1a8042db4
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Fill in more opcodes, implement EOR
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2013-04-04 01:27:51 -07:00 |
Jeffrey Pfau
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4025bf89f2
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Add boilerplate for instructions
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2013-04-04 00:46:50 -07:00 |
Jeffrey Pfau
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bf72532715
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Add more framework for loading instructions
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2013-04-03 22:34:49 -07:00 |
Jeffrey Pfau
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009bef870c
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Initial commit
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2013-04-03 22:12:15 -07:00 |