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mgba
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4,648 Commits 36 Branches 39 Tags 69 MiB
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4648 Commits

Author SHA1 Message Date
Jeffrey Pfau 7e38db4533 DS: Begin memory timings 2017-01-03 22:03:24 -08:00
Jeffrey Pfau 5a55b53983 DS: Port over DMAs 2017-01-03 17:48:07 -08:00
Jeffrey Pfau 66db559f5b DS Memory: Fix copy-paste error 2017-01-03 15:31:09 -08:00
Jeffrey Pfau 0053f85922 DS: Start work on IPC 2017-01-03 15:30:56 -08:00
Jeffrey Pfau c037dada3e DS: Share code between cores 2017-01-03 13:58:54 -08:00
Jeffrey Pfau 2359a4e886 DS: Move time slicing to event system 2017-01-02 21:48:12 -08:00
Jeffrey Pfau d620a8c38c DS: Merge GBA and DS timers 2017-01-02 19:31:38 -08:00
Jeffrey Pfau e0ae2e8906 DS: Backport CPSR I fix 2017-01-02 18:22:02 -08:00
Jeffrey Pfau 87caf0a6ac Merge branch 'master' into medusa 2017-01-02 18:17:50 -08:00
Jeffrey Pfau 3f61f68f22 GBA: Fix multiboot ROM loading 2017-01-01 22:04:04 -08:00
Jeffrey Pfau 180418a74f ARM7: Fix MLA/*MULL/*MLAL timing 2017-01-01 14:46:58 -08:00
Jeffrey Pfau ae9feee147 All: Update CHANGES for 0.5.2 2016-12-31 01:56:26 -08:00
Jeffrey Pfau 2c52c55efc Windows: Fix VDir unitialized variable 2016-12-31 01:47:51 -08:00
Jeffrey Pfau 978349d765 Windows: Fix build 2016-12-30 23:46:07 -08:00
Jeffrey Pfau fa884d071e All: Migrate includes to separate directory 2016-12-30 21:25:07 -08:00
Jeffrey Pfau 6d898542c7 Merge branch 'feature/python-bindings' 2016-12-29 01:23:31 -08:00
Jeffrey Pfau 19b164d560 Libretro: Fix disabling BIOS 2016-12-28 19:16:33 -08:00
Jeffrey Pfau 2d02719fa5 Revert "GBA Video: Fix out-of-order OBJWIN" 
This reverts commit f34f45257a.
 2016-12-28 19:05:57 -08:00
Jeffrey Pfau d752df421f 3DS: Fix build 2016-12-27 04:12:15 -08:00
Jeffrey Pfau 20367765b8 GUI: Fix build 2016-12-27 04:03:44 -08:00
Jeffrey Pfau 9cbbd9f255 GBA I/O: Set JOYSTAT TRANS flag when writing JOY_TRANS registers 2016-12-27 03:48:41 -08:00
Jeffrey Pfau 75d9085eef GBA I/O: Clear JOYSTAT RECV flag when reading JOY_RECV registers 2016-12-27 02:11:54 -08:00
Jeffrey Pfau 463ce99739 All: Include cleanup 2016-12-26 23:27:32 -08:00
Jeffrey Pfau 03ca7515b3 GBA SIO: Add some basic JOY bus constants 2016-12-26 22:26:31 -08:00
Jeffrey Pfau f7ac90d74e Util: Add ifndef guard for UNUSED define 2016-12-26 21:02:57 -08:00
Jeffrey Pfau 2f1cb61d01 All: Add C++ header guards 2016-12-26 21:01:55 -08:00
Jeffrey Pfau daaa2fa523 GB SIO: Support faster transfer speeds 2016-12-26 17:20:51 -08:00
Jeffrey Pfau c662b59e99 GB: Allow player 2 to act as shift clock 2016-12-26 17:13:53 -08:00
Jeffrey Pfau 269b18d8aa GB SIO: Some fixes 2016-12-26 16:46:51 -08:00
Jeffrey Pfau 871ce36386 DS Memory: Implement (currently fixed-location) DTCM 2016-12-26 01:03:11 -08:00
Jeffrey Pfau ef29028109 DS: Modernize a bit 2016-12-26 00:46:12 -08:00
Jeffrey Pfau 0c5ce511fb DS: Fix build 2016-12-25 23:48:13 -08:00
Jeffrey Pfau 6049c1b340 Util: Make clz consistent 2016-12-25 23:36:47 -08:00
Jeffrey Pfau 12928954ab Read TM*CNT registers 2016-12-25 23:36:47 -08:00
Jeffrey Pfau 7dd3e99d2a DS: Write IF register 2016-12-25 23:36:47 -08:00
Jeffrey Pfau e649be94f5 DS: Add timers and start interrupts 2016-12-25 23:36:47 -08:00
Jeffrey Pfau 9c91235a34 ARM7: Clean up instruction decoding for future expandability 2016-12-25 23:36:47 -08:00
Jeffrey Pfau 89936d1b94 ARM9: Implement BLX (2) 2016-12-25 23:36:47 -08:00
Jeffrey Pfau 3796c32eb4 ARM: Start implementing ARMv5 instructions 2016-12-25 23:36:47 -08:00
Jeffrey Pfau aeaa59eb88 DS Core: Spin both CPUs more reliably 2016-12-25 23:36:47 -08:00
Jeffrey Pfau 7969bac2b2 DS: Add ability to switch CPUs while debugging 2016-12-25 23:36:47 -08:00
Jeffrey Pfau 36b3f07ed1 DS I/O: Start I/O 2016-12-25 23:36:47 -08:00
Jeffrey Pfau 5d3acef7fe DS Memory: More baseline 2016-12-25 23:36:46 -08:00
Jeffrey Pfau 0088229e9f DS: Spin both CPUs 2016-12-25 23:36:46 -08:00
Jeffrey Pfau 112beb8e66 DS: Add SWI handling for ARM7 CPU 2016-12-25 23:36:46 -08:00
Jeffrey Pfau ad492cab49 DS Memory: Add ITCM 2016-12-25 23:36:46 -08:00
Jeffrey Pfau 60d49b4860 ARM: CP15 improvements 2016-12-25 23:36:46 -08:00
Jeffrey Pfau 8bfad3f7be DS Memory: Implement basic RAM access 2016-12-25 23:36:46 -08:00
Jeffrey Pfau f32e92e0f1 ARM: Implement MCR for coprocessor 15 2016-12-25 23:36:46 -08:00
Jeffrey Pfau b83f037799 DS: Add CPSR-reading skeleton, sans IRQs 2016-12-25 23:36:46 -08:00