mirror of https://github.com/mgba-emu/mgba.git
DS: Add timers and start interrupts
This commit is contained in:
parent
9c91235a34
commit
e649be94f5
64
src/ds/ds.c
64
src/ds/ds.c
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@ -80,6 +80,10 @@ static void DSInit(void* cpu, struct mCPUComponent* component) {
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ds->springIRQ7 = 0;
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ds->springIRQ9 = 0;
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ds->timersEnabled7 = 0;
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ds->timersEnabled9 = 0;
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memset(ds->timers7, 0, sizeof(ds->timers7));
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memset(ds->timers9, 0, sizeof(ds->timers9));
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ds->keySource = NULL;
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ds->rtcSource = NULL;
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ds->rumble = NULL;
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@ -196,22 +200,26 @@ static void DSProcessEvents(struct ARMCore* cpu) {
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ds->springIRQ7 = 0;
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}
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do {
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int32_t cycles = cpu->nextEvent;
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int32_t nextEvent = INT_MAX;
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int32_t cycles = cpu->nextEvent;
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int32_t nextEvent = INT_MAX;
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int32_t testEvent;
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#ifndef NDEBUG
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if (cycles < 0) {
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mLOG(DS, FATAL, "Negative cycles passed: %i", cycles);
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}
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if (cycles < 0) {
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mLOG(DS, FATAL, "Negative cycles passed: %i", cycles);
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}
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#endif
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cpu->cycles -= cycles;
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cpu->nextEvent = nextEvent;
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testEvent = DSTimersProcessEvents(ds, cycles);
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if (testEvent < nextEvent) {
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nextEvent = testEvent;
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}
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if (cpu->halted) {
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cpu->cycles = cpu->nextEvent;
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}
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} while (cpu->cycles >= cpu->nextEvent);
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cpu->cycles -= cycles;
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cpu->nextEvent = nextEvent;
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if (cpu->halted) {
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cpu->cycles = cpu->nextEvent;
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}
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}
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void DSAttachDebugger(struct DS* ds, struct mDebugger* debugger) {
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@ -454,4 +462,34 @@ void DS9WriteCP15(struct ARMCore* cpu, int crn, int crm, int opcode1, int opcode
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case 9:
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_writeTCMControl(cpu, crm, opcode2, value);
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break;
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}}
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}
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}
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void DSWriteIE(struct ARMCore* cpu, uint16_t* io, uint32_t value) {
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if (io[DS7_REG_IME >> 1] && (value & io[DS7_REG_IF_LO >> 1] || (value >> 16) & io[DS7_REG_IF_HI >> 1])) {
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ARMRaiseIRQ(cpu);
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}
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}
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void DSWriteIME(struct ARMCore* cpu, uint16_t* io, uint16_t value) {
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if (value && (io[DS7_REG_IE_LO >> 1] & io[DS7_REG_IF_LO >> 1] || io[DS7_REG_IE_HI >> 1] & io[DS7_REG_IF_HI >> 1])) {
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ARMRaiseIRQ(cpu);
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}
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}
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void DSRaiseIRQ(struct ARMCore* cpu, uint16_t* io, enum DSIRQ irq) {
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if (irq < 16) {
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io[DS7_REG_IF_LO >> 1] |= 1 << irq;
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} else {
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io[DS7_REG_IF_HI >> 1] |= 1 << (irq - 16);
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}
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cpu->halted = 0;
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if (!io[DS7_REG_IME >> 1]) {
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return;
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}
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if (irq < 16 && (io[DS7_REG_IE_LO >> 1] & 1 << irq)) {
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ARMRaiseIRQ(cpu);
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} else if (io[DS7_REG_IE_HI >> 1] & 1 << (irq - 16)) {
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ARMRaiseIRQ(cpu);
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}
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}
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@ -12,6 +12,7 @@
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#include "core/log.h"
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#include "ds/memory.h"
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#include "ds/timer.h"
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#include "ds/video.h"
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extern const uint32_t DS_ARM946ES_FREQUENCY;
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@ -57,6 +58,10 @@ struct DS {
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struct ARMCore* arm9;
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struct DSMemory memory;
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struct DSVideo video;
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int timersEnabled7;
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int timersEnabled9;
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struct DSTimer timers7[4];
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struct DSTimer timers9[4];
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struct mCoreSync* sync;
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@ -131,4 +136,8 @@ bool DSIsROM(struct VFile* vf);
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void DSGetGameCode(struct DS* ds, char* out);
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void DSGetGameTitle(struct DS* ds, char* out);
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void DSWriteIME(struct ARMCore* cpu, uint16_t* io, uint16_t value);
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void DSWriteIE(struct ARMCore* cpu, uint16_t* io, uint32_t value);
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void DSRaiseIRQ(struct ARMCore* cpu, uint16_t* io, enum DSIRQ irq);
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#endif
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74
src/ds/io.c
74
src/ds/io.c
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@ -24,11 +24,53 @@ void DS7IOInit(struct DS* ds) {
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void DS7IOWrite(struct DS* ds, uint32_t address, uint16_t value) {
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switch (address) {
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case DS9_REG_IPCSYNC:
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// Timers
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case DS7_REG_TM0CNT_LO:
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DSTimerWriteTMCNT_LO(&ds->timers7[0], value);
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return;
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case DS7_REG_TM1CNT_LO:
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DSTimerWriteTMCNT_LO(&ds->timers7[1], value);
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return;
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case DS7_REG_TM2CNT_LO:
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DSTimerWriteTMCNT_LO(&ds->timers7[2], value);
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return;
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case DS7_REG_TM3CNT_LO:
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DSTimerWriteTMCNT_LO(&ds->timers7[3], value);
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return;
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case DS7_REG_TM0CNT_HI:
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value &= 0x00C7;
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DSTimerWriteTMCNT_HI(&ds->timers7[0], ds->arm7, &ds->memory.io7[(address - 2) >> 1], value);
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ds->timersEnabled7 &= ~1;
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ds->timersEnabled7 |= DSTimerFlagsGetEnable(ds->timers7[0].flags);
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break;
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case DS7_REG_TM1CNT_HI:
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value &= 0x00C7;
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DSTimerWriteTMCNT_HI(&ds->timers7[1], ds->arm7, &ds->memory.io7[(address - 2) >> 1], value);
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ds->timersEnabled7 &= ~2;
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ds->timersEnabled7 |= DSTimerFlagsGetEnable(ds->timers7[1].flags) << 1;
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break;
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case DS7_REG_TM2CNT_HI:
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value &= 0x00C7;
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DSTimerWriteTMCNT_HI(&ds->timers7[2], ds->arm7, &ds->memory.io7[(address - 2) >> 1], value);
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ds->timersEnabled7 &= ~4;
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ds->timersEnabled7 |= DSTimerFlagsGetEnable(ds->timers7[2].flags) << 2;
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break;
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case DS7_REG_TM3CNT_HI:
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value &= 0x00C7;
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DSTimerWriteTMCNT_HI(&ds->timers7[3], ds->arm7, &ds->memory.io7[(address - 2) >> 1], value);
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ds->timersEnabled7 &= ~8;
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ds->timersEnabled7 |= DSTimerFlagsGetEnable(ds->timers7[3].flags) << 3;
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break;
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case DS7_REG_IPCSYNC:
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value &= 0x6F00;
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value |= ds->memory.io7[address >> 1] & 0x000F;
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_writeIPCSync(ds->arm9, ds->memory.io9, value);
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break;
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case DS7_REG_IME:
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DSWriteIME(ds->arm7, ds->memory.io7, value);
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break;
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default:
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mLOG(DS_IO, STUB, "Stub DS7 I/O register write: %06X:%04X", address, value);
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if (address >= DS7_REG_MAX) {
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@ -50,11 +92,28 @@ void DS7IOWrite8(struct DS* ds, uint32_t address, uint8_t value) {
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}
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}
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void DS7IOWrite32(struct DS* ds, uint32_t address, uint32_t value);
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void DS7IOWrite32(struct DS* ds, uint32_t address, uint32_t value) {
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switch (address) {
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case DS7_REG_IE_LO:
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DSWriteIE(ds->arm7, ds->memory.io7, value);
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break;
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default:
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DS7IOWrite(ds, address, value & 0xFFFF);
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DS7IOWrite(ds, address | 2, value >> 16);
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return;
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}
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ds->memory.io7[address >> 1] = value;
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ds->memory.io7[(address >> 1) + 1] = value >> 16;
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}
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uint16_t DS7IORead(struct DS* ds, uint32_t address) {
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switch (address) {
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case DS7_REG_IPCSYNC:
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case DS7_REG_IME:
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case DS7_REG_IE_LO:
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case DS7_REG_IE_HI:
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case DS7_REG_IF_LO:
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case DS7_REG_IF_HI:
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// Handled transparently by the registers
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break;
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default:
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@ -98,7 +157,16 @@ void DS9IOWrite8(struct DS* ds, uint32_t address, uint8_t value) {
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}
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}
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void DS9IOWrite32(struct DS* ds, uint32_t address, uint32_t value);
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void DS9IOWrite32(struct DS* ds, uint32_t address, uint32_t value) {
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switch (address) {
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default:
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DS9IOWrite(ds, address, value & 0xFFFF);
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DS9IOWrite(ds, address | 2, value >> 16);
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return;
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}
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ds->memory.io9[address >> 1] = value;
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ds->memory.io9[(address >> 1) + 1] = value >> 16;
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}
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uint16_t DS9IORead(struct DS* ds, uint32_t address) {
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switch (address) {
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@ -248,6 +248,9 @@ uint32_t DS7Load32(struct ARMCore* cpu, uint32_t address, int* cycleCounter) {
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}
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mLOG(DS_MEM, STUB, "Unimplemented DS7 Load32: %08X", address);
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break;
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case DS_REGION_IO:
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value = DS7IORead(ds, address & 0x00FFFFFC) | (DS7IORead(ds, (address & 0x00FFFFFC) | 2) << 16);
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break;
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default:
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mLOG(DS_MEM, STUB, "Unimplemented DS7 Load32: %08X", address);
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break;
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@ -347,6 +350,9 @@ void DS7Store32(struct ARMCore* cpu, uint32_t address, int32_t value, int* cycle
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}
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mLOG(DS_MEM, STUB, "Unimplemented DS7 Store32: %08X:%08X", address, value);
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break;
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case DS_REGION_IO:
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DS7IOWrite32(ds, address & 0x00FFFFFF, value);
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break;
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default:
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mLOG(DS_MEM, STUB, "Unimplemented DS7 Store32: %08X:%08X", address, value);
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break;
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@ -455,6 +461,9 @@ uint32_t DS7LoadMultiple(struct ARMCore* cpu, uint32_t address, int mask, enum L
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mLOG(DS_MEM, STUB, "Unimplemented DS7 LDM: %08X", address);
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});
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break;
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case DS_REGION_IO:
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LDM_LOOP(value = DS7IORead(ds, address & 0x00FFFFFC) | (DS7IORead(ds, (address & 0x00FFFFFC) | 2) << 16));
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break;
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default:
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mLOG(DS_MEM, STUB, "Unimplemented DS7 LDM: %08X", address);
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LDM_LOOP(value = 0);
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@ -592,6 +601,9 @@ uint32_t DS9Load32(struct ARMCore* cpu, uint32_t address, int* cycleCounter) {
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}
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mLOG(DS_MEM, STUB, "Unimplemented DS9 Load32: %08X", address);
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break;
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case DS_REGION_IO:
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value = DS9IORead(ds, address & 0x00FFFFFC) | (DS9IORead(ds, (address & 0x00FFFFFC) | 2) << 16);
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break;
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default:
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mLOG(DS_MEM, STUB, "Unimplemented DS9 Load32: %08X", address);
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break;
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@ -682,6 +694,9 @@ void DS9Store32(struct ARMCore* cpu, uint32_t address, int32_t value, int* cycle
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}
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mLOG(DS_MEM, STUB, "Unimplemented DS9 Store32: %08X:%08X", address, value);
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break;
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case DS_REGION_IO:
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DS9IOWrite32(ds, address & 0x00FFFFFF, value);
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break;
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default:
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mLOG(DS_MEM, STUB, "Unimplemented DS9 Store32: %08X:%08X", address, value);
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break;
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@ -0,0 +1,110 @@
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/* Copyright (c) 2013-2016 Jeffrey Pfau
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*
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* This Source Code Form is subject to the terms of the Mozilla Public
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* License, v. 2.0. If a copy of the MPL was not distributed with this
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* file, You can obtain one at http://mozilla.org/MPL/2.0/. */
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#include "timer.h"
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#include "arm/arm.h"
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#include "ds/ds.h"
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void DSTimerUpdateRegister(struct DSTimer* timer, struct ARMCore* cpu, uint16_t* io) {
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if (DSTimerFlagsIsEnable(timer->flags) && !DSTimerFlagsIsCountUp(timer->flags)) {
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// Reading this takes two cycles (1N+1I), so let's remove them preemptively
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*io = timer->oldReload + ((cpu->cycles - timer->lastEvent - 2) >> DSTimerFlagsGetPrescaleBits(timer->flags));
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}
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}
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void DSTimerWriteTMCNT_LO(struct DSTimer* timer, uint16_t reload) {
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timer->reload = reload;
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timer->overflowInterval = (0x10000 - timer->reload) << DSTimerFlagsGetPrescaleBits(timer->flags);
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}
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void DSTimerWriteTMCNT_HI(struct DSTimer* timer, struct ARMCore* cpu, uint16_t* io, uint16_t control) {
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DSTimerUpdateRegister(timer, cpu, io);
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unsigned oldPrescale = DSTimerFlagsGetPrescaleBits(timer->flags);
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switch (control & 0x0003) {
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case 0x0000:
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timer->flags = DSTimerFlagsSetPrescaleBits(timer->flags, 0);
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break;
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case 0x0001:
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timer->flags = DSTimerFlagsSetPrescaleBits(timer->flags, 6);
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break;
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case 0x0002:
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timer->flags = DSTimerFlagsSetPrescaleBits(timer->flags, 8);
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break;
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case 0x0003:
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timer->flags = DSTimerFlagsSetPrescaleBits(timer->flags, 10);
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break;
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}
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timer->flags = DSTimerFlagsTestFillCountUp(timer->flags, control & 0x0004);
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timer->flags = DSTimerFlagsTestFillDoIrq(timer->flags, control & 0x0040);
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timer->overflowInterval = (0x10000 - timer->reload) << DSTimerFlagsGetPrescaleBits(timer->flags);
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bool wasEnabled = DSTimerFlagsIsEnable(timer->flags);
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timer->flags = DSTimerFlagsTestFillEnable(timer->flags, control & 0x0080);
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if (!wasEnabled && DSTimerFlagsIsEnable(timer->flags)) {
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if (!DSTimerFlagsIsCountUp(timer->flags)) {
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timer->nextEvent = cpu->cycles + timer->overflowInterval;
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} else {
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timer->nextEvent = INT_MAX;
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}
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*io = timer->reload;
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timer->oldReload = timer->reload;
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timer->lastEvent = cpu->cycles;
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} else if (wasEnabled && !DSTimerFlagsIsEnable(timer->flags)) {
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if (!DSTimerFlagsIsCountUp(timer->flags)) {
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*io = timer->oldReload + ((cpu->cycles - timer->lastEvent) >> oldPrescale);
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}
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} else if (DSTimerFlagsGetPrescaleBits(timer->flags) != oldPrescale && !DSTimerFlagsIsCountUp(timer->flags)) {
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// FIXME: this might be before present
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timer->nextEvent = timer->lastEvent + timer->overflowInterval;
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}
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if (timer->nextEvent < cpu->nextEvent) {
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cpu->nextEvent = timer->nextEvent;
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}
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}
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int32_t DSTimersProcessEvents(struct DS* ds, int32_t cycles) {
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int32_t nextEvent = INT_MAX;
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if (!ds->timersEnabled7) {
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return nextEvent;
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}
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struct DSTimer* timer;
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struct DSTimer* nextTimer;
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int t;
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for (t = 0; t < 4; ++t) {
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timer = &ds->timers7[t];
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if (DSTimerFlagsIsEnable(timer->flags)) {
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timer->nextEvent -= cycles;
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timer->lastEvent -= cycles;
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while (timer->nextEvent <= 0) {
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timer->lastEvent = timer->nextEvent;
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timer->nextEvent += timer->overflowInterval;
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ds->memory.io7[(DS7_REG_TM0CNT_LO + (t << 2)) >> 1] = timer->reload;
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timer->oldReload = timer->reload;
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if (DSTimerFlagsIsDoIrq(timer->flags)) {
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DSRaiseIRQ(ds->arm7, ds->memory.io7, DS_IRQ_TIMER0);
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}
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if (t == 3) {
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break;
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}
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nextTimer = &ds->timers7[t + 1];
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if (DSTimerFlagsIsCountUp(nextTimer->flags)) {
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++ds->memory.io7[(DS7_REG_TM1CNT_LO + (t << 2)) >> 1];
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if (!ds->memory.io7[(DS7_REG_TM1CNT_LO + (t << 2)) >> 1]) {
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nextTimer->nextEvent = 0;
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}
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}
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}
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nextEvent = timer->nextEvent;
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}
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}
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return nextEvent;
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}
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@ -0,0 +1,34 @@
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/* Copyright (c) 2013-2016 Jeffrey Pfau
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*
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* This Source Code Form is subject to the terms of the Mozilla Public
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* License, v. 2.0. If a copy of the MPL was not distributed with this
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* file, You can obtain one at http://mozilla.org/MPL/2.0/. */
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#ifndef DS_TIMER_H
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#define DS_TIMER_H
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#include "util/common.h"
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DECL_BITFIELD(DSTimerFlags, uint32_t);
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DECL_BITS(DSTimerFlags, PrescaleBits, 0, 4);
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DECL_BIT(DSTimerFlags, CountUp, 4);
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DECL_BIT(DSTimerFlags, DoIrq, 5);
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DECL_BIT(DSTimerFlags, Enable, 6);
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struct DSTimer {
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uint16_t reload;
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uint16_t oldReload;
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int32_t lastEvent;
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int32_t nextEvent;
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int32_t overflowInterval;
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DSTimerFlags flags;
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};
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// TODO: Merge back into GBATimer
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struct ARMCore;
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void DSTimerUpdateRegister(struct DSTimer* timer, struct ARMCore* cpu, uint16_t* io);
|
||||
void DSTimerWriteTMCNT_LO(struct DSTimer* timer, uint16_t reload);
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||||
void DSTimerWriteTMCNT_HI(struct DSTimer* timer, struct ARMCore* cpu, uint16_t* io, uint16_t control);
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||||
|
||||
struct DS;
|
||||
int32_t DSTimersProcessEvents(struct DS* ds, int32_t cycles);
|
||||
#endif
|
Loading…
Reference in New Issue