mirror of https://github.com/mgba-emu/mgba.git
DS: Port over DMAs
This commit is contained in:
Jeffrey Pfau
parent
66db559f5b
commit
5a55b53983
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@ -0,0 +1,46 @@
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/* Copyright (c) 2013-2017 Jeffrey Pfau
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*
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* This Source Code Form is subject to the terms of the Mozilla Public
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* License, v. 2.0. If a copy of the MPL was not distributed with this
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* file, You can obtain one at http://mozilla.org/MPL/2.0/. */
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#ifndef DS_DMA_H
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#define DS_DMA_H
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#include <mgba-util/common.h>
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CXX_GUARD_START
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#include <mgba/internal/gba/dma.h>
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enum DSDMATiming {
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DS_DMA_TIMING_NOW = 0,
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DS_DMA_TIMING_VBLANK = 1,
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DS_DMA_TIMING_HBLANK = 2,
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DS7_DMA_TIMING_SLOT1 = 2,
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DS_DMA_TIMING_DISPLAY_START = 3,
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DS7_DMA_TIMING_CUSTOM = 3,
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DS_DMA_TIMING_MEMORY_DISPLAY = 4,
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DS9_DMA_TIMING_SLOT1 = 5,
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DS_DMA_TIMING_SLOT2 = 6,
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DS_DMA_TIMING_GEOM_FIFO = 7,
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};
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DECL_BITS(GBADMARegister, Timing9, 11, 3);
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struct DS;
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struct DSCommon;
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void DSDMAInit(struct DS* ds);
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void DSDMAReset(struct DSCommon* dscore);
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uint32_t DSDMAWriteSAD(struct DSCommon* dscore, int dma, uint32_t address);
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uint32_t DSDMAWriteDAD(struct DSCommon* dscore, int dma, uint32_t address);
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void DS7DMAWriteCNT(struct DSCommon* dscore, int dma, uint32_t value);
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void DS9DMAWriteCNT(struct DSCommon* dscore, int dma, uint32_t value);
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struct DSDMA;
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void DSDMASchedule(struct DSCommon* dscore, int number, struct GBADMA* info);
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void DSDMAUpdate(struct DSCommon* dscore);
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CXX_GUARD_END
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#endif
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@ -10,8 +10,10 @@
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CXX_GUARD_START
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#include <mgba/internal/arm/arm.h>
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#include <mgba/core/log.h>
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#include <mgba/core/timing.h>
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#include <mgba/internal/arm/arm.h>
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#include <mgba/internal/ds/dma.h>
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#include <mgba/internal/ds/io.h>
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enum DSMemoryRegion {
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@ -65,50 +67,8 @@ enum {
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DS_BASE_OFFSET = 24
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};
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enum DSDMAControl {
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DS_DMA_INCREMENT = 0,
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DS_DMA_DECREMENT = 1,
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DS_DMA_FIXED = 2,
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DS_DMA_INCREMENT_RELOAD = 3
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};
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enum DSDMATiming {
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DS_DMA_TIMING_NOW = 0,
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DS_DMA_TIMING_VBLANK = 1,
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DS_DMA_TIMING_HBLANK = 2,
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DS7_DMA_TIMING_SLOT1 = 2,
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DS_DMA_TIMING_DISPLAY_START = 3,
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DS7_DMA_TIMING_CUSTOM = 3,
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DS_DMA_TIMING_MEMORY_DISPLAY = 4,
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DS9_DMA_TIMING_SLOT1 = 5,
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DS_DMA_TIMING_SLOT2 = 6,
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DS_DMA_TIMING_GEOM_FIFO = 7,
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};
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mLOG_DECLARE_CATEGORY(DS_MEM);
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DECL_BITFIELD(DSDMARegister, uint16_t);
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DECL_BITS(DSDMARegister, DestControl, 5, 2);
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DECL_BITS(DSDMARegister, SrcControl, 7, 2);
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DECL_BIT(DSDMARegister, Repeat, 9);
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DECL_BIT(DSDMARegister, Width, 10);
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DECL_BITS(DSDMARegister, Timing7, 12, 2);
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DECL_BITS(DSDMARegister, Timing9, 11, 3);
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DECL_BIT(DSDMARegister, DoIRQ, 14);
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DECL_BIT(DSDMARegister, Enable, 15);
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struct DSDMA {
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DSDMARegister reg;
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uint32_t source;
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uint32_t dest;
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int32_t count;
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uint32_t nextSource;
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uint32_t nextDest;
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int32_t nextCount;
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int32_t nextEvent;
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};
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struct DSMemory {
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uint32_t* bios7;
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uint32_t* bios9;
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@ -139,7 +99,8 @@ struct DSCoreMemory {
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uint16_t* io;
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int activeRegion;
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struct DSDMA dma[4];
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struct GBADMA dma[4];
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struct mTimingEvent dmaEvent;
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int activeDMA;
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};
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@ -10,6 +10,42 @@
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CXX_GUARD_START
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enum DMAControl {
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DMA_INCREMENT = 0,
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DMA_DECREMENT = 1,
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DMA_FIXED = 2,
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DMA_INCREMENT_RELOAD = 3
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};
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enum DMATiming {
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DMA_TIMING_NOW = 0,
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DMA_TIMING_VBLANK = 1,
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DMA_TIMING_HBLANK = 2,
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DMA_TIMING_CUSTOM = 3
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};
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DECL_BITFIELD(GBADMARegister, uint16_t);
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DECL_BITS(GBADMARegister, DestControl, 5, 2);
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DECL_BITS(GBADMARegister, SrcControl, 7, 2);
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DECL_BIT(GBADMARegister, Repeat, 9);
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DECL_BIT(GBADMARegister, Width, 10);
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DECL_BIT(GBADMARegister, DRQ, 11);
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DECL_BITS(GBADMARegister, Timing, 12, 2);
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DECL_BIT(GBADMARegister, DoIRQ, 14);
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DECL_BIT(GBADMARegister, Enable, 15);
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struct GBADMA {
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GBADMARegister reg;
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uint32_t source;
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uint32_t dest;
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int32_t count;
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uint32_t nextSource;
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uint32_t nextDest;
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int32_t nextCount;
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uint32_t when;
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};
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struct GBA;
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void GBADMAInit(struct GBA* gba);
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void GBADMAReset(struct GBA* gba);
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@ -13,10 +13,13 @@ CXX_GUARD_START
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#include <mgba/core/timing.h>
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#include <mgba/internal/arm/arm.h>
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#include <mgba/internal/gba/dma.h>
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#include <mgba/internal/gba/hardware.h>
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#include <mgba/internal/gba/savedata.h>
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#include <mgba/internal/gba/vfame.h>
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mLOG_DECLARE_CATEGORY(GBA_MEM);
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enum GBAMemoryRegion {
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REGION_BIOS = 0x0,
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REGION_WORKING_RAM = 0x2,
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BASE_OFFSET = 24
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};
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enum DMAControl {
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DMA_INCREMENT = 0,
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DMA_DECREMENT = 1,
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DMA_FIXED = 2,
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DMA_INCREMENT_RELOAD = 3
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};
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enum DMATiming {
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DMA_TIMING_NOW = 0,
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DMA_TIMING_VBLANK = 1,
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DMA_TIMING_HBLANK = 2,
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DMA_TIMING_CUSTOM = 3
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};
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mLOG_DECLARE_CATEGORY(GBA_MEM);
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DECL_BITFIELD(GBADMARegister, uint16_t);
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DECL_BITS(GBADMARegister, DestControl, 5, 2);
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DECL_BITS(GBADMARegister, SrcControl, 7, 2);
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DECL_BIT(GBADMARegister, Repeat, 9);
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DECL_BIT(GBADMARegister, Width, 10);
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DECL_BIT(GBADMARegister, DRQ, 11);
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DECL_BITS(GBADMARegister, Timing, 12, 2);
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DECL_BIT(GBADMARegister, DoIRQ, 14);
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DECL_BIT(GBADMARegister, Enable, 15);
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struct GBADMA {
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GBADMARegister reg;
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uint32_t source;
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uint32_t dest;
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int32_t count;
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uint32_t nextSource;
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uint32_t nextDest;
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int32_t nextCount;
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uint32_t when;
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};
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struct GBAMemory {
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uint32_t* bios;
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uint32_t* wram;
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@ -0,0 +1,199 @@
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/* Copyright (c) 2013-2015 Jeffrey Pfau
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*
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* This Source Code Form is subject to the terms of the Mozilla Public
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* License, v. 2.0. If a copy of the MPL was not distributed with this
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* file, You can obtain one at http://mozilla.org/MPL/2.0/. */
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#include <mgba/internal/ds/dma.h>
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#include <mgba/internal/ds/ds.h>
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#include <mgba/internal/ds/io.h>
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#include <mgba/internal/ds/memory.h>
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static void _dmaEvent(struct mTiming* timing, void* context, uint32_t cyclesLate);
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static void DSDMAService(struct DSCommon* dscore, int number, struct GBADMA* info);
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static const int DMA_OFFSET[] = { 1, -1, 0, 1 };
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void DSDMAInit(struct DS* ds) {
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ds->ds7.memory.dmaEvent.name = "DS7 DMA";
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ds->ds7.memory.dmaEvent.callback = _dmaEvent;
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ds->ds7.memory.dmaEvent.context = &ds->ds7;
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ds->ds7.memory.dmaEvent.priority = 0x40;
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ds->ds9.memory.dmaEvent.name = "DS9 DMA";
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ds->ds9.memory.dmaEvent.callback = _dmaEvent;
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ds->ds9.memory.dmaEvent.context = &ds->ds9;
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ds->ds9.memory.dmaEvent.priority = 0x40;
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}
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void DSDMAReset(struct DSCommon* dscore) {
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memset(dscore->memory.dma, 0, sizeof(dscore->memory.dma));
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int i;
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for (i = 0; i < 4; ++i) {
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// TODO: This is wrong for DS7
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dscore->memory.dma[i].count = 0x200000;
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}
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dscore->memory.activeDMA = -1;
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}
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uint32_t DSDMAWriteSAD(struct DSCommon* dscore, int dma, uint32_t address) {
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address &= 0x0FFFFFFE;
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dscore->memory.dma[dma].source = address;
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return dscore->memory.dma[dma].source;
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}
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uint32_t DSDMAWriteDAD(struct DSCommon* dscore, int dma, uint32_t address) {
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address &= 0x0FFFFFFE;
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dscore->memory.dma[dma].dest = address;
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return dscore->memory.dma[dma].dest;
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}
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void DS7DMAWriteCNT(struct DSCommon* dscore, int dma, uint32_t value) {
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struct DSCoreMemory* memory = &dscore->memory;
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struct GBADMA* currentDma = &memory->dma[dma];
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uint32_t count = value & 0xFFFF;
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currentDma->count = count ? count : (dma == 3 ? 0x10000 : 0x4000);
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int wasEnabled = GBADMARegisterIsEnable(currentDma->reg);
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unsigned control = (value >> 16) & 0xF7E0;
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currentDma->reg = control;
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if (!wasEnabled && GBADMARegisterIsEnable(currentDma->reg)) {
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currentDma->nextSource = currentDma->source;
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currentDma->nextDest = currentDma->dest;
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DSDMASchedule(dscore, dma, currentDma);
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}
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}
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void DS9DMAWriteCNT(struct DSCommon* dscore, int dma, uint32_t value) {
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struct DSCoreMemory* memory = &dscore->memory;
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struct GBADMA* currentDma = &memory->dma[dma];
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uint32_t count = value & 0x1FFFFF;
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currentDma->count = count ? count : 0x200000;
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int wasEnabled = GBADMARegisterIsEnable(currentDma->reg);
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unsigned control = (value >> 16) & 0xFFE0;
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currentDma->reg = control;
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if (!wasEnabled && GBADMARegisterIsEnable(currentDma->reg)) {
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currentDma->nextSource = currentDma->source;
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currentDma->nextDest = currentDma->dest;
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DSDMASchedule(dscore, dma, currentDma);
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}
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}
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void DSDMASchedule(struct DSCommon* dscore, int number, struct GBADMA* info) {
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switch (GBADMARegisterGetTiming(info->reg)) {
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case DS_DMA_TIMING_NOW:
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info->when = mTimingCurrentTime(&dscore->timing) + 3; // DMAs take 3 cycles to start
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info->nextCount = info->count;
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break;
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case DS_DMA_TIMING_HBLANK:
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case DS_DMA_TIMING_VBLANK:
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// Handled implicitly
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return;
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default:
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mLOG(DS_MEM, STUB, "Unimplemented DMA");
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}
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DSDMAUpdate(dscore);
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}
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void _dmaEvent(struct mTiming* timing, void* context, uint32_t cyclesLate) {
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UNUSED(timing);
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UNUSED(cyclesLate);
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struct DSCommon* dscore = context;
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struct DSCoreMemory* memory = &dscore->memory;
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struct GBADMA* dma = &memory->dma[memory->activeDMA];
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if (dma->nextCount == dma->count) {
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dma->when = mTimingCurrentTime(&dscore->timing);
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}
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if (dma->nextCount & 0xFFFFF) {
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dscore->p->cpuBlocked = true; // TODO: Fix for ITCM
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DSDMAService(dscore, memory->activeDMA, dma);
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} else {
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dma->nextCount = 0;
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if (!GBADMARegisterIsRepeat(dma->reg) || GBADMARegisterGetTiming(dma->reg) == DMA_TIMING_NOW) {
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dma->reg = GBADMARegisterClearEnable(dma->reg);
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// Clear the enable bit in memory
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memory->io[(DS_REG_DMA0CNT_HI + memory->activeDMA * (DS_REG_DMA1CNT_HI - DS_REG_DMA0CNT_HI)) >> 1] &= 0x7FE0;
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}
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if (GBADMARegisterGetDestControl(dma->reg) == DMA_INCREMENT_RELOAD) {
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dma->nextDest = dma->dest;
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}
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if (GBADMARegisterIsDoIRQ(dma->reg)) {
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DSRaiseIRQ(dscore->cpu, dscore->memory.io, DS_IRQ_DMA0 + memory->activeDMA);
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}
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DSDMAUpdate(dscore);
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}
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}
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void DSDMAUpdate(struct DSCommon* dscore) {
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int i;
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struct DSCoreMemory* memory = &dscore->memory;
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memory->activeDMA = -1;
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uint32_t currentTime = mTimingCurrentTime(&dscore->timing);
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for (i = 0; i < 4; ++i) {
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struct GBADMA* dma = &memory->dma[i];
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if (GBADMARegisterIsEnable(dma->reg) && dma->nextCount) {
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memory->activeDMA = i;
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break;
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}
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}
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if (memory->activeDMA >= 0) {
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mTimingDeschedule(&dscore->timing, &memory->dmaEvent);
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mTimingSchedule(&dscore->timing, &memory->dmaEvent, memory->dma[memory->activeDMA].when - currentTime);
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} else {
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dscore->p->cpuBlocked = false;
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}
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}
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void DSDMAService(struct DSCommon* dscore, int number, struct GBADMA* info) {
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struct DSCoreMemory* memory = &dscore->memory;
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struct ARMCore* cpu = dscore->cpu;
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uint32_t width = 2 << GBADMARegisterGetWidth(info->reg);
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int32_t wordsRemaining = info->nextCount;
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uint32_t source = info->nextSource;
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uint32_t dest = info->nextDest;
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uint32_t sourceRegion = source >> DS_BASE_OFFSET;
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uint32_t destRegion = dest >> DS_BASE_OFFSET;
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int32_t cycles = 2;
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if (info->count == info->nextCount) {
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if (width == 4) {
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cycles += dscore->p->memory.waitstatesNonseq32[sourceRegion] + dscore->p->memory.waitstatesNonseq32[destRegion];
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} else {
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cycles += dscore->p->memory.waitstatesNonseq16[sourceRegion] + dscore->p->memory.waitstatesNonseq16[destRegion];
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}
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source &= -width;
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dest &= -width;
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} else {
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if (width == 4) {
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cycles += dscore->p->memory.waitstatesSeq32[sourceRegion] + dscore->p->memory.waitstatesSeq32[destRegion];
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} else {
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cycles += dscore->p->memory.waitstatesSeq16[sourceRegion] + dscore->p->memory.waitstatesSeq16[destRegion];
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}
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}
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info->when += cycles;
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uint32_t word;
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if (width == 4) {
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word = cpu->memory.load32(cpu, source, 0);
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cpu->memory.store32(cpu, dest, word, 0);
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} else {
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word = cpu->memory.load16(cpu, source, 0);
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cpu->memory.store16(cpu, dest, word, 0);
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}
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int sourceOffset = DMA_OFFSET[GBADMARegisterGetSrcControl(info->reg)] * width;
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int destOffset = DMA_OFFSET[GBADMARegisterGetDestControl(info->reg)] * width;
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source += sourceOffset;
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dest += destOffset;
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--wordsRemaining;
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info->nextCount = wordsRemaining;
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info->nextSource = source;
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info->nextDest = dest;
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if (!wordsRemaining) {
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info->nextCount |= 0x80000000;
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}
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DSDMAUpdate(dscore);
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}
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@ -111,6 +111,7 @@ static void DSInit(void* cpu, struct mCPUComponent* component) {
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DS7InterruptHandlerInit(&ds->ds7.cpu->irqh);
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DS9InterruptHandlerInit(&ds->ds9.cpu->irqh);
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DSMemoryInit(ds);
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DSDMAInit(ds);
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ds->video.p = ds;
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@ -183,6 +184,7 @@ void DS7Reset(struct ARMCore* cpu) {
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mTimingClear(&ds->ds7.timing);
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CircleBufferInit(&ds->ds7.fifo, 64);
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DSMemoryReset(ds);
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DSDMAReset(&ds->ds7);
|
||||
DS7IOInit(ds);
|
||||
|
||||
struct DSCartridge* header = ds->romVf->map(ds->romVf, sizeof(*header), MAP_READ);
|
||||
|
|
@ -215,6 +217,7 @@ void DS9Reset(struct ARMCore* cpu) {
|
|||
struct DS* ds = (struct DS*) cpu->master;
|
||||
mTimingClear(&ds->ds9.timing);
|
||||
CircleBufferInit(&ds->ds9.fifo, 64);
|
||||
DSDMAReset(&ds->ds9);
|
||||
DS9IOInit(ds);
|
||||
|
||||
ds->activeCpu = cpu;
|
||||
|
|
|
|||
80
src/ds/io.c
80
src/ds/io.c
|
|
@ -113,8 +113,47 @@ void DS7IOWrite8(struct DS* ds, uint32_t address, uint8_t value) {
|
|||
|
||||
void DS7IOWrite32(struct DS* ds, uint32_t address, uint32_t value) {
|
||||
switch (address) {
|
||||
case DS_REG_DMA0SAD_LO:
|
||||
value = DSDMAWriteSAD(&ds->ds7, 0, value);
|
||||
break;
|
||||
case DS_REG_DMA1SAD_LO:
|
||||
value = DSDMAWriteSAD(&ds->ds7, 1, value);
|
||||
break;
|
||||
case DS_REG_DMA2SAD_LO:
|
||||
value = DSDMAWriteSAD(&ds->ds7, 2, value);
|
||||
break;
|
||||
case DS_REG_DMA3SAD_LO:
|
||||
value = DSDMAWriteSAD(&ds->ds7, 3, value);
|
||||
break;
|
||||
|
||||
case DS_REG_DMA0DAD_LO:
|
||||
value = DSDMAWriteDAD(&ds->ds7, 0, value);
|
||||
break;
|
||||
case DS_REG_DMA1DAD_LO:
|
||||
value = DSDMAWriteDAD(&ds->ds7, 1, value);
|
||||
break;
|
||||
case DS_REG_DMA2DAD_LO:
|
||||
value = DSDMAWriteDAD(&ds->ds7, 2, value);
|
||||
break;
|
||||
case DS_REG_DMA3DAD_LO:
|
||||
value = DSDMAWriteDAD(&ds->ds7, 3, value);
|
||||
break;
|
||||
|
||||
case DS_REG_DMA0CNT_LO:
|
||||
DS7DMAWriteCNT(&ds->ds7, 0, value);
|
||||
break;
|
||||
case DS_REG_DMA1CNT_LO:
|
||||
DS7DMAWriteCNT(&ds->ds7, 1, value);
|
||||
break;
|
||||
case DS_REG_DMA2CNT_LO:
|
||||
DS7DMAWriteCNT(&ds->ds7, 2, value);
|
||||
break;
|
||||
case DS_REG_DMA3CNT_LO:
|
||||
DS7DMAWriteCNT(&ds->ds7, 3, value);
|
||||
break;
|
||||
|
||||
case DS_REG_IPCFIFOSEND_LO:
|
||||
DSIPCWriteFIFO(&ds->ds9, value);
|
||||
DSIPCWriteFIFO(&ds->ds7, value);
|
||||
break;
|
||||
case DS_REG_IE_LO:
|
||||
DSWriteIE(ds->ds7.cpu, ds->ds7.memory.io, value);
|
||||
|
|
@ -189,6 +228,45 @@ void DS9IOWrite8(struct DS* ds, uint32_t address, uint8_t value) {
|
|||
|
||||
void DS9IOWrite32(struct DS* ds, uint32_t address, uint32_t value) {
|
||||
switch (address) {
|
||||
case DS_REG_DMA0SAD_LO:
|
||||
value = DSDMAWriteSAD(&ds->ds9, 0, value);
|
||||
break;
|
||||
case DS_REG_DMA1SAD_LO:
|
||||
value = DSDMAWriteSAD(&ds->ds9, 1, value);
|
||||
break;
|
||||
case DS_REG_DMA2SAD_LO:
|
||||
value = DSDMAWriteSAD(&ds->ds9, 2, value);
|
||||
break;
|
||||
case DS_REG_DMA3SAD_LO:
|
||||
value = DSDMAWriteSAD(&ds->ds9, 3, value);
|
||||
break;
|
||||
|
||||
case DS_REG_DMA0DAD_LO:
|
||||
value = DSDMAWriteDAD(&ds->ds9, 0, value);
|
||||
break;
|
||||
case DS_REG_DMA1DAD_LO:
|
||||
value = DSDMAWriteDAD(&ds->ds9, 1, value);
|
||||
break;
|
||||
case DS_REG_DMA2DAD_LO:
|
||||
value = DSDMAWriteDAD(&ds->ds9, 2, value);
|
||||
break;
|
||||
case DS_REG_DMA3DAD_LO:
|
||||
value = DSDMAWriteDAD(&ds->ds9, 3, value);
|
||||
break;
|
||||
|
||||
case DS_REG_DMA0CNT_LO:
|
||||
DS9DMAWriteCNT(&ds->ds9, 0, value);
|
||||
break;
|
||||
case DS_REG_DMA1CNT_LO:
|
||||
DS9DMAWriteCNT(&ds->ds9, 1, value);
|
||||
break;
|
||||
case DS_REG_DMA2CNT_LO:
|
||||
DS9DMAWriteCNT(&ds->ds9, 2, value);
|
||||
break;
|
||||
case DS_REG_DMA3CNT_LO:
|
||||
DS9DMAWriteCNT(&ds->ds9, 3, value);
|
||||
break;
|
||||
|
||||
case DS_REG_IPCFIFOSEND_LO:
|
||||
DSIPCWriteFIFO(&ds->ds9, value);
|
||||
break;
|
||||
|
|
|
|||
|
|
@ -77,8 +77,6 @@ static void DS7SetActiveRegion(struct ARMCore* cpu, uint32_t region);
|
|||
static void DS9SetActiveRegion(struct ARMCore* cpu, uint32_t region);
|
||||
static int32_t DSMemoryStall(struct ARMCore* cpu, int32_t wait);
|
||||
|
||||
static const int DMA_OFFSET[] = { 1, -1, 0, 1 };
|
||||
|
||||
void DSMemoryInit(struct DS* ds) {
|
||||
struct ARMCore* arm7 = ds->ds7.cpu;
|
||||
arm7->memory.load32 = DS7Load32;
|
||||
|
|
|
|||
Loading…
Reference in New Issue