2013-11-01 07:50:42 +00:00
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#include "decoder.h"
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2013-10-31 06:22:38 +00:00
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2013-11-02 07:34:49 +00:00
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#include "decoder-inlines.h"
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2013-11-01 07:47:12 +00:00
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#include "emitter-thumb.h"
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#include "isa-inlines.h"
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#define DEFINE_THUMB_DECODER(NAME, MNEMONIC, BODY) \
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2014-07-10 10:30:59 +00:00
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static void _ThumbDecode ## NAME (uint16_t opcode, struct ARMInstructionInfo* info) { \
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2013-11-01 07:47:12 +00:00
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UNUSED(opcode); \
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2014-07-10 10:30:59 +00:00
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info->mnemonic = ARM_MN_ ## MNEMONIC; \
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2013-11-01 07:47:12 +00:00
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BODY; \
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}
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2013-11-09 21:49:34 +00:00
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#define DEFINE_IMMEDIATE_5_DECODER_DATA_THUMB(NAME, IMMEDIATE, MNEMONIC, WIDTH) \
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2013-11-01 07:47:12 +00:00
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DEFINE_THUMB_DECODER(NAME, MNEMONIC, \
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info->op3.immediate = IMMEDIATE; \
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info->op1.reg = opcode & 0x0007; \
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info->op2.reg = (opcode >> 3) & 0x0007; \
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info->affectsCPSR = 1; \
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info->operandFormat = ARM_OPERAND_REGISTER_1 | \
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ARM_OPERAND_AFFECTED_1 | \
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ARM_OPERAND_REGISTER_2 | \
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ARM_OPERAND_IMMEDIATE_3;)
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2013-11-09 21:49:34 +00:00
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#define DEFINE_IMMEDIATE_5_DECODER_MEM_THUMB(NAME, IMMEDIATE, MNEMONIC, CYCLES, WIDTH) \
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2013-11-01 07:47:12 +00:00
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DEFINE_THUMB_DECODER(NAME, MNEMONIC, \
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info->op1.reg = opcode & 0x0007; \
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info->memory.baseReg = (opcode >> 3) & 0x0007; \
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2013-11-09 21:49:34 +00:00
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info->memory.offset.immediate = IMMEDIATE * WIDTH; \
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2014-07-10 10:30:59 +00:00
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info->memory.width = (enum ARMMemoryAccessType) WIDTH; \
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2013-11-01 07:47:12 +00:00
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info->operandFormat = ARM_OPERAND_REGISTER_1 | \
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ARM_OPERAND_AFFECTED_1 | \
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ARM_OPERAND_MEMORY_2; \
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info->memory.format = ARM_MEMORY_REGISTER_BASE | \
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2013-11-02 09:52:53 +00:00
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ARM_MEMORY_IMMEDIATE_OFFSET; \
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CYCLES)
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2013-11-09 21:49:34 +00:00
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#define DEFINE_IMMEDIATE_5_DECODER_MEM_LOAD_THUMB(NAME, IMMEDIATE, MNEMONIC, WIDTH) \
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DEFINE_IMMEDIATE_5_DECODER_MEM_THUMB(NAME, IMMEDIATE, MNEMONIC, LOAD_CYCLES, WIDTH)
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2013-11-02 09:52:53 +00:00
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2013-11-09 21:49:34 +00:00
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#define DEFINE_IMMEDIATE_5_DECODER_MEM_STORE_THUMB(NAME, IMMEDIATE, MNEMONIC, WIDTH) \
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DEFINE_IMMEDIATE_5_DECODER_MEM_THUMB(NAME, IMMEDIATE, MNEMONIC, STORE_CYCLES, WIDTH)
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2013-11-01 07:47:12 +00:00
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2013-11-09 21:49:34 +00:00
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#define DEFINE_IMMEDIATE_5_DECODER_THUMB(NAME, MNEMONIC, TYPE, WIDTH) \
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2014-07-16 06:30:55 +00:00
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COUNT_CALL_5(DEFINE_IMMEDIATE_5_DECODER_ ## TYPE ## _THUMB, NAME ## _, MNEMONIC, WIDTH)
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2013-11-01 07:47:12 +00:00
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2013-11-09 21:49:34 +00:00
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DEFINE_IMMEDIATE_5_DECODER_THUMB(LSL1, LSL, DATA,)
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DEFINE_IMMEDIATE_5_DECODER_THUMB(LSR1, LSR, DATA,)
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DEFINE_IMMEDIATE_5_DECODER_THUMB(ASR1, ASR, DATA,)
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DEFINE_IMMEDIATE_5_DECODER_THUMB(LDR1, LDR, MEM_LOAD, 4)
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2014-07-10 10:30:59 +00:00
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DEFINE_IMMEDIATE_5_DECODER_THUMB(LDRB1, LDR, MEM_LOAD, 1)
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DEFINE_IMMEDIATE_5_DECODER_THUMB(LDRH1, LDR, MEM_LOAD, 2)
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2013-11-09 21:49:34 +00:00
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DEFINE_IMMEDIATE_5_DECODER_THUMB(STR1, STR, MEM_STORE, 4)
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2014-07-10 10:30:59 +00:00
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DEFINE_IMMEDIATE_5_DECODER_THUMB(STRB1, STR, MEM_STORE, 1)
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DEFINE_IMMEDIATE_5_DECODER_THUMB(STRH1, STR, MEM_STORE, 2)
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2013-11-01 07:47:12 +00:00
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#define DEFINE_DATA_FORM_1_DECODER_EX_THUMB(NAME, RM, MNEMONIC) \
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DEFINE_THUMB_DECODER(NAME, MNEMONIC, \
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info->op1.reg = opcode & 0x0007; \
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info->op2.reg = (opcode >> 3) & 0x0007; \
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info->op3.reg = RM; \
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info->affectsCPSR = 1; \
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info->operandFormat = ARM_OPERAND_REGISTER_1 | \
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ARM_OPERAND_AFFECTED_1 | \
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ARM_OPERAND_REGISTER_2 | \
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ARM_OPERAND_REGISTER_3;)
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#define DEFINE_DATA_FORM_1_DECODER_THUMB(NAME) \
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2014-07-16 06:30:55 +00:00
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COUNT_CALL_3(DEFINE_DATA_FORM_1_DECODER_EX_THUMB, NAME ## 3_R, NAME)
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2013-11-01 07:47:12 +00:00
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2013-11-02 09:52:53 +00:00
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DEFINE_DATA_FORM_1_DECODER_THUMB(ADD)
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2013-11-01 07:47:12 +00:00
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DEFINE_DATA_FORM_1_DECODER_THUMB(SUB)
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#define DEFINE_DATA_FORM_2_DECODER_EX_THUMB(NAME, IMMEDIATE, MNEMONIC) \
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DEFINE_THUMB_DECODER(NAME, MNEMONIC, \
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info->op1.reg = opcode & 0x0007; \
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info->op2.reg = (opcode >> 3) & 0x0007; \
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info->op3.immediate = IMMEDIATE; \
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info->affectsCPSR = 1; \
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info->operandFormat = ARM_OPERAND_REGISTER_1 | \
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ARM_OPERAND_AFFECTED_1 | \
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ARM_OPERAND_REGISTER_2 | \
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ARM_OPERAND_IMMEDIATE_3;)
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#define DEFINE_DATA_FORM_2_DECODER_THUMB(NAME) \
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2014-07-16 06:30:55 +00:00
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COUNT_CALL_3(DEFINE_DATA_FORM_2_DECODER_EX_THUMB, NAME ## 1_, NAME)
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2013-11-01 07:47:12 +00:00
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DEFINE_DATA_FORM_2_DECODER_THUMB(ADD)
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DEFINE_DATA_FORM_2_DECODER_THUMB(SUB)
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#define DEFINE_DATA_FORM_3_DECODER_EX_THUMB(NAME, RD, MNEMONIC, AFFECTED) \
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DEFINE_THUMB_DECODER(NAME, MNEMONIC, \
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info->op1.reg = RD; \
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info->op2.immediate = opcode & 0x00FF; \
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info->affectsCPSR = 1; \
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info->operandFormat = ARM_OPERAND_REGISTER_1 | \
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AFFECTED | \
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ARM_OPERAND_IMMEDIATE_2;)
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#define DEFINE_DATA_FORM_3_DECODER_THUMB(NAME, MNEMONIC, AFFECTED) \
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2014-07-16 06:30:55 +00:00
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COUNT_CALL_3(DEFINE_DATA_FORM_3_DECODER_EX_THUMB, NAME ## _R, MNEMONIC, AFFECTED)
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2013-11-01 07:47:12 +00:00
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DEFINE_DATA_FORM_3_DECODER_THUMB(ADD2, ADD, ARM_OPERAND_AFFECTED_1)
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DEFINE_DATA_FORM_3_DECODER_THUMB(CMP1, CMP, ARM_OPERAND_NONE)
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DEFINE_DATA_FORM_3_DECODER_THUMB(MOV1, MOV, ARM_OPERAND_AFFECTED_1)
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DEFINE_DATA_FORM_3_DECODER_THUMB(SUB2, SUB, ARM_OPERAND_AFFECTED_1)
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#define DEFINE_DATA_FORM_5_DECODER_THUMB(NAME, MNEMONIC, AFFECTED) \
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DEFINE_THUMB_DECODER(NAME, MNEMONIC, \
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info->op1.reg = opcode & 0x0007; \
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info->op2.reg = (opcode >> 3) & 0x0007; \
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info->affectsCPSR = 1; \
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info->operandFormat = ARM_OPERAND_REGISTER_1 | \
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AFFECTED | \
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ARM_OPERAND_REGISTER_2;)
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DEFINE_DATA_FORM_5_DECODER_THUMB(AND, AND, ARM_OPERAND_AFFECTED_1)
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DEFINE_DATA_FORM_5_DECODER_THUMB(EOR, EOR, ARM_OPERAND_AFFECTED_1)
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DEFINE_DATA_FORM_5_DECODER_THUMB(LSL2, LSL, ARM_OPERAND_AFFECTED_1)
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DEFINE_DATA_FORM_5_DECODER_THUMB(LSR2, LSR, ARM_OPERAND_AFFECTED_1)
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DEFINE_DATA_FORM_5_DECODER_THUMB(ASR2, ASR, ARM_OPERAND_AFFECTED_1)
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DEFINE_DATA_FORM_5_DECODER_THUMB(ADC, ADC, ARM_OPERAND_AFFECTED_1)
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DEFINE_DATA_FORM_5_DECODER_THUMB(SBC, SBC, ARM_OPERAND_AFFECTED_1)
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DEFINE_DATA_FORM_5_DECODER_THUMB(ROR, ROR, ARM_OPERAND_AFFECTED_1)
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2014-07-11 08:26:57 +00:00
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DEFINE_DATA_FORM_5_DECODER_THUMB(TST, TST, ARM_OPERAND_NONE)
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2013-11-01 07:47:12 +00:00
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DEFINE_DATA_FORM_5_DECODER_THUMB(NEG, NEG, ARM_OPERAND_AFFECTED_1)
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DEFINE_DATA_FORM_5_DECODER_THUMB(CMP2, CMP, ARM_OPERAND_NONE)
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DEFINE_DATA_FORM_5_DECODER_THUMB(CMN, CMN, ARM_OPERAND_NONE)
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DEFINE_DATA_FORM_5_DECODER_THUMB(ORR, ORR, ARM_OPERAND_AFFECTED_1)
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DEFINE_DATA_FORM_5_DECODER_THUMB(MUL, MUL, ARM_OPERAND_AFFECTED_1)
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DEFINE_DATA_FORM_5_DECODER_THUMB(BIC, BIC, ARM_OPERAND_AFFECTED_1)
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2013-11-02 09:52:53 +00:00
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DEFINE_DATA_FORM_5_DECODER_THUMB(MVN, MVN, ARM_OPERAND_AFFECTED_1)
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2013-11-01 07:47:12 +00:00
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#define DEFINE_DECODER_WITH_HIGH_EX_THUMB(NAME, H1, H2, MNEMONIC, AFFECTED, CPSR) \
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DEFINE_THUMB_DECODER(NAME, MNEMONIC, \
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info->op1.reg = (opcode & 0x0007) | H1; \
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info->op2.reg = ((opcode >> 3) & 0x0007) | H2; \
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2013-11-03 00:07:58 +00:00
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info->branches = info->op1.reg == ARM_PC; \
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2013-11-01 07:47:12 +00:00
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info->affectsCPSR = CPSR; \
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info->operandFormat = ARM_OPERAND_REGISTER_1 | \
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AFFECTED | \
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ARM_OPERAND_REGISTER_2;)
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#define DEFINE_DECODER_WITH_HIGH_THUMB(NAME, MNEMONIC, AFFECTED, CPSR) \
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DEFINE_DECODER_WITH_HIGH_EX_THUMB(NAME ## 00, 0, 0, MNEMONIC, AFFECTED, CPSR) \
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DEFINE_DECODER_WITH_HIGH_EX_THUMB(NAME ## 01, 0, 8, MNEMONIC, AFFECTED, CPSR) \
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DEFINE_DECODER_WITH_HIGH_EX_THUMB(NAME ## 10, 8, 0, MNEMONIC, AFFECTED, CPSR) \
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DEFINE_DECODER_WITH_HIGH_EX_THUMB(NAME ## 11, 8, 8, MNEMONIC, AFFECTED, CPSR)
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DEFINE_DECODER_WITH_HIGH_THUMB(ADD4, ADD, ARM_OPERAND_AFFECTED_1, 0)
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DEFINE_DECODER_WITH_HIGH_THUMB(CMP3, CMP, ARM_OPERAND_NONE, 1)
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DEFINE_DECODER_WITH_HIGH_THUMB(MOV3, MOV, ARM_OPERAND_AFFECTED_1, 0)
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#define DEFINE_IMMEDIATE_WITH_REGISTER_DATA_THUMB(NAME, RD, MNEMONIC, REG) \
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DEFINE_THUMB_DECODER(NAME, MNEMONIC, \
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info->op1.reg = RD; \
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info->op2.reg = REG; \
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info->op3.immediate = (opcode & 0x00FF) << 2; \
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info->operandFormat = ARM_OPERAND_REGISTER_1 | \
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ARM_OPERAND_AFFECTED_1 | \
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ARM_OPERAND_REGISTER_2 | \
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ARM_OPERAND_IMMEDIATE_3;)
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2013-11-02 09:52:53 +00:00
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#define DEFINE_IMMEDIATE_WITH_REGISTER_MEM_THUMB(NAME, RD, MNEMONIC, REG, CYCLES) \
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2013-11-01 07:47:12 +00:00
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DEFINE_THUMB_DECODER(NAME, MNEMONIC, \
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info->op1.reg = RD; \
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info->memory.baseReg = REG; \
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info->memory.offset.immediate = (opcode & 0x00FF) << 2; \
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2014-07-10 10:30:59 +00:00
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info->memory.width = ARM_ACCESS_WORD; \
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2013-11-01 07:47:12 +00:00
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info->operandFormat = ARM_OPERAND_REGISTER_1 | \
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ARM_OPERAND_AFFECTED_1 | \
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ARM_OPERAND_MEMORY_2; \
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info->memory.format = ARM_MEMORY_REGISTER_BASE | \
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2013-11-02 09:52:53 +00:00
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ARM_MEMORY_IMMEDIATE_OFFSET; \
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CYCLES;)
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#define DEFINE_IMMEDIATE_WITH_REGISTER_MEM_LOAD_THUMB(NAME, RD, MNEMONIC, REG) \
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DEFINE_IMMEDIATE_WITH_REGISTER_MEM_THUMB(NAME, RD, MNEMONIC, REG, LOAD_CYCLES)
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#define DEFINE_IMMEDIATE_WITH_REGISTER_MEM_STORE_THUMB(NAME, RD, MNEMONIC, REG) \
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DEFINE_IMMEDIATE_WITH_REGISTER_MEM_THUMB(NAME, RD, MNEMONIC, REG, STORE_CYCLES)
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2013-11-01 07:47:12 +00:00
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#define DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(NAME, MNEMONIC, TYPE, REG) \
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2014-07-16 06:30:55 +00:00
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COUNT_CALL_3(DEFINE_IMMEDIATE_WITH_REGISTER_ ## TYPE ## _THUMB, NAME ## _R, MNEMONIC, REG)
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2013-11-01 07:47:12 +00:00
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2013-11-02 09:52:53 +00:00
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DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(LDR3, LDR, MEM_LOAD, ARM_PC)
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DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(LDR4, LDR, MEM_LOAD, ARM_SP)
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DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(STR3, STR, MEM_STORE, ARM_SP)
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2013-11-01 07:47:12 +00:00
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DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(ADD5, ADD, DATA, ARM_PC)
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DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(ADD6, ADD, DATA, ARM_SP)
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2014-07-10 10:30:59 +00:00
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#define DEFINE_LOAD_STORE_WITH_REGISTER_EX_THUMB(NAME, RM, MNEMONIC, CYCLES, TYPE) \
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2013-11-01 07:47:12 +00:00
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DEFINE_THUMB_DECODER(NAME, MNEMONIC, \
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info->memory.offset.reg = RM; \
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info->op1.reg = opcode & 0x0007; \
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info->memory.baseReg = (opcode >> 3) & 0x0007; \
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2014-07-10 10:30:59 +00:00
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info->memory.width = TYPE; \
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2013-11-01 07:47:12 +00:00
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info->operandFormat = ARM_OPERAND_REGISTER_1 | \
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2014-07-11 10:19:02 +00:00
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ARM_OPERAND_AFFECTED_1 | /* TODO: Remove this for STR */ \
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2013-11-01 07:47:12 +00:00
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ARM_OPERAND_MEMORY_2; \
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info->memory.format = ARM_MEMORY_REGISTER_BASE | \
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2013-11-02 09:52:53 +00:00
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ARM_MEMORY_REGISTER_OFFSET; \
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CYCLES;)
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2013-11-01 07:47:12 +00:00
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2014-07-10 10:30:59 +00:00
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#define DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(NAME, MNEMONIC, CYCLES, TYPE) \
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2014-07-16 06:30:55 +00:00
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COUNT_CALL_3(DEFINE_LOAD_STORE_WITH_REGISTER_EX_THUMB, NAME ## _R, MNEMONIC, CYCLES, TYPE)
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2013-11-01 07:47:12 +00:00
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2014-07-10 10:30:59 +00:00
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DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDR2, LDR, LOAD_CYCLES, ARM_ACCESS_WORD)
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DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDRB2, LDR, LOAD_CYCLES, ARM_ACCESS_BYTE)
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DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDRH2, LDR, LOAD_CYCLES, ARM_ACCESS_HALFWORD)
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DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDRSB, LDR, LOAD_CYCLES, ARM_ACCESS_SIGNED_BYTE)
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DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDRSH, LDR, LOAD_CYCLES, ARM_ACCESS_SIGNED_HALFWORD)
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DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(STR2, STR, STORE_CYCLES, ARM_ACCESS_WORD)
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DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(STRB2, STR, STORE_CYCLES, ARM_ACCESS_BYTE)
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DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(STRH2, STR, STORE_CYCLES, ARM_ACCESS_HALFWORD)
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2013-11-01 07:47:12 +00:00
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2014-07-11 10:19:02 +00:00
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// TODO: Estimate memory cycles
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2014-07-10 10:30:59 +00:00
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#define DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(NAME, RN, MNEMONIC, DIRECTION, ADDITIONAL_REG) \
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2013-11-01 07:47:12 +00:00
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DEFINE_THUMB_DECODER(NAME, MNEMONIC, \
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info->memory.baseReg = RN; \
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2013-11-01 08:47:04 +00:00
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info->op1.immediate = (opcode & 0xFF) | ADDITIONAL_REG; \
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2013-11-03 00:07:58 +00:00
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info->branches = info->op1.immediate & (1 << ARM_PC); \
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2013-11-02 11:12:21 +00:00
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info->operandFormat = ARM_OPERAND_MEMORY_1; \
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2013-11-01 07:47:12 +00:00
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info->memory.format = ARM_MEMORY_REGISTER_BASE | \
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2014-07-11 10:19:02 +00:00
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ARM_MEMORY_WRITEBACK | \
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DIRECTION;)
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2013-11-01 07:47:12 +00:00
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#define DEFINE_LOAD_STORE_MULTIPLE_THUMB(NAME) \
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2014-07-16 06:30:55 +00:00
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COUNT_CALL_3(DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB, NAME ## IA_R, NAME, ARM_MEMORY_INCREMENT_AFTER, 0)
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2013-11-01 07:47:12 +00:00
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2014-07-10 10:30:59 +00:00
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DEFINE_LOAD_STORE_MULTIPLE_THUMB(LDM)
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DEFINE_LOAD_STORE_MULTIPLE_THUMB(STM)
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2013-11-01 07:47:12 +00:00
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#define DEFINE_CONDITIONAL_BRANCH_THUMB(COND) \
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DEFINE_THUMB_DECODER(B ## COND, B, \
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int8_t immediate = opcode; \
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2013-11-02 05:29:55 +00:00
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info->op1.immediate = immediate << 1; \
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2013-11-01 07:47:12 +00:00
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info->branches = 1; \
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2013-11-02 05:29:55 +00:00
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info->condition = ARM_CONDITION_ ## COND; \
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2013-11-01 07:47:12 +00:00
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info->operandFormat = ARM_OPERAND_IMMEDIATE_1;)
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DEFINE_CONDITIONAL_BRANCH_THUMB(EQ)
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DEFINE_CONDITIONAL_BRANCH_THUMB(NE)
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DEFINE_CONDITIONAL_BRANCH_THUMB(CS)
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DEFINE_CONDITIONAL_BRANCH_THUMB(CC)
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DEFINE_CONDITIONAL_BRANCH_THUMB(MI)
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DEFINE_CONDITIONAL_BRANCH_THUMB(PL)
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DEFINE_CONDITIONAL_BRANCH_THUMB(VS)
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DEFINE_CONDITIONAL_BRANCH_THUMB(VC)
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DEFINE_CONDITIONAL_BRANCH_THUMB(LS)
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DEFINE_CONDITIONAL_BRANCH_THUMB(HI)
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DEFINE_CONDITIONAL_BRANCH_THUMB(GE)
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DEFINE_CONDITIONAL_BRANCH_THUMB(LT)
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DEFINE_CONDITIONAL_BRANCH_THUMB(GT)
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DEFINE_CONDITIONAL_BRANCH_THUMB(LE)
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#define DEFINE_SP_MODIFY_THUMB(NAME, MNEMONIC) \
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DEFINE_THUMB_DECODER(NAME, MNEMONIC, \
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info->op1.reg = ARM_SP; \
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info->op2.immediate = (opcode & 0x7F) << 2; \
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info->operandFormat = ARM_OPERAND_REGISTER_1 | \
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ARM_OPERAND_AFFECTED_1 | \
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ARM_OPERAND_IMMEDIATE_2;)
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DEFINE_SP_MODIFY_THUMB(ADD7, ADD)
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DEFINE_SP_MODIFY_THUMB(SUB4, SUB)
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2014-07-11 08:27:32 +00:00
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DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(POP, ARM_SP, LDM, ARM_MEMORY_INCREMENT_AFTER, 0)
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DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(POPR, ARM_SP, LDM, ARM_MEMORY_INCREMENT_AFTER, 1 << ARM_PC)
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DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(PUSH, ARM_SP, STM, ARM_MEMORY_DECREMENT_BEFORE, 0)
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DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(PUSHR, ARM_SP, STM, ARM_MEMORY_DECREMENT_BEFORE, 1 << ARM_LR)
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2013-11-01 07:47:12 +00:00
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DEFINE_THUMB_DECODER(ILL, ILL, info->traps = 1;)
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DEFINE_THUMB_DECODER(BKPT, BKPT, info->traps = 1;)
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DEFINE_THUMB_DECODER(B, B,
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int16_t immediate = (opcode & 0x07FF) << 5;
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info->op1.immediate = (((int32_t) immediate) >> 4);
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info->operandFormat = ARM_OPERAND_IMMEDIATE_1;
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info->branches = 1;)
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DEFINE_THUMB_DECODER(BL1, BLH,
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int16_t immediate = (opcode & 0x07FF) << 5;
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info->op1.immediate = (((int32_t) immediate) << 7);
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2014-07-10 09:33:16 +00:00
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info->operandFormat = ARM_OPERAND_IMMEDIATE_1;)
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2013-11-01 07:47:12 +00:00
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DEFINE_THUMB_DECODER(BL2, BL,
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info->op1.immediate = (opcode & 0x07FF) << 1;
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info->operandFormat = ARM_OPERAND_IMMEDIATE_1;
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info->branches = 1;)
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DEFINE_THUMB_DECODER(BX, BX,
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info->op1.reg = (opcode >> 3) & 0xF;
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info->operandFormat = ARM_OPERAND_REGISTER_1;
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info->branches = 1;)
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DEFINE_THUMB_DECODER(SWI, SWI,
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info->op1.immediate = opcode & 0xFF;
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info->operandFormat = ARM_OPERAND_IMMEDIATE_1;
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info->traps = 1;)
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2014-07-10 10:30:59 +00:00
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typedef void (*ThumbDecoder)(uint16_t opcode, struct ARMInstructionInfo* info);
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2013-11-01 07:47:12 +00:00
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static const ThumbDecoder _thumbDecoderTable[0x400] = {
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DECLARE_THUMB_EMITTER_BLOCK(_ThumbDecode)
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};
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2014-07-10 10:30:59 +00:00
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void ARMDecodeThumb(uint16_t opcode, struct ARMInstructionInfo* info) {
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2014-07-12 07:13:11 +00:00
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info->execMode = MODE_THUMB;
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2013-10-31 06:22:38 +00:00
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info->opcode = opcode;
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2013-11-01 07:47:12 +00:00
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info->branches = 0;
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info->traps = 0;
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info->affectsCPSR = 0;
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2013-11-02 05:29:55 +00:00
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info->condition = ARM_CONDITION_AL;
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2013-11-02 09:52:53 +00:00
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info->sDataCycles = 0;
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info->nDataCycles = 0;
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info->sInstructionCycles = 1;
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info->nInstructionCycles = 0;
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info->iCycles = 0;
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info->cCycles = 0;
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2013-11-01 07:47:12 +00:00
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ThumbDecoder decoder = _thumbDecoderTable[opcode >> 6];
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decoder(opcode, info);
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2013-10-31 06:22:38 +00:00
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}
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