mirror of https://github.com/mgba-emu/mgba.git
Remove notion of special register
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fec4040691
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a22c89fedb
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@ -138,7 +138,6 @@ DEFINE_DATA_FORM_5_DECODER_THUMB(MVN, MVN, ARM_OPERAND_AFFECTED_1)
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DEFINE_THUMB_DECODER(NAME, MNEMONIC, \
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info->op1.reg = (opcode & 0x0007) | H1; \
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info->op2.reg = ((opcode >> 3) & 0x0007) | H2; \
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info->accessesSpecialRegisters = info->op1.reg > 12 || info->op2.reg > 12; \
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info->branches = info->op1.reg == ARM_PC; \
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info->affectsCPSR = CPSR; \
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info->operandFormat = ARM_OPERAND_REGISTER_1 | \
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@ -161,7 +160,6 @@ DEFINE_DECODER_WITH_HIGH_THUMB(MOV3, MOV, ARM_OPERAND_AFFECTED_1, 0)
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info->op1.reg = RD; \
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info->op2.reg = REG; \
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info->op3.immediate = (opcode & 0x00FF) << 2; \
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info->accessesSpecialRegisters = 1; \
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info->operandFormat = ARM_OPERAND_REGISTER_1 | \
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ARM_OPERAND_AFFECTED_1 | \
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ARM_OPERAND_REGISTER_2 | \
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@ -172,7 +170,6 @@ DEFINE_DECODER_WITH_HIGH_THUMB(MOV3, MOV, ARM_OPERAND_AFFECTED_1, 0)
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info->op1.reg = RD; \
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info->memory.baseReg = REG; \
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info->memory.offset.immediate = (opcode & 0x00FF) << 2; \
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info->accessesSpecialRegisters = 1; \
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info->operandFormat = ARM_OPERAND_REGISTER_1 | \
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ARM_OPERAND_AFFECTED_1 | \
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ARM_OPERAND_MEMORY_2; \
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@ -223,7 +220,6 @@ DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(STRH2, STRH, STORE_CYCLES)
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#define DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(NAME, RN, MNEMONIC, SPECIAL_REG, ADDITIONAL_REG) \
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DEFINE_THUMB_DECODER(NAME, MNEMONIC, \
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info->memory.baseReg = RN; \
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info->accessesSpecialRegisters = SPECIAL_REG; \
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info->op1.immediate = (opcode & 0xFF) | ADDITIONAL_REG; \
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info->branches = info->op1.immediate & (1 << ARM_PC); \
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info->operandFormat = ARM_OPERAND_MEMORY_1; \
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@ -263,7 +259,6 @@ DEFINE_CONDITIONAL_BRANCH_THUMB(LE)
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DEFINE_THUMB_DECODER(NAME, MNEMONIC, \
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info->op1.reg = ARM_SP; \
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info->op2.immediate = (opcode & 0x7F) << 2; \
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info->accessesSpecialRegisters = 1; \
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info->operandFormat = ARM_OPERAND_REGISTER_1 | \
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ARM_OPERAND_AFFECTED_1 | \
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ARM_OPERAND_IMMEDIATE_2;)
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@ -288,13 +283,11 @@ DEFINE_THUMB_DECODER(B, B,
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DEFINE_THUMB_DECODER(BL1, BLH,
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int16_t immediate = (opcode & 0x07FF) << 5;
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info->op1.immediate = (((int32_t) immediate) << 7);
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info->operandFormat = ARM_OPERAND_IMMEDIATE_1;
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info->accessesSpecialRegisters = 1;)
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info->operandFormat = ARM_OPERAND_IMMEDIATE_1;)
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DEFINE_THUMB_DECODER(BL2, BL,
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info->op1.immediate = (opcode & 0x07FF) << 1;
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info->operandFormat = ARM_OPERAND_IMMEDIATE_1;
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info->accessesSpecialRegisters = 1;
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info->branches = 1;)
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DEFINE_THUMB_DECODER(BX, BX,
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@ -317,7 +310,6 @@ void ARMDecodeThumb(uint16_t opcode, struct ThumbInstructionInfo* info) {
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info->opcode = opcode;
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info->branches = 0;
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info->traps = 0;
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info->accessesSpecialRegisters = 0;
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info->affectsCPSR = 0;
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info->condition = ARM_CONDITION_AL;
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info->sDataCycles = 0;
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@ -136,7 +136,6 @@ struct ThumbInstructionInfo {
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int operandFormat;
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int branches;
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int traps;
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int accessesSpecialRegisters;
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int affectsCPSR;
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int condition;
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int sDataCycles;
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