mirror of https://github.com/mgba-emu/mgba.git
Merge Thumb mnemonics into ARM mnemonics in preparation for ARM decoder
This commit is contained in:
Jeffrey Pfau
parent
a22c89fedb
commit
64cc5ada86
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@ -9,9 +9,9 @@
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#include <string.h>
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#define DEFINE_THUMB_DECODER(NAME, MNEMONIC, BODY) \
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static void _ThumbDecode ## NAME (uint16_t opcode, struct ThumbInstructionInfo* info) { \
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static void _ThumbDecode ## NAME (uint16_t opcode, struct ARMInstructionInfo* info) { \
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UNUSED(opcode); \
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info->mnemonic = THUMB_MN_ ## MNEMONIC; \
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info->mnemonic = ARM_MN_ ## MNEMONIC; \
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BODY; \
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}
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@ -31,6 +31,7 @@
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info->op1.reg = opcode & 0x0007; \
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info->memory.baseReg = (opcode >> 3) & 0x0007; \
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info->memory.offset.immediate = IMMEDIATE * WIDTH; \
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info->memory.width = (enum ARMMemoryAccessType) WIDTH; \
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info->operandFormat = ARM_OPERAND_REGISTER_1 | \
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ARM_OPERAND_AFFECTED_1 | \
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ARM_OPERAND_MEMORY_2; \
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@ -51,11 +52,11 @@ DEFINE_IMMEDIATE_5_DECODER_THUMB(LSL1, LSL, DATA,)
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DEFINE_IMMEDIATE_5_DECODER_THUMB(LSR1, LSR, DATA,)
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DEFINE_IMMEDIATE_5_DECODER_THUMB(ASR1, ASR, DATA,)
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DEFINE_IMMEDIATE_5_DECODER_THUMB(LDR1, LDR, MEM_LOAD, 4)
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DEFINE_IMMEDIATE_5_DECODER_THUMB(LDRB1, LDRB, MEM_LOAD, 1)
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DEFINE_IMMEDIATE_5_DECODER_THUMB(LDRH1, LDRH, MEM_LOAD, 2)
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DEFINE_IMMEDIATE_5_DECODER_THUMB(LDRB1, LDR, MEM_LOAD, 1)
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DEFINE_IMMEDIATE_5_DECODER_THUMB(LDRH1, LDR, MEM_LOAD, 2)
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DEFINE_IMMEDIATE_5_DECODER_THUMB(STR1, STR, MEM_STORE, 4)
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DEFINE_IMMEDIATE_5_DECODER_THUMB(STRB1, STRB, MEM_STORE, 1)
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DEFINE_IMMEDIATE_5_DECODER_THUMB(STRH1, STRH, MEM_STORE, 2)
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DEFINE_IMMEDIATE_5_DECODER_THUMB(STRB1, STR, MEM_STORE, 1)
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DEFINE_IMMEDIATE_5_DECODER_THUMB(STRH1, STR, MEM_STORE, 2)
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#define DEFINE_DATA_FORM_1_DECODER_EX_THUMB(NAME, RM, MNEMONIC) \
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DEFINE_THUMB_DECODER(NAME, MNEMONIC, \
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@ -170,6 +171,7 @@ DEFINE_DECODER_WITH_HIGH_THUMB(MOV3, MOV, ARM_OPERAND_AFFECTED_1, 0)
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info->op1.reg = RD; \
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info->memory.baseReg = REG; \
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info->memory.offset.immediate = (opcode & 0x00FF) << 2; \
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info->memory.width = ARM_ACCESS_WORD; \
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info->operandFormat = ARM_OPERAND_REGISTER_1 | \
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ARM_OPERAND_AFFECTED_1 | \
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ARM_OPERAND_MEMORY_2; \
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@ -193,11 +195,12 @@ DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(STR3, STR, MEM_STORE, ARM_SP)
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DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(ADD5, ADD, DATA, ARM_PC)
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DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(ADD6, ADD, DATA, ARM_SP)
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#define DEFINE_LOAD_STORE_WITH_REGISTER_EX_THUMB(NAME, RM, MNEMONIC, CYCLES) \
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#define DEFINE_LOAD_STORE_WITH_REGISTER_EX_THUMB(NAME, RM, MNEMONIC, CYCLES, TYPE) \
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DEFINE_THUMB_DECODER(NAME, MNEMONIC, \
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info->memory.offset.reg = RM; \
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info->op1.reg = opcode & 0x0007; \
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info->memory.baseReg = (opcode >> 3) & 0x0007; \
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info->memory.width = TYPE; \
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info->operandFormat = ARM_OPERAND_REGISTER_1 | \
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ARM_OPERAND_AFFECTED_1 | \
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ARM_OPERAND_MEMORY_2; \
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@ -205,32 +208,33 @@ DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(ADD6, ADD, DATA, ARM_SP)
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ARM_MEMORY_REGISTER_OFFSET; \
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CYCLES;)
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#define DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(NAME, MNEMONIC, CYCLES) \
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COUNT_3(DEFINE_LOAD_STORE_WITH_REGISTER_EX_THUMB, NAME ## _R, MNEMONIC, CYCLES)
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#define DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(NAME, MNEMONIC, CYCLES, TYPE) \
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COUNT_3(DEFINE_LOAD_STORE_WITH_REGISTER_EX_THUMB, NAME ## _R, MNEMONIC, CYCLES, TYPE)
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DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDR2, LDR, LOAD_CYCLES)
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DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDRB2, LDRB, LOAD_CYCLES)
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DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDRH2, LDRH, LOAD_CYCLES)
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DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDRSB, LDRSB, LOAD_CYCLES)
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DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDRSH, LDRSH, LOAD_CYCLES)
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DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(STR2, STR, STORE_CYCLES)
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DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(STRB2, STRB, STORE_CYCLES)
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DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(STRH2, STRH, STORE_CYCLES)
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DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDR2, LDR, LOAD_CYCLES, ARM_ACCESS_WORD)
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DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDRB2, LDR, LOAD_CYCLES, ARM_ACCESS_BYTE)
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DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDRH2, LDR, LOAD_CYCLES, ARM_ACCESS_HALFWORD)
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DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDRSB, LDR, LOAD_CYCLES, ARM_ACCESS_SIGNED_BYTE)
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DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDRSH, LDR, LOAD_CYCLES, ARM_ACCESS_SIGNED_HALFWORD)
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DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(STR2, STR, STORE_CYCLES, ARM_ACCESS_WORD)
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DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(STRB2, STR, STORE_CYCLES, ARM_ACCESS_BYTE)
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DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(STRH2, STR, STORE_CYCLES, ARM_ACCESS_HALFWORD)
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#define DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(NAME, RN, MNEMONIC, SPECIAL_REG, ADDITIONAL_REG) \
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#define DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(NAME, RN, MNEMONIC, DIRECTION, ADDITIONAL_REG) \
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DEFINE_THUMB_DECODER(NAME, MNEMONIC, \
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info->memory.baseReg = RN; \
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info->op1.immediate = (opcode & 0xFF) | ADDITIONAL_REG; \
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info->branches = info->op1.immediate & (1 << ARM_PC); \
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info->operandFormat = ARM_OPERAND_MEMORY_1; \
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info->memory.direction = DIRECTION; \
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info->memory.format = ARM_MEMORY_REGISTER_BASE | \
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ARM_MEMORY_POST_INCREMENT;)
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#define DEFINE_LOAD_STORE_MULTIPLE_THUMB(NAME) \
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COUNT_3(DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB, NAME ## _R, NAME, 0, 0)
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COUNT_3(DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB, NAME ## IA_R, NAME, ARM_INCREMENT_AFTER, 0)
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DEFINE_LOAD_STORE_MULTIPLE_THUMB(LDMIA)
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DEFINE_LOAD_STORE_MULTIPLE_THUMB(STMIA)
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DEFINE_LOAD_STORE_MULTIPLE_THUMB(LDM)
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DEFINE_LOAD_STORE_MULTIPLE_THUMB(STM)
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#define DEFINE_CONDITIONAL_BRANCH_THUMB(COND) \
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DEFINE_THUMB_DECODER(B ## COND, B, \
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@ -266,10 +270,10 @@ DEFINE_CONDITIONAL_BRANCH_THUMB(LE)
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DEFINE_SP_MODIFY_THUMB(ADD7, ADD)
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DEFINE_SP_MODIFY_THUMB(SUB4, SUB)
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DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(POP, ARM_SP, POP, 1, 0)
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DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(POPR, ARM_SP, POP, 1, 1 << ARM_PC)
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DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(PUSH, ARM_SP, PUSH, 1, 0)
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DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(PUSHR, ARM_SP, PUSH, 1, 1 << ARM_LR)
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DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(POP, ARM_SP, LDM, ARM_INCREMENT_AFTER, 0)
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DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(POPR, ARM_SP, LDM, ARM_INCREMENT_AFTER, 1 << ARM_PC)
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DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(PUSH, ARM_SP, STM, ARM_DECREMENT_BEFORE, 0)
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DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(PUSHR, ARM_SP, STM, ARM_DECREMENT_BEFORE, 1 << ARM_LR)
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DEFINE_THUMB_DECODER(ILL, ILL, info->traps = 1;)
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DEFINE_THUMB_DECODER(BKPT, BKPT, info->traps = 1;)
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@ -300,13 +304,13 @@ DEFINE_THUMB_DECODER(SWI, SWI,
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info->operandFormat = ARM_OPERAND_IMMEDIATE_1;
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info->traps = 1;)
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typedef void (*ThumbDecoder)(uint16_t opcode, struct ThumbInstructionInfo* info);
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typedef void (*ThumbDecoder)(uint16_t opcode, struct ARMInstructionInfo* info);
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static const ThumbDecoder _thumbDecoderTable[0x400] = {
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DECLARE_THUMB_EMITTER_BLOCK(_ThumbDecode)
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};
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void ARMDecodeThumb(uint16_t opcode, struct ThumbInstructionInfo* info) {
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void ARMDecodeThumb(uint16_t opcode, struct ARMInstructionInfo* info) {
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info->opcode = opcode;
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info->branches = 0;
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info->traps = 0;
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@ -322,7 +326,7 @@ void ARMDecodeThumb(uint16_t opcode, struct ThumbInstructionInfo* info) {
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decoder(opcode, info);
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}
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const char* thumbMnemonicStrings[] = {
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const char* armMnemonicStrings[] = {
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"ill",
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"adc",
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"add",
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@ -337,12 +341,8 @@ const char* thumbMnemonicStrings[] = {
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"cmn",
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"cmp",
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"eor",
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"ldmia",
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"ldm",
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"ldr",
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"ldrb",
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"ldrh",
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"ldrsb",
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"ldrsh",
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"lsl",
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"lsr",
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"mov",
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@ -350,46 +350,75 @@ const char* thumbMnemonicStrings[] = {
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"mvn",
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"neg",
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"orr",
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"pop",
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"push",
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"ror",
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"sbc",
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"stmia",
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"stm",
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"str",
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"strb",
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"strh",
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"sub",
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"swi",
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"tst"
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};
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const char* armDirectionStrings[] = {
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"da",
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"ia",
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"db",
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"da"
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};
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const char* armAccessTypeStrings[] = {
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"",
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"b",
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"h",
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"",
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"",
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"",
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"",
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"",
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"",
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"sb",
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"sh",
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""
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""
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};
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int ARMDisassembleThumb(uint16_t opcode, uint32_t pc, char* buffer, int blen) {
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struct ThumbInstructionInfo info;
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struct ARMInstructionInfo info;
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ARMDecodeThumb(opcode, &info);
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const char* mnemonic = thumbMnemonicStrings[info.mnemonic];
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const char* mnemonic = armMnemonicStrings[info.mnemonic];
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int written;
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int total = 0;
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const char* cond = "";
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if (info.condition != ARM_CONDITION_AL && info.condition < ARM_CONDITION_NV) {
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cond = _armConditions[info.condition];
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}
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written = snprintf(buffer, blen, "%s%s ", mnemonic, cond);
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const char* flags = "";
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switch (info.mnemonic) {
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case ARM_MN_LDM:
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case ARM_MN_STM:
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flags = armDirectionStrings[info.memory.direction];
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break;
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case ARM_MN_LDR:
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case ARM_MN_STR:
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flags = armAccessTypeStrings[info.memory.direction];
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break;
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default:
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break;
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}
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written = snprintf(buffer, blen - 1, "%s%s%s ", mnemonic, flags, cond);
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ADVANCE(written);
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switch (info.mnemonic) {
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case THUMB_MN_LDMIA:
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case THUMB_MN_STMIA:
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case ARM_MN_LDM:
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case ARM_MN_STM:
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written = _decodeRegister(info.memory.baseReg, buffer, blen);
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ADVANCE(written);
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strncpy(buffer, "!, ", blen);
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ADVANCE(3);
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// Fall through
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case THUMB_MN_POP:
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case THUMB_MN_PUSH:
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written = _decodeRegisterList(info.op1.immediate, buffer, blen);
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ADVANCE(written);
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break;
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case THUMB_MN_B:
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case ARM_MN_B:
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written = _decodePCRelative(info.op1.immediate, pc, buffer, blen);
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ADVANCE(written);
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break;
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@ -77,58 +77,69 @@ union ARMOperand {
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int32_t immediate;
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};
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enum ARMMultipleDirection {
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ARM_DECREMENT_AFTER = 0,
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ARM_INCREMENT_AFTER = 1,
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ARM_DECREMENT_BEFORE = 2,
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ARM_INCREMENT_BEFORE = 3,
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};
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enum ARMMemoryAccessType {
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ARM_ACCESS_WORD = 4,
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ARM_ACCESS_HALFWORD = 2,
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ARM_ACCESS_SIGNED_HALFWORD = 10,
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ARM_ACCESS_BYTE = 1,
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ARM_ACCESS_SIGNED_BYTE = 9
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};
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struct ARMMemoryAccess {
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uint8_t baseReg;
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uint16_t format;
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union ARMOperand offset;
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union {
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enum ARMMultipleDirection direction;
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enum ARMMemoryAccessType width;
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};
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};
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enum ThumbMnemonic {
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THUMB_MN_ILL = 0,
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THUMB_MN_ADC,
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THUMB_MN_ADD,
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THUMB_MN_AND,
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THUMB_MN_ASR,
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THUMB_MN_B,
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THUMB_MN_BIC,
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THUMB_MN_BKPT,
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THUMB_MN_BL,
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THUMB_MN_BLH,
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THUMB_MN_BX,
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THUMB_MN_CMN,
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THUMB_MN_CMP,
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THUMB_MN_EOR,
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THUMB_MN_LDMIA,
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THUMB_MN_LDR,
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THUMB_MN_LDRB,
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THUMB_MN_LDRH,
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THUMB_MN_LDRSB,
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THUMB_MN_LDRSH,
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THUMB_MN_LSL,
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THUMB_MN_LSR,
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THUMB_MN_MOV,
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THUMB_MN_MUL,
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THUMB_MN_MVN,
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THUMB_MN_NEG,
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THUMB_MN_ORR,
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THUMB_MN_POP,
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THUMB_MN_PUSH,
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THUMB_MN_ROR,
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THUMB_MN_SBC,
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THUMB_MN_STMIA,
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THUMB_MN_STR,
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THUMB_MN_STRB,
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THUMB_MN_STRH,
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THUMB_MN_SUB,
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THUMB_MN_SWI,
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THUMB_MN_TST,
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enum ARMMnemonic {
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ARM_MN_ILL = 0,
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ARM_MN_ADC,
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ARM_MN_ADD,
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ARM_MN_AND,
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ARM_MN_ASR,
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ARM_MN_B,
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ARM_MN_BIC,
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ARM_MN_BKPT,
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ARM_MN_BL,
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ARM_MN_BLH,
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ARM_MN_BX,
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ARM_MN_CMN,
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ARM_MN_CMP,
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ARM_MN_EOR,
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ARM_MN_LDM,
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ARM_MN_LDR,
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ARM_MN_LSL,
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ARM_MN_LSR,
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ARM_MN_MOV,
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ARM_MN_MUL,
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ARM_MN_MVN,
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ARM_MN_NEG,
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ARM_MN_ORR,
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ARM_MN_ROR,
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ARM_MN_SBC,
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ARM_MN_STM,
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ARM_MN_STR,
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ARM_MN_SUB,
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ARM_MN_SWI,
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ARM_MN_TST,
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THUMB_MN_MAX
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ARM_MN_MAX
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};
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struct ThumbInstructionInfo {
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uint16_t opcode;
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enum ThumbMnemonic mnemonic;
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struct ARMInstructionInfo {
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uint32_t opcode;
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enum ARMMnemonic mnemonic;
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union ARMOperand op1;
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union ARMOperand op2;
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union ARMOperand op3;
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@ -146,7 +157,7 @@ struct ThumbInstructionInfo {
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int cCycles;
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};
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void ARMDecodeThumb(uint16_t opcode, struct ThumbInstructionInfo* info);
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void ARMDecodeThumb(uint16_t opcode, struct ARMInstructionInfo* info);
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int ARMDisassembleThumb(uint16_t opcode, uint32_t pc, char* buffer, int blen);
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#endif
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