mirror of https://github.com/mgba-emu/mgba.git
Descriptions of all opcodes
This commit is contained in:
Jeffrey Pfau
parent
5d19919df2
commit
65c1d67dfd
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@ -1,6 +1,303 @@
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#include "decompiler.h"
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#include "arm.h"
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#include "emitter-thumb.h"
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#include "isa-inlines.h"
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#define DEFINE_THUMB_DECODER(NAME, MNEMONIC, BODY) \
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static void _ThumbDecode ## NAME (uint16_t opcode, struct ThumbInstructionInfo* info) { \
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UNUSED(opcode); \
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info->mnemonic = THUMB_MN_ ## MNEMONIC; \
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BODY; \
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}
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#define DEFINE_IMMEDIATE_5_DECODER_DATA_THUMB(NAME, IMMEDIATE, MNEMONIC) \
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DEFINE_THUMB_DECODER(NAME, MNEMONIC, \
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info->op3.immediate = IMMEDIATE; \
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info->op1.reg = opcode & 0x0007; \
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info->op2.reg = (opcode >> 3) & 0x0007; \
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info->affectsCPSR = 1; \
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info->operandFormat = ARM_OPERAND_REGISTER_1 | \
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ARM_OPERAND_AFFECTED_1 | \
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ARM_OPERAND_REGISTER_2 | \
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ARM_OPERAND_IMMEDIATE_3;)
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#define DEFINE_IMMEDIATE_5_DECODER_MEM_THUMB(NAME, IMMEDIATE, MNEMONIC) \
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DEFINE_THUMB_DECODER(NAME, MNEMONIC, \
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info->op1.reg = opcode & 0x0007; \
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info->memory.baseReg = (opcode >> 3) & 0x0007; \
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info->memory.offset.shifterReg = IMMEDIATE << 2; \
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info->operandFormat = ARM_OPERAND_REGISTER_1 | \
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ARM_OPERAND_AFFECTED_1 | \
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ARM_OPERAND_MEMORY_2; \
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info->memory.format = ARM_MEMORY_REGISTER_BASE | \
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ARM_MEMORY_IMMEDIATE_OFFSET;)
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#define DEFINE_IMMEDIATE_5_DECODER_THUMB(NAME, MNEMONIC, TYPE) \
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COUNT_5(DEFINE_IMMEDIATE_5_DECODER_ ## TYPE ## _THUMB, NAME ## _, MNEMONIC)
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DEFINE_IMMEDIATE_5_DECODER_THUMB(LSL1, LSL, DATA)
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DEFINE_IMMEDIATE_5_DECODER_THUMB(LSR1, LSR, DATA)
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DEFINE_IMMEDIATE_5_DECODER_THUMB(ASR1, ASR, DATA)
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DEFINE_IMMEDIATE_5_DECODER_THUMB(LDR1, LDR, MEM)
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DEFINE_IMMEDIATE_5_DECODER_THUMB(LDRB1, LDRB, MEM)
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DEFINE_IMMEDIATE_5_DECODER_THUMB(LDRH1, LDRH, MEM)
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DEFINE_IMMEDIATE_5_DECODER_THUMB(STR1, STR, MEM)
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DEFINE_IMMEDIATE_5_DECODER_THUMB(STRB1, STRB, MEM)
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DEFINE_IMMEDIATE_5_DECODER_THUMB(STRH1, STRH, MEM)
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#define DEFINE_DATA_FORM_1_DECODER_EX_THUMB(NAME, RM, MNEMONIC) \
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DEFINE_THUMB_DECODER(NAME, MNEMONIC, \
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info->op1.reg = opcode & 0x0007; \
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info->op2.reg = (opcode >> 3) & 0x0007; \
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info->op3.reg = RM; \
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info->affectsCPSR = 1; \
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info->operandFormat = ARM_OPERAND_REGISTER_1 | \
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ARM_OPERAND_AFFECTED_1 | \
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ARM_OPERAND_REGISTER_2 | \
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ARM_OPERAND_REGISTER_3;)
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#define DEFINE_DATA_FORM_1_DECODER_THUMB(NAME) \
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COUNT_3(DEFINE_DATA_FORM_1_DECODER_EX_THUMB, NAME ## 3_R, NAME)
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DEFINE_DATA_FORM_1_DECODER_THUMB(ADD)
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DEFINE_DATA_FORM_1_DECODER_THUMB(SUB)
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#define DEFINE_DATA_FORM_2_DECODER_EX_THUMB(NAME, IMMEDIATE, MNEMONIC) \
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DEFINE_THUMB_DECODER(NAME, MNEMONIC, \
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info->op1.reg = opcode & 0x0007; \
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info->op2.reg = (opcode >> 3) & 0x0007; \
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info->op3.immediate = IMMEDIATE; \
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info->affectsCPSR = 1; \
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info->operandFormat = ARM_OPERAND_REGISTER_1 | \
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ARM_OPERAND_AFFECTED_1 | \
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ARM_OPERAND_REGISTER_2 | \
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ARM_OPERAND_IMMEDIATE_3;)
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#define DEFINE_DATA_FORM_2_DECODER_THUMB(NAME) \
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COUNT_3(DEFINE_DATA_FORM_2_DECODER_EX_THUMB, NAME ## 1_, NAME)
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DEFINE_DATA_FORM_2_DECODER_THUMB(ADD)
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DEFINE_DATA_FORM_2_DECODER_THUMB(SUB)
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#define DEFINE_DATA_FORM_3_DECODER_EX_THUMB(NAME, RD, MNEMONIC, AFFECTED) \
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DEFINE_THUMB_DECODER(NAME, MNEMONIC, \
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info->op1.reg = RD; \
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info->op2.immediate = opcode & 0x00FF; \
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info->affectsCPSR = 1; \
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info->operandFormat = ARM_OPERAND_REGISTER_1 | \
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AFFECTED | \
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ARM_OPERAND_IMMEDIATE_2;)
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#define DEFINE_DATA_FORM_3_DECODER_THUMB(NAME, MNEMONIC, AFFECTED) \
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COUNT_3(DEFINE_DATA_FORM_3_DECODER_EX_THUMB, NAME ## _R, MNEMONIC, AFFECTED)
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DEFINE_DATA_FORM_3_DECODER_THUMB(ADD2, ADD, ARM_OPERAND_AFFECTED_1)
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DEFINE_DATA_FORM_3_DECODER_THUMB(CMP1, CMP, ARM_OPERAND_NONE)
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DEFINE_DATA_FORM_3_DECODER_THUMB(MOV1, MOV, ARM_OPERAND_AFFECTED_1)
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DEFINE_DATA_FORM_3_DECODER_THUMB(SUB2, SUB, ARM_OPERAND_AFFECTED_1)
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#define DEFINE_DATA_FORM_5_DECODER_THUMB(NAME, MNEMONIC, AFFECTED) \
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DEFINE_THUMB_DECODER(NAME, MNEMONIC, \
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info->op1.reg = opcode & 0x0007; \
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info->op2.reg = (opcode >> 3) & 0x0007; \
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info->affectsCPSR = 1; \
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info->operandFormat = ARM_OPERAND_REGISTER_1 | \
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AFFECTED | \
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ARM_OPERAND_REGISTER_2;)
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DEFINE_DATA_FORM_5_DECODER_THUMB(AND, AND, ARM_OPERAND_AFFECTED_1)
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DEFINE_DATA_FORM_5_DECODER_THUMB(EOR, EOR, ARM_OPERAND_AFFECTED_1)
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DEFINE_DATA_FORM_5_DECODER_THUMB(LSL2, LSL, ARM_OPERAND_AFFECTED_1)
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DEFINE_DATA_FORM_5_DECODER_THUMB(LSR2, LSR, ARM_OPERAND_AFFECTED_1)
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DEFINE_DATA_FORM_5_DECODER_THUMB(ASR2, ASR, ARM_OPERAND_AFFECTED_1)
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DEFINE_DATA_FORM_5_DECODER_THUMB(ADC, ADC, ARM_OPERAND_AFFECTED_1)
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DEFINE_DATA_FORM_5_DECODER_THUMB(SBC, SBC, ARM_OPERAND_AFFECTED_1)
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DEFINE_DATA_FORM_5_DECODER_THUMB(ROR, ROR, ARM_OPERAND_AFFECTED_1)
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DEFINE_DATA_FORM_5_DECODER_THUMB(TST, TST, ARM_OPERAND_AFFECTED_1)
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DEFINE_DATA_FORM_5_DECODER_THUMB(NEG, NEG, ARM_OPERAND_AFFECTED_1)
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DEFINE_DATA_FORM_5_DECODER_THUMB(CMP2, CMP, ARM_OPERAND_NONE)
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DEFINE_DATA_FORM_5_DECODER_THUMB(CMN, CMN, ARM_OPERAND_NONE)
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DEFINE_DATA_FORM_5_DECODER_THUMB(ORR, ORR, ARM_OPERAND_AFFECTED_1)
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DEFINE_DATA_FORM_5_DECODER_THUMB(MUL, MUL, ARM_OPERAND_AFFECTED_1)
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DEFINE_DATA_FORM_5_DECODER_THUMB(BIC, BIC, ARM_OPERAND_AFFECTED_1)
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DEFINE_DATA_FORM_5_DECODER_THUMB(MVN, MVN, ARM_OPERAND_AFFECTED_1)
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#define DEFINE_DECODER_WITH_HIGH_EX_THUMB(NAME, H1, H2, MNEMONIC, AFFECTED, CPSR) \
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DEFINE_THUMB_DECODER(NAME, MNEMONIC, \
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info->op1.reg = (opcode & 0x0007) | H1; \
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info->op2.reg = ((opcode >> 3) & 0x0007) | H2; \
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info->accessesSpecialRegisters = info->op1.reg > 12 || info->op2.reg > 12; \
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info->affectsCPSR = CPSR; \
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info->operandFormat = ARM_OPERAND_REGISTER_1 | \
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AFFECTED | \
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ARM_OPERAND_REGISTER_2;)
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#define DEFINE_DECODER_WITH_HIGH_THUMB(NAME, MNEMONIC, AFFECTED, CPSR) \
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DEFINE_DECODER_WITH_HIGH_EX_THUMB(NAME ## 00, 0, 0, MNEMONIC, AFFECTED, CPSR) \
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DEFINE_DECODER_WITH_HIGH_EX_THUMB(NAME ## 01, 0, 8, MNEMONIC, AFFECTED, CPSR) \
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DEFINE_DECODER_WITH_HIGH_EX_THUMB(NAME ## 10, 8, 0, MNEMONIC, AFFECTED, CPSR) \
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DEFINE_DECODER_WITH_HIGH_EX_THUMB(NAME ## 11, 8, 8, MNEMONIC, AFFECTED, CPSR)
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DEFINE_DECODER_WITH_HIGH_THUMB(ADD4, ADD, ARM_OPERAND_AFFECTED_1, 0)
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DEFINE_DECODER_WITH_HIGH_THUMB(CMP3, CMP, ARM_OPERAND_NONE, 1)
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DEFINE_DECODER_WITH_HIGH_THUMB(MOV3, MOV, ARM_OPERAND_AFFECTED_1, 0)
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#define DEFINE_IMMEDIATE_WITH_REGISTER_DATA_THUMB(NAME, RD, MNEMONIC, REG) \
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DEFINE_THUMB_DECODER(NAME, MNEMONIC, \
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info->op1.reg = RD; \
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info->op2.reg = REG; \
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info->op3.immediate = (opcode & 0x00FF) << 2; \
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info->accessesSpecialRegisters = 1; \
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info->operandFormat = ARM_OPERAND_REGISTER_1 | \
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ARM_OPERAND_AFFECTED_1 | \
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ARM_OPERAND_REGISTER_2 | \
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ARM_OPERAND_IMMEDIATE_3;)
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#define DEFINE_IMMEDIATE_WITH_REGISTER_MEM_THUMB(NAME, RD, MNEMONIC, REG) \
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DEFINE_THUMB_DECODER(NAME, MNEMONIC, \
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info->op1.reg = RD; \
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info->memory.baseReg = REG; \
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info->memory.offset.immediate = (opcode & 0x00FF) << 2; \
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info->accessesSpecialRegisters = 1; \
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info->operandFormat = ARM_OPERAND_REGISTER_1 | \
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ARM_OPERAND_AFFECTED_1 | \
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ARM_OPERAND_MEMORY_2; \
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info->memory.format = ARM_MEMORY_REGISTER_BASE | \
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ARM_MEMORY_IMMEDIATE_OFFSET;)
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#define DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(NAME, MNEMONIC, TYPE, REG) \
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COUNT_3(DEFINE_IMMEDIATE_WITH_REGISTER_ ## TYPE ## _THUMB, NAME ## _R, MNEMONIC, REG)
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DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(LDR3, LDR, MEM, ARM_PC)
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DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(LDR4, LDR, MEM, ARM_SP)
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DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(STR3, STR, MEM, ARM_SP)
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DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(ADD5, ADD, DATA, ARM_PC)
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DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(ADD6, ADD, DATA, ARM_SP)
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#define DEFINE_LOAD_STORE_WITH_REGISTER_EX_THUMB(NAME, RM, MNEMONIC) \
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DEFINE_THUMB_DECODER(NAME, MNEMONIC, \
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info->memory.offset.reg = RM; \
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info->op1.reg = opcode & 0x0007; \
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info->memory.baseReg = (opcode >> 3) & 0x0007; \
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info->operandFormat = ARM_OPERAND_REGISTER_1 | \
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ARM_OPERAND_AFFECTED_1 | \
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ARM_OPERAND_MEMORY_2; \
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info->memory.format = ARM_MEMORY_REGISTER_BASE | \
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ARM_MEMORY_REGISTER_OFFSET;)
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#define DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(NAME, MNEMONIC) \
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COUNT_3(DEFINE_LOAD_STORE_WITH_REGISTER_EX_THUMB, NAME ## _R, MNEMONIC)
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DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDR2, LDR)
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DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDRB2, LDRB)
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DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDRH2, LDRH)
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DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDRSB, LDRSB)
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DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDRSH, LDRSH)
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DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(STR2, STR)
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DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(STRB2, STRB)
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DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(STRH2, STRH)
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#define DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(NAME, RN, MNEMONIC, SPECIAL_REG) \
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DEFINE_THUMB_DECODER(NAME, MNEMONIC, \
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info->memory.baseReg = RN; \
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info->accessesSpecialRegisters = SPECIAL_REG; \
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info->op1.immediate = opcode & 0xFF; \
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info->operandFormat = ARM_OPERAND_IMMEDIATE_1 | \
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ARM_OPERAND_AFFECTED_1; \
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info->memory.format = ARM_MEMORY_REGISTER_BASE | \
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ARM_MEMORY_POST_INCREMENT;)
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#define DEFINE_LOAD_STORE_MULTIPLE_THUMB(NAME) \
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COUNT_3(DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB, NAME ## _R, NAME, 0)
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DEFINE_LOAD_STORE_MULTIPLE_THUMB(LDMIA)
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DEFINE_LOAD_STORE_MULTIPLE_THUMB(STMIA)
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#define DEFINE_CONDITIONAL_BRANCH_THUMB(COND) \
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DEFINE_THUMB_DECODER(B ## COND, B, \
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int8_t immediate = opcode; \
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info->op1.immediate += immediate << 1; \
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info->branches = 1; \
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info->operandFormat = ARM_OPERAND_IMMEDIATE_1;)
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DEFINE_CONDITIONAL_BRANCH_THUMB(EQ)
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DEFINE_CONDITIONAL_BRANCH_THUMB(NE)
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DEFINE_CONDITIONAL_BRANCH_THUMB(CS)
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DEFINE_CONDITIONAL_BRANCH_THUMB(CC)
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DEFINE_CONDITIONAL_BRANCH_THUMB(MI)
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DEFINE_CONDITIONAL_BRANCH_THUMB(PL)
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DEFINE_CONDITIONAL_BRANCH_THUMB(VS)
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DEFINE_CONDITIONAL_BRANCH_THUMB(VC)
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DEFINE_CONDITIONAL_BRANCH_THUMB(LS)
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DEFINE_CONDITIONAL_BRANCH_THUMB(HI)
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DEFINE_CONDITIONAL_BRANCH_THUMB(GE)
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DEFINE_CONDITIONAL_BRANCH_THUMB(LT)
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DEFINE_CONDITIONAL_BRANCH_THUMB(GT)
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DEFINE_CONDITIONAL_BRANCH_THUMB(LE)
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#define DEFINE_SP_MODIFY_THUMB(NAME, MNEMONIC) \
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DEFINE_THUMB_DECODER(NAME, MNEMONIC, \
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info->op1.reg = ARM_SP; \
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info->op2.immediate = (opcode & 0x7F) << 2; \
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info->accessesSpecialRegisters = 1; \
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info->operandFormat = ARM_OPERAND_REGISTER_1 | \
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ARM_OPERAND_AFFECTED_1 | \
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ARM_OPERAND_IMMEDIATE_2;)
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DEFINE_SP_MODIFY_THUMB(ADD7, ADD)
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DEFINE_SP_MODIFY_THUMB(SUB4, SUB)
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DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(POP, ARM_SP, POP, 1)
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DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(POPR, ARM_SP, POP, 1)
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DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(PUSH, ARM_SP, PUSH, 1)
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DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(PUSHR, ARM_SP, PUSH, 1)
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DEFINE_THUMB_DECODER(ILL, ILL, info->traps = 1;)
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DEFINE_THUMB_DECODER(BKPT, BKPT, info->traps = 1;)
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DEFINE_THUMB_DECODER(B, B,
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int16_t immediate = (opcode & 0x07FF) << 5;
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info->op1.immediate = (((int32_t) immediate) >> 4);
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info->operandFormat = ARM_OPERAND_IMMEDIATE_1;
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info->branches = 1;)
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DEFINE_THUMB_DECODER(BL1, BLH,
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int16_t immediate = (opcode & 0x07FF) << 5;
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info->op1.immediate = (((int32_t) immediate) << 7);
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info->operandFormat = ARM_OPERAND_IMMEDIATE_1;
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info->accessesSpecialRegisters = 1;)
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DEFINE_THUMB_DECODER(BL2, BL,
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info->op1.immediate = (opcode & 0x07FF) << 1;
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info->operandFormat = ARM_OPERAND_IMMEDIATE_1;
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info->accessesSpecialRegisters = 1;
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info->branches = 1;)
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DEFINE_THUMB_DECODER(BX, BX,
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info->op1.reg = (opcode >> 3) & 0xF;
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info->operandFormat = ARM_OPERAND_REGISTER_1;
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info->branches = 1;)
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DEFINE_THUMB_DECODER(SWI, SWI,
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info->op1.immediate = opcode & 0xFF;
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info->operandFormat = ARM_OPERAND_IMMEDIATE_1;
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info->traps = 1;)
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typedef void (*ThumbDecoder)(uint16_t opcode, struct ThumbInstructionInfo* info);
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static const ThumbDecoder _thumbDecoderTable[0x400] = {
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DECLARE_THUMB_EMITTER_BLOCK(_ThumbDecode)
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};
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void ARMDecodeThumb(uint16_t opcode, struct ThumbInstructionInfo* info) {
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// TODO
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info->opcode = opcode;
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info->branches = 0;
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info->traps = 0;
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info->accessesSpecialRegisters = 0;
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info->affectsCPSR = 0;
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ThumbDecoder decoder = _thumbDecoderTable[opcode >> 6];
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decoder(opcode, info);
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}
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@ -3,26 +3,62 @@
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#include <stdint.h>
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union ARMOperand {
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uint8_t reg;
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int32_t immediate;
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};
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struct ARMMemoryAccess {
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uint8_t baseRegister;
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union ARMOperand offset;
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};
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// Bit 0: a register is involved with this operand
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// Bit 1: an immediate is invovled with this operand
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// Bit 2: a memory access is invovled with this operand
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// Bit 3: the destination of this operand is affected by this opcode
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// Bit 4: this operand is shifted by a register
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// Bit 5: this operand is shifted by an immediate
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// Bit 6: this operand is added or subtracted to the base register
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enum ARMOperandFormat {
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ARM_OPERAND_NONE = 0x00000000,
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ARM_OPERAND_REGISTER_1 = 0x00000001,
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ARM_OPERAND_IMMEDIATE_1 = 0x00000002,
|
||||
ARM_OPERAND_MEMORY_REGISTER_1 = 0x00000005,
|
||||
ARM_OPERAND_MEMORY_IMMEDIATE_1 = 0x00000006,
|
||||
ARM_OPERAND_MEMORY_OFFSET_1 = 0x00000007,
|
||||
ARM_OPERAND_AFFECTED_1 = 0x00000080,
|
||||
ARM_OPERAND_MEMORY_POST_INCR_1 = 0x00000097,
|
||||
ARM_OPERAND_MEMORY_PRE_INCR_1 = 0x000000A7,
|
||||
ARM_OPERAND_MEMORY_1 = 0x00000004,
|
||||
ARM_OPERAND_AFFECTED_1 = 0x00000008,
|
||||
ARM_OPERAND_SHIFT_REGISTER_1 = 0x00000010,
|
||||
ARM_OPERAND_SHIFT_IMMEDIATE_1 = 0x00000020,
|
||||
|
||||
ARM_OPERAND_REGISTER_2 = 0x00000100,
|
||||
ARM_OPERAND_IMMEDIATE_2 = 0x00000200,
|
||||
ARM_OPERAND_MEMORY_2 = 0x00000400,
|
||||
ARM_OPERAND_AFFECTED_2 = 0x00000800,
|
||||
ARM_OPERAND_SHIFT_REGISTER_2 = 0x00001000,
|
||||
ARM_OPERAND_SHIFT_IMMEDIATE_2 = 0x00002000,
|
||||
|
||||
ARM_OPERAND_REGISTER_3 = 0x00010000,
|
||||
ARM_OPERAND_IMMEDIATE_3 = 0x00020000,
|
||||
ARM_OPERAND_MEMORY_3 = 0x00040000,
|
||||
ARM_OPERAND_AFFECTED_3 = 0x00080000,
|
||||
ARM_OPERAND_SHIFT_REGISTER_3 = 0x00100000,
|
||||
ARM_OPERAND_SHIFT_IMMEDIATE_3 = 0x00200000
|
||||
};
|
||||
|
||||
enum ARMMemoryFormat {
|
||||
ARM_MEMORY_REGISTER_BASE = 0x0001,
|
||||
ARM_MEMORY_IMMEDIATE_OFFSET = 0x0002,
|
||||
ARM_MEMORY_REGISTER_OFFSET = 0x0004,
|
||||
ARM_MEMORY_SHIFTED_OFFSET = 0x0008,
|
||||
ARM_MEMORY_PRE_INCREMENT = 0x0010,
|
||||
ARM_MEMORY_POST_INCREMENT = 0x0020
|
||||
};
|
||||
|
||||
union ARMOperand {
|
||||
struct {
|
||||
uint8_t reg;
|
||||
uint8_t shifterOp;
|
||||
union {
|
||||
uint8_t shifterReg;
|
||||
uint8_t shifterImm;
|
||||
};
|
||||
};
|
||||
int32_t immediate;
|
||||
};
|
||||
|
||||
struct ARMMemoryAccess {
|
||||
uint8_t baseReg;
|
||||
uint16_t format;
|
||||
union ARMOperand offset;
|
||||
};
|
||||
|
||||
enum ThumbMnemonic {
|
||||
|
|
@ -33,6 +69,7 @@ enum ThumbMnemonic {
|
|||
THUMB_MN_ASR,
|
||||
THUMB_MN_B,
|
||||
THUMB_MN_BIC,
|
||||
THUMB_MN_BKPT,
|
||||
THUMB_MN_BL,
|
||||
THUMB_MN_BLH,
|
||||
THUMB_MN_BX,
|
||||
|
|
@ -72,11 +109,11 @@ struct ThumbInstructionInfo {
|
|||
union ARMOperand op2;
|
||||
union ARMOperand op3;
|
||||
struct ARMMemoryAccess memory;
|
||||
int immediateFormat;
|
||||
int operandFormat;
|
||||
int branches;
|
||||
int accessesMemory;
|
||||
int accessesHighRegisters;
|
||||
int traps;
|
||||
int accessesSpecialRegisters;
|
||||
int affectsCPSR;
|
||||
};
|
||||
|
||||
void ARMDecodeThumb(uint16_t opcode, struct ThumbInstructionInfo* info);
|
||||
|
|
|
|||
Loading…
Reference in New Issue