79dfb8dc8f
Introduce `Platform::Log` ( #1640 )
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* Add Platform::Log and Platform::LogLevel
* Replace most printf calls with Platform::Log calls
* Move a brace down
* Move some log entries to one Log call
- Some implementations of Log may assume a full line
* Log the MAC address as LogLevel::Info
2023-03-23 18:04:38 +01:00
86d2e60df7
fix #1593
2023-01-03 18:50:03 +01:00
35cc79787d
update copyright headers
2022-01-09 02:15:50 +01:00
19ddaee13b
finally decouple Config from the core. baahhahahahah
2021-11-18 01:17:51 +01:00
c1dcd585be
decouple JIT from Config. bahahahahah
2021-11-17 18:15:50 +01:00
cca5615748
add the PU checks. bahahahah
2021-10-29 00:36:55 +02:00
43daa1c7d2
blarg
2021-10-28 21:24:39 +02:00
e121953c9a
more complete (and accurate) CP15 setup for direct boot
2021-10-28 21:15:12 +02:00
9d82826cdb
fix some gaps in CPU modes
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* non-defined CPU modes are actually possible
* bit4 of all PSRs is forced to one (modes 00-0F aren't possible)
* modes 14/15/16 and 18/19/1A share a SPSR with modes 17 and 1B respectively (but they don't share the register banks)
* modes 10 and 1C/1D/1E don't have a SPSR (MRS returns the CPSR always)
2021-10-28 19:45:32 +02:00
ff3f661bb5
DLDI/SD folder-sync apparatus ( #1251 )
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guess we can finally have DLDI that isn't obtuse
2021-10-28 18:47:13 +02:00
883fceb6ce
use std::swap 🔃
2021-08-21 01:54:45 +02:00
436b3c4c1d
update copyright year and add missing GPL headers
2021-03-12 20:07:40 +01:00
1dbe69c6be
remove some debug crap
2020-12-10 18:09:11 +01:00
81964a0f89
make things function atleast somewhat
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no pciture is being actually sent yet
2020-10-26 21:54:08 +01:00
8d42b1c7d7
messin' around
2020-09-08 20:19:37 +02:00
f56aa60eb6
check IRQ first then Idle loop
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apparently I put it this way for a reason
2020-07-28 00:44:58 +02:00
5903b11bda
subtract cycles after checking IRQ and Halt
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also switch back to adding to ARM::Cycles instead of subtracting from them
2020-07-27 23:14:39 +02:00
8a96dfce18
fix build with JIT disabled
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fixes #675 and #674
2020-07-25 20:59:53 +02:00
c5381d2911
reconcile DSi and JIT, fastmem for x64 and Windows
2020-06-30 23:50:41 +02:00
e335a8ca76
first steps in bringing over the JIT refactor/fastmem
2020-06-16 12:11:19 +02:00
052ff73672
rewrite JIT memory emulation
2020-06-16 12:01:08 +02:00
6d217e1010
fix build with JIT disabled and set default JIT maxblock size to 32
2020-06-16 11:59:09 +02:00
1c07932b40
implement block linking + some refactoring
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currently only supported for x64
2020-06-16 11:59:06 +02:00
baed0ac0d5
remove debug leftovers
2020-06-16 11:57:50 +02:00
ec965c6014
improve nop handling and proper behaviour for LDM^
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fixes dslinux
2020-06-16 11:57:49 +02:00
1cfbbcbb2a
make savestates 100% compatible again
2020-06-16 11:57:48 +02:00
441869a105
integrate changes from ARM64 backend and more
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- better handle LDM/STM in reg alloc
- unify Halted and IRQ in anticipation for branch inlining
- literal optimisations can be disabled in gui
- jit blocks follow simple returns
- fix idle loop detection
- break jit blocks on IRQ (fixes saving in Pokemon White)
2020-06-16 11:57:45 +02:00
40b88ab05a
new block cache and much more...
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- more reliable code invalidation detection
- blocks aren't stopped at any branch, but are being followed
if possible to get larger blocks
- idle loop recognition
- optimised literal loads, load/store cycle counting
and loads/stores from constant addresses
2020-06-16 11:56:36 +02:00
316378092a
abandon pipelining on jit
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fixes Golden Sun Dawn
this makes the cpu state incompatible between interpreter and JIT. That's why switching cpu mode requires a restart(not requiring is stupid anyway) and the pipeline is manually filled when making a save state.
2020-06-16 11:55:24 +02:00
00cd9af033
fix uninitialised memory mapping
2020-06-16 11:54:47 +02:00
4deecc7d65
jit: decrease blockcache AddrMapping size for ARM9
2020-06-16 11:54:05 +02:00
86f2be7260
jit: add compile option
2020-06-16 11:54:03 +02:00
d13d625f73
jit: make everything configurable
2020-06-16 11:53:21 +02:00
f22521a43d
jit: LDM/STM finally(!) working + MUL, MLA and CLZ
2020-06-16 11:53:10 +02:00
83bd863361
jit: branch instructions
2020-06-16 11:53:09 +02:00
10e386fe50
JIT: most mem instructions working
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+ branching
2020-06-16 11:53:08 +02:00
2f6b46fd4f
JIT: implemented most ALU instructions
2020-06-16 11:53:06 +02:00
c692287eba
JIT: base
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all instructions are interpreted
2020-06-16 11:53:05 +02:00
43e045357f
make it able to switch between DS and DSi modes
2020-06-01 20:36:30 +02:00
2327de2423
Merge commit '4b57416552ec2fa95216e2b044559f215723bf70' into melonDSi
2020-05-30 03:12:42 +02:00
5f99a68151
detect whether we are running the game
2020-02-24 18:31:44 +01:00
85a6a5bb38
* add support for a bunch of codes (all of them minus the loop shit, really)
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* hook it betterer so it doesn't asplode
2020-02-14 23:34:26 +01:00
83f8e11bc1
update copyright years
2020-02-14 20:18:08 +01:00
81dde71eba
add AES, fix a bunch of bugs
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we're getting an error screen! wee
2019-06-19 14:24:49 +02:00
606a40e6b8
y'know, actually running the DMA units might yield better results.
2019-06-18 22:57:37 +02:00
78c41736c3
fix fucking ass-stupid bug with new-WRAM handling
2019-06-16 14:26:54 +02:00
4d3f346edc
get it to do more interesting things
2019-06-15 18:30:12 +02:00
58e3ff61ac
add I2C shito
2019-06-15 16:58:02 +02:00
09cfdc6e76
pft
2019-06-10 18:24:38 +02:00
434a3007e2
fasterer BG/OBJ VRAM reads
2019-06-09 16:06:01 +02:00
Jesse Talavera-Greenberg