* fix 'STMxx with base register included in register list' when base register is banked.
* fix cart DMA for ARM9.
This commit is contained in:
parent
829b044802
commit
5ccf56d21d
2
ARM.cpp
2
ARM.cpp
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@ -216,7 +216,7 @@ void ARM::RestoreCPSR()
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break;
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break;
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default:
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default:
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printf("!! attempt to restore CPSR under bad mode %02X\n", CPSR&0x1F);
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printf("!! attempt to restore CPSR under bad mode %02X, %08X\n", CPSR&0x1F, R[15]);
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break;
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break;
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}
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}
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@ -441,8 +441,17 @@ void A_STM(ARM* cpu)
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preinc = !preinc;
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preinc = !preinc;
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}
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}
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bool isbanked = false;
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if (cpu->CurInstr & (1<<22))
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if (cpu->CurInstr & (1<<22))
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{
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u32 mode = (cpu->CPSR & 0x1F);
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if (mode == 0x11)
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isbanked = (baseid >= 8 && baseid < 15);
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else if (mode != 0x10 && mode != 0x1F)
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isbanked = (baseid >= 13 && baseid < 15);
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cpu->UpdateMode(cpu->CPSR, (cpu->CPSR&~0x1F)|0x10);
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cpu->UpdateMode(cpu->CPSR, (cpu->CPSR&~0x1F)|0x10);
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}
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for (u32 i = 0; i < 16; i++)
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for (u32 i = 0; i < 16; i++)
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{
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{
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@ -450,7 +459,7 @@ void A_STM(ARM* cpu)
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{
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{
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if (preinc) base += 4;
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if (preinc) base += 4;
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if (i == baseid)
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if (i == baseid && !isbanked)
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{
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{
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if ((cpu->Num == 0) || (!(cpu->CurInstr & (i-1))))
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if ((cpu->Num == 0) || (!(cpu->CurInstr & (i-1))))
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cpu->DataWrite32(base, oldbase);
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cpu->DataWrite32(base, oldbase);
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4
DMA.cpp
4
DMA.cpp
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@ -110,6 +110,8 @@ void DMA::Start()
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if ((Cnt & 0x00600000) == 0x00600000)
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if ((Cnt & 0x00600000) == 0x00600000)
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CurDstAddr = DstAddr;
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CurDstAddr = DstAddr;
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//printf("ARM%d DMA%d %08X %08X->%08X %d bytes %dbit\n", CPU?7:9, Num, Cnt, CurSrcAddr, CurDstAddr, RemCount*((Cnt&0x04000000)?4:2), (Cnt&0x04000000)?32:16);
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// special path for cart DMA. this is a gross hack.
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// special path for cart DMA. this is a gross hack.
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// emulating it properly requires emulating cart transfer delays, so uh... TODO
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// emulating it properly requires emulating cart transfer delays, so uh... TODO
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if (CurSrcAddr==0x04100010 && RemCount==1 && (Cnt & 0x07E00000)==0x07000000 &&
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if (CurSrcAddr==0x04100010 && RemCount==1 && (Cnt & 0x07E00000)==0x07000000 &&
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@ -122,8 +124,6 @@ void DMA::Start()
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return;
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return;
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}
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}
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//printf("ARM%d DMA%d %08X %08X->%08X %d bytes %dbit\n", CPU?7:9, Num, Cnt, CurSrcAddr, CurDstAddr, RemCount*((Cnt&0x04000000)?4:2), (Cnt&0x04000000)?32:16);
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// TODO: NOT MAKE THE DMA INSTANT!!
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// TODO: NOT MAKE THE DMA INSTANT!!
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if (!(Cnt & 0x04000000))
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if (!(Cnt & 0x04000000))
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{
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{
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15
NDS.cpp
15
NDS.cpp
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@ -167,10 +167,19 @@ void SetupDirectBoot()
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ARM9Write32(0x027FF800, 0x00001FC2);
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ARM9Write32(0x027FF800, 0x00001FC2);
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ARM9Write32(0x027FF804, 0x00001FC2);
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ARM9Write32(0x027FF804, 0x00001FC2);
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ARM9Write16(0x027FF808, *(u16*)&NDSCart::CartROM[0x15E]);
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ARM9Write16(0x027FF80A, *(u16*)&NDSCart::CartROM[0x6C]);
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ARM9Write16(0x027FF850, 0x5835);
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ARM9Write32(0x027FFC00, 0x00001FC2);
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ARM9Write32(0x027FFC00, 0x00001FC2);
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ARM9Write32(0x027FFC04, 0x00001FC2);
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ARM9Write32(0x027FFC04, 0x00001FC2);
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ARM9Write16(0x027FFC08, *(u16*)&NDSCart::CartROM[0x15E]);
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ARM9Write16(0x027FFC0A, *(u16*)&NDSCart::CartROM[0x6C]);
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ARM9Write16(0x027FFC10, 0x5835);
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ARM9Write16(0x027FFC30, 0xFFFF);
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ARM9Write16(0x027FFC30, 0xFFFF);
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ARM9Write16(0x027FFC40, 0x0001);
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CP15::Write(0x910, 0x0300000A);
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CP15::Write(0x910, 0x0300000A);
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CP15::Write(0x911, 0x00000020);
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CP15::Write(0x911, 0x00000020);
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@ -274,7 +283,7 @@ void Reset()
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// test
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// test
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//LoadROM();
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//LoadROM();
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//LoadFirmware();
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//LoadFirmware();
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NDSCart::LoadROM("rom/nsmb.nds");
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NDSCart::LoadROM("rom/peach.nds");
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Running = true; // hax
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Running = true; // hax
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}
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}
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@ -1605,7 +1614,7 @@ void ARM9IOWrite16(u32 addr, u16 val)
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return;
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return;
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}
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}
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printf("unknown ARM9 IO write16 %08X %04X\n", addr, val);
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printf("unknown ARM9 IO write16 %08X %04X %08X\n", addr, val, ARM9->R[14]);
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}
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}
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void ARM9IOWrite32(u32 addr, u32 val)
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void ARM9IOWrite32(u32 addr, u32 val)
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@ -1679,7 +1688,7 @@ void ARM9IOWrite32(u32 addr, u32 val)
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case 0x040001B4: *(u32*)&ROMSeed1[0] = val; return;
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case 0x040001B4: *(u32*)&ROMSeed1[0] = val; return;
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case 0x04000208: IME[0] = val & 0x1; return;
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case 0x04000208: IME[0] = val & 0x1; return;
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case 0x04000210: IE[0] = val; if (val&~0x000F0F7F)printf("unusual IRQ %08X\n",val);return;
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case 0x04000210: IE[0] = val; if (val&~0x000F2F7F)printf("unusual IRQ %08X\n",val);return;
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case 0x04000214: IF[0] &= ~val; return;
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case 0x04000214: IF[0] &= ~val; return;
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case 0x04000240:
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case 0x04000240:
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@ -850,7 +850,7 @@ void WriteROMCnt(u32 val)
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EndTransfer();
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EndTransfer();
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else
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else
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{
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{
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NDS::CheckDMAs(0, 0x06);
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NDS::CheckDMAs(0, 0x05);
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NDS::CheckDMAs(1, 0x12);
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NDS::CheckDMAs(1, 0x12);
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}
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}
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//NDS::ScheduleEvent((ROMCnt & (1<<27)) ? 8:5, ROMPrepareData, 0);
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//NDS::ScheduleEvent((ROMCnt & (1<<27)) ? 8:5, ROMPrepareData, 0);
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2
RTC.cpp
2
RTC.cpp
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@ -93,7 +93,7 @@ void ByteIn(u8 val)
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Output[0] = 0x17;
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Output[0] = 0x17;
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Output[1] = 0x01;
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Output[1] = 0x01;
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Output[2] = 0x19;
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Output[2] = 0x19;
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Output[3] = 0x03; // day of week. checkme
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Output[3] = 0x04; // day of week. checkme. apparently 04=Thursday
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Output[4] = 0x06;
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Output[4] = 0x06;
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Output[5] = 0x30;
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Output[5] = 0x30;
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Output[6] = 0x30;
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Output[6] = 0x30;
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@ -10,7 +10,7 @@
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1481161027 c:\documents\sources\melonds\types.h
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1481161027 c:\documents\sources\melonds\types.h
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1486163139 source:c:\documents\sources\melonds\nds.cpp
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1486309683 source:c:\documents\sources\melonds\nds.cpp
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<stdio.h>
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<stdio.h>
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<string.h>
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<string.h>
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"NDS.h"
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"NDS.h"
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@ -24,13 +24,13 @@
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"RTC.h"
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"RTC.h"
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"Wifi.h"
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"Wifi.h"
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1486152642 source:c:\documents\sources\melonds\arm.cpp
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1486309562 source:c:\documents\sources\melonds\arm.cpp
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<stdio.h>
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<stdio.h>
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"NDS.h"
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"NDS.h"
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"ARM.h"
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"ARM.h"
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"ARMInterpreter.h"
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"ARMInterpreter.h"
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1485806035 c:\documents\sources\melonds\arm.h
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1486261220 c:\documents\sources\melonds\arm.h
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"types.h"
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"types.h"
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"NDS.h"
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"NDS.h"
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"CP15.h"
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"CP15.h"
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@ -41,7 +41,7 @@
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"types.h"
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"types.h"
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"ARM.h"
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"ARM.h"
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1485831103 source:c:\documents\sources\melonds\arminterpreter.cpp
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1486253445 source:c:\documents\sources\melonds\arminterpreter.cpp
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<stdio.h>
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<stdio.h>
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"NDS.h"
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"NDS.h"
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"CP15.h"
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"CP15.h"
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@ -65,7 +65,7 @@
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1485795628 c:\documents\sources\melonds\arminterpreter_loadstore.h
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1485795628 c:\documents\sources\melonds\arminterpreter_loadstore.h
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1485977845 source:c:\documents\sources\melonds\arminterpreter_loadstore.cpp
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1486261538 source:c:\documents\sources\melonds\arminterpreter_loadstore.cpp
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<stdio.h>
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<stdio.h>
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"ARM.h"
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"ARM.h"
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@ -80,13 +80,13 @@
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1485900740 c:\documents\sources\melonds\spi.h
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1485900740 c:\documents\sources\melonds\spi.h
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1485905004 source:c:\documents\sources\melonds\spi.cpp
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1486163389 source:c:\documents\sources\melonds\spi.cpp
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<stdio.h>
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<stdio.h>
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<string.h>
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<string.h>
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"NDS.h"
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"NDS.h"
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"SPI.h"
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"SPI.h"
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1486163016 source:c:\documents\sources\melonds\gpu2d.cpp
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1486264329 source:c:\documents\sources\melonds\gpu2d.cpp
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<stdio.h>
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<stdio.h>
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<string.h>
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<string.h>
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"NDS.h"
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"NDS.h"
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@ -108,7 +108,7 @@
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1484612398 c:\documents\sources\melonds\fifo.h
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1484612398 c:\documents\sources\melonds\fifo.h
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"types.h"
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"types.h"
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1486143982 source:c:\documents\sources\melonds\dma.cpp
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1486309616 source:c:\documents\sources\melonds\dma.cpp
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<stdio.h>
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<stdio.h>
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"NDS.h"
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"NDS.h"
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"DMA.h"
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"DMA.h"
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@ -129,7 +129,7 @@
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1484848282 c:\documents\sources\melonds\rtc.h
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1484848282 c:\documents\sources\melonds\rtc.h
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"types.h"
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"types.h"
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1485016019 source:c:\documents\sources\melonds\rtc.cpp
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1486244121 source:c:\documents\sources\melonds\rtc.cpp
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<stdio.h>
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<stdio.h>
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<string.h>
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<string.h>
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"RTC.h"
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"RTC.h"
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@ -137,7 +137,7 @@
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1485980863 c:\documents\sources\melonds\ndscart.h
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1485980863 c:\documents\sources\melonds\ndscart.h
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"types.h"
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"types.h"
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1486137256 source:c:\documents\sources\melonds\ndscart.cpp
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1486309588 source:c:\documents\sources\melonds\ndscart.cpp
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<stdio.h>
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<stdio.h>
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<string.h>
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<string.h>
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"NDS.h"
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"NDS.h"
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