From 5ccf56d21d51638f2a0dc5d165da30bc4f4e0723 Mon Sep 17 00:00:00 2001 From: StapleButter Date: Sun, 5 Feb 2017 16:50:20 +0100 Subject: [PATCH] * fix 'STMxx with base register included in register list' when base register is banked. * fix cart DMA for ARM9. --- ARM.cpp | 2 +- ARMInterpreter_LoadStore.cpp | 11 ++++++++++- DMA.cpp | 4 ++-- NDS.cpp | 15 ++++++++++++--- NDSCart.cpp | 2 +- RTC.cpp | 2 +- melonDS.depend | 20 ++++++++++---------- 7 files changed, 37 insertions(+), 19 deletions(-) diff --git a/ARM.cpp b/ARM.cpp index 6e1faf40..80ba82be 100644 --- a/ARM.cpp +++ b/ARM.cpp @@ -216,7 +216,7 @@ void ARM::RestoreCPSR() break; default: - printf("!! attempt to restore CPSR under bad mode %02X\n", CPSR&0x1F); + printf("!! attempt to restore CPSR under bad mode %02X, %08X\n", CPSR&0x1F, R[15]); break; } diff --git a/ARMInterpreter_LoadStore.cpp b/ARMInterpreter_LoadStore.cpp index 8f701b51..ccbee34a 100644 --- a/ARMInterpreter_LoadStore.cpp +++ b/ARMInterpreter_LoadStore.cpp @@ -441,8 +441,17 @@ void A_STM(ARM* cpu) preinc = !preinc; } + bool isbanked = false; if (cpu->CurInstr & (1<<22)) + { + u32 mode = (cpu->CPSR & 0x1F); + if (mode == 0x11) + isbanked = (baseid >= 8 && baseid < 15); + else if (mode != 0x10 && mode != 0x1F) + isbanked = (baseid >= 13 && baseid < 15); + cpu->UpdateMode(cpu->CPSR, (cpu->CPSR&~0x1F)|0x10); + } for (u32 i = 0; i < 16; i++) { @@ -450,7 +459,7 @@ void A_STM(ARM* cpu) { if (preinc) base += 4; - if (i == baseid) + if (i == baseid && !isbanked) { if ((cpu->Num == 0) || (!(cpu->CurInstr & (i-1)))) cpu->DataWrite32(base, oldbase); diff --git a/DMA.cpp b/DMA.cpp index 91cb5324..12845658 100644 --- a/DMA.cpp +++ b/DMA.cpp @@ -110,6 +110,8 @@ void DMA::Start() if ((Cnt & 0x00600000) == 0x00600000) CurDstAddr = DstAddr; + //printf("ARM%d DMA%d %08X %08X->%08X %d bytes %dbit\n", CPU?7:9, Num, Cnt, CurSrcAddr, CurDstAddr, RemCount*((Cnt&0x04000000)?4:2), (Cnt&0x04000000)?32:16); + // special path for cart DMA. this is a gross hack. // emulating it properly requires emulating cart transfer delays, so uh... TODO if (CurSrcAddr==0x04100010 && RemCount==1 && (Cnt & 0x07E00000)==0x07000000 && @@ -122,8 +124,6 @@ void DMA::Start() return; } - //printf("ARM%d DMA%d %08X %08X->%08X %d bytes %dbit\n", CPU?7:9, Num, Cnt, CurSrcAddr, CurDstAddr, RemCount*((Cnt&0x04000000)?4:2), (Cnt&0x04000000)?32:16); - // TODO: NOT MAKE THE DMA INSTANT!! if (!(Cnt & 0x04000000)) { diff --git a/NDS.cpp b/NDS.cpp index d1d0c4b6..217a5240 100644 --- a/NDS.cpp +++ b/NDS.cpp @@ -167,10 +167,19 @@ void SetupDirectBoot() ARM9Write32(0x027FF800, 0x00001FC2); ARM9Write32(0x027FF804, 0x00001FC2); + ARM9Write16(0x027FF808, *(u16*)&NDSCart::CartROM[0x15E]); + ARM9Write16(0x027FF80A, *(u16*)&NDSCart::CartROM[0x6C]); + + ARM9Write16(0x027FF850, 0x5835); + ARM9Write32(0x027FFC00, 0x00001FC2); ARM9Write32(0x027FFC04, 0x00001FC2); + ARM9Write16(0x027FFC08, *(u16*)&NDSCart::CartROM[0x15E]); + ARM9Write16(0x027FFC0A, *(u16*)&NDSCart::CartROM[0x6C]); + ARM9Write16(0x027FFC10, 0x5835); ARM9Write16(0x027FFC30, 0xFFFF); + ARM9Write16(0x027FFC40, 0x0001); CP15::Write(0x910, 0x0300000A); CP15::Write(0x911, 0x00000020); @@ -274,7 +283,7 @@ void Reset() // test //LoadROM(); //LoadFirmware(); - NDSCart::LoadROM("rom/nsmb.nds"); + NDSCart::LoadROM("rom/peach.nds"); Running = true; // hax } @@ -1605,7 +1614,7 @@ void ARM9IOWrite16(u32 addr, u16 val) return; } - printf("unknown ARM9 IO write16 %08X %04X\n", addr, val); + printf("unknown ARM9 IO write16 %08X %04X %08X\n", addr, val, ARM9->R[14]); } void ARM9IOWrite32(u32 addr, u32 val) @@ -1679,7 +1688,7 @@ void ARM9IOWrite32(u32 addr, u32 val) case 0x040001B4: *(u32*)&ROMSeed1[0] = val; return; case 0x04000208: IME[0] = val & 0x1; return; - case 0x04000210: IE[0] = val; if (val&~0x000F0F7F)printf("unusual IRQ %08X\n",val);return; + case 0x04000210: IE[0] = val; if (val&~0x000F2F7F)printf("unusual IRQ %08X\n",val);return; case 0x04000214: IF[0] &= ~val; return; case 0x04000240: diff --git a/NDSCart.cpp b/NDSCart.cpp index 9a2e0944..3bfc814d 100644 --- a/NDSCart.cpp +++ b/NDSCart.cpp @@ -850,7 +850,7 @@ void WriteROMCnt(u32 val) EndTransfer(); else { - NDS::CheckDMAs(0, 0x06); + NDS::CheckDMAs(0, 0x05); NDS::CheckDMAs(1, 0x12); } //NDS::ScheduleEvent((ROMCnt & (1<<27)) ? 8:5, ROMPrepareData, 0); diff --git a/RTC.cpp b/RTC.cpp index 76043533..c5b9d505 100644 --- a/RTC.cpp +++ b/RTC.cpp @@ -93,7 +93,7 @@ void ByteIn(u8 val) Output[0] = 0x17; Output[1] = 0x01; Output[2] = 0x19; - Output[3] = 0x03; // day of week. checkme + Output[3] = 0x04; // day of week. checkme. apparently 04=Thursday Output[4] = 0x06; Output[5] = 0x30; Output[6] = 0x30; diff --git a/melonDS.depend b/melonDS.depend index e517db75..77cdb916 100644 --- a/melonDS.depend +++ b/melonDS.depend @@ -10,7 +10,7 @@ 1481161027 c:\documents\sources\melonds\types.h -1486163139 source:c:\documents\sources\melonds\nds.cpp +1486309683 source:c:\documents\sources\melonds\nds.cpp "NDS.h" @@ -24,13 +24,13 @@ "RTC.h" "Wifi.h" -1486152642 source:c:\documents\sources\melonds\arm.cpp +1486309562 source:c:\documents\sources\melonds\arm.cpp "NDS.h" "ARM.h" "ARMInterpreter.h" -1485806035 c:\documents\sources\melonds\arm.h +1486261220 c:\documents\sources\melonds\arm.h "types.h" "NDS.h" "CP15.h" @@ -41,7 +41,7 @@ "types.h" "ARM.h" -1485831103 source:c:\documents\sources\melonds\arminterpreter.cpp +1486253445 source:c:\documents\sources\melonds\arminterpreter.cpp "NDS.h" "CP15.h" @@ -65,7 +65,7 @@ 1485795628 c:\documents\sources\melonds\arminterpreter_loadstore.h -1485977845 source:c:\documents\sources\melonds\arminterpreter_loadstore.cpp +1486261538 source:c:\documents\sources\melonds\arminterpreter_loadstore.cpp "ARM.h" @@ -80,13 +80,13 @@ 1485900740 c:\documents\sources\melonds\spi.h -1485905004 source:c:\documents\sources\melonds\spi.cpp +1486163389 source:c:\documents\sources\melonds\spi.cpp "NDS.h" "SPI.h" -1486163016 source:c:\documents\sources\melonds\gpu2d.cpp +1486264329 source:c:\documents\sources\melonds\gpu2d.cpp "NDS.h" @@ -108,7 +108,7 @@ 1484612398 c:\documents\sources\melonds\fifo.h "types.h" -1486143982 source:c:\documents\sources\melonds\dma.cpp +1486309616 source:c:\documents\sources\melonds\dma.cpp "NDS.h" "DMA.h" @@ -129,7 +129,7 @@ 1484848282 c:\documents\sources\melonds\rtc.h "types.h" -1485016019 source:c:\documents\sources\melonds\rtc.cpp +1486244121 source:c:\documents\sources\melonds\rtc.cpp "RTC.h" @@ -137,7 +137,7 @@ 1485980863 c:\documents\sources\melonds\ndscart.h "types.h" -1486137256 source:c:\documents\sources\melonds\ndscart.cpp +1486309588 source:c:\documents\sources\melonds\ndscart.cpp "NDS.h"