2016-12-05 17:02:29 +00:00
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/*
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2018-09-15 00:32:13 +00:00
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Copyright 2016-2019 StapleButter
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2016-12-05 17:02:29 +00:00
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This file is part of melonDS.
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melonDS is free software: you can redistribute it and/or modify it under
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the terms of the GNU General Public License as published by the Free
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Software Foundation, either version 3 of the License, or (at your option)
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any later version.
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melonDS is distributed in the hope that it will be useful, but WITHOUT ANY
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WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
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You should have received a copy of the GNU General Public License along
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with melonDS. If not, see http://www.gnu.org/licenses/.
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*/
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2016-05-16 15:48:40 +00:00
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#ifndef NDS_H
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#define NDS_H
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2018-09-15 00:47:34 +00:00
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#include "Savestate.h"
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2016-05-16 15:48:40 +00:00
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#include "types.h"
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namespace NDS
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{
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2017-01-30 17:36:11 +00:00
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enum
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{
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2017-02-03 17:47:40 +00:00
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Event_LCD = 0,
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2017-04-06 17:44:34 +00:00
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Event_SPU,
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2017-05-01 20:27:05 +00:00
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Event_Wifi,
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2017-01-30 17:36:11 +00:00
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2017-06-26 09:02:10 +00:00
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Event_DisplayFIFO,
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2017-04-11 18:21:31 +00:00
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Event_ROMTransfer,
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2017-07-15 17:29:10 +00:00
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Event_ROMSPITransfer,
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Event_SPITransfer,
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2017-07-15 17:46:27 +00:00
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Event_Div,
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Event_Sqrt,
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2017-04-11 18:21:31 +00:00
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2017-01-30 17:36:11 +00:00
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Event_MAX
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};
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2017-01-31 02:54:51 +00:00
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typedef struct
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{
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void (*Func)(u32 param);
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s32 WaitCycles;
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u32 Param;
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} SchedEvent;
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2016-12-04 02:20:50 +00:00
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enum
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{
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IRQ_VBlank = 0,
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IRQ_HBlank,
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IRQ_VCount,
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IRQ_Timer0,
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IRQ_Timer1,
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IRQ_Timer2,
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IRQ_Timer3,
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IRQ_RTC,
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IRQ_DMA0,
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IRQ_DMA1,
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IRQ_DMA2,
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IRQ_DMA3,
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IRQ_Keypad,
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IRQ_GBASlot,
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IRQ_Unused14,
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IRQ_Unused15,
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IRQ_IPCSync,
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IRQ_IPCSendDone,
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IRQ_IPCRecv,
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IRQ_CartSendDone,
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IRQ_CartIREQMC,
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IRQ_GXFIFO,
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IRQ_LidOpen,
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IRQ_SPI,
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IRQ_Wifi
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};
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2016-12-05 16:08:24 +00:00
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typedef struct
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{
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u16 Reload;
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2017-01-31 02:54:51 +00:00
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u16 Cnt;
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u32 Counter;
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u32 CycleShift;
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2016-12-05 16:08:24 +00:00
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} Timer;
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2016-12-23 20:22:22 +00:00
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// hax
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2016-12-06 16:32:51 +00:00
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extern u32 IME[2];
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2017-01-18 16:57:12 +00:00
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extern u32 IE[2];
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extern u32 IF[2];
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2016-12-23 20:22:22 +00:00
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extern Timer Timers[8];
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2017-10-30 04:45:26 +00:00
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extern u16 PowerControl9;
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2017-01-22 19:34:59 +00:00
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extern u16 ExMemCnt[2];
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extern u8 ROMSeed0[2*8];
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extern u8 ROMSeed1[2*8];
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extern u8 ARM9BIOS[0x1000];
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extern u8 ARM7BIOS[0x4000];
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2017-04-12 14:58:09 +00:00
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extern u8 MainRAM[0x400000];
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2017-02-07 21:23:46 +00:00
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bool Init();
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void DeInit();
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2016-05-16 15:48:40 +00:00
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void Reset();
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2017-09-21 01:59:12 +00:00
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void Stop();
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2016-05-16 15:48:40 +00:00
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2018-10-17 23:38:33 +00:00
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bool DoSavestate(Savestate* file);
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2018-09-15 00:47:34 +00:00
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2017-10-10 22:01:05 +00:00
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bool LoadROM(const char* path, bool direct);
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2017-03-29 16:59:20 +00:00
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void LoadBIOS();
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2017-02-01 20:35:00 +00:00
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void SetupDirectBoot();
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2017-05-10 00:21:02 +00:00
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u32 RunFrame();
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2016-11-24 17:31:49 +00:00
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2016-12-23 20:22:22 +00:00
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void PressKey(u32 key);
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void ReleaseKey(u32 key);
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2017-01-31 23:24:36 +00:00
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void TouchScreen(u16 x, u16 y);
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void ReleaseScreen();
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2016-12-23 20:22:22 +00:00
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2017-09-30 18:05:56 +00:00
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void SetKeyMask(u32 mask);
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2017-01-31 02:54:51 +00:00
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void ScheduleEvent(u32 id, bool periodic, s32 delay, void (*func)(u32), u32 param);
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void CancelEvent(u32 id);
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2016-12-05 16:08:24 +00:00
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2017-01-30 17:36:11 +00:00
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void debug(u32 p);
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2016-11-24 17:31:49 +00:00
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void Halt();
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2016-12-06 16:32:51 +00:00
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void MapSharedWRAM(u8 val);
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2016-12-03 17:29:19 +00:00
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2017-03-02 23:48:26 +00:00
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void SetIRQ(u32 cpu, u32 irq);
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void ClearIRQ(u32 cpu, u32 irq);
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2016-12-06 16:32:51 +00:00
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bool HaltInterrupted(u32 cpu);
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2017-03-02 23:48:26 +00:00
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void StopCPU(u32 cpu, u32 mask);
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void ResumeCPU(u32 cpu, u32 mask);
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2016-12-04 02:20:50 +00:00
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2017-06-25 15:35:45 +00:00
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u32 GetPC(u32 cpu);
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2017-06-26 09:02:10 +00:00
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bool DMAsInMode(u32 cpu, u32 mode);
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2017-01-22 19:34:59 +00:00
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void CheckDMAs(u32 cpu, u32 mode);
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2017-03-20 21:18:35 +00:00
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void StopDMAs(u32 cpu, u32 mode);
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2017-01-22 19:34:59 +00:00
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2017-03-20 16:39:42 +00:00
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void RunTimingCriticalDevices(u32 cpu, s32 cycles);
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2016-12-03 00:31:33 +00:00
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u8 ARM9Read8(u32 addr);
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u16 ARM9Read16(u32 addr);
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2016-11-03 00:38:58 +00:00
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u32 ARM9Read32(u32 addr);
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2016-12-03 00:31:33 +00:00
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void ARM9Write8(u32 addr, u8 val);
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void ARM9Write16(u32 addr, u16 val);
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void ARM9Write32(u32 addr, u32 val);
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2016-11-03 00:38:58 +00:00
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2016-12-03 00:31:33 +00:00
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u8 ARM7Read8(u32 addr);
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u16 ARM7Read16(u32 addr);
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u32 ARM7Read32(u32 addr);
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void ARM7Write8(u32 addr, u8 val);
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void ARM7Write16(u32 addr, u16 val);
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void ARM7Write32(u32 addr, u32 val);
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2016-05-16 15:48:40 +00:00
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2017-01-17 01:29:25 +00:00
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u8 ARM9IORead8(u32 addr);
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u16 ARM9IORead16(u32 addr);
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u32 ARM9IORead32(u32 addr);
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void ARM9IOWrite8(u32 addr, u8 val);
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void ARM9IOWrite16(u32 addr, u16 val);
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void ARM9IOWrite32(u32 addr, u32 val);
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u8 ARM7IORead8(u32 addr);
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u16 ARM7IORead16(u32 addr);
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u32 ARM7IORead32(u32 addr);
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void ARM7IOWrite8(u32 addr, u8 val);
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void ARM7IOWrite16(u32 addr, u16 val);
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void ARM7IOWrite32(u32 addr, u32 val);
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2016-05-16 15:48:40 +00:00
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}
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#endif // NDS_H
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