Commit Graph

132 Commits

Author SHA1 Message Date
Flyinghead 6305df9dab ignore fldi0/fldi1 in double precision instead of dying 2019-03-13 17:19:41 +01:00
Flyinghead 6d6492ddc1 mmu: flush tables when MMUCR.TI is written 2019-03-13 17:17:08 +01:00
Flyinghead 0d0fd212ff Implement Ch2 DMA to 32-bit VRAM
Fixes Giana's Return
2019-03-08 13:23:51 +01:00
Flyinghead 492e771272 Content browser (WIP)
Get rid of the renderer thread. It is now the main/UI thread on all
platforms. The emulator runs in a separate thread.
Content browser displayed at startup.
2019-02-25 17:52:53 +01:00
Flyinghead 35bb81b195 fix some printf format strings 2019-02-16 14:16:50 +01:00
flyinghead 3cdd39170d win32: call os_DoEvents on the emu/main thread and other fixes 2019-02-07 19:20:10 +01:00
Flyinghead 91cfd4b2f7 Reserve and allocate maximum RAM/VRAM/ARAM in all cases
Reserve enough virtual memory space for DC and Naomi
Allocate dynarec entry point tables for max possible ram
Free mem and release vmem on exit
2019-01-24 09:48:58 +01:00
Flyinghead 0cce6cc5a5 Clean up and comments. No functional change 2019-01-24 09:40:14 +01:00
Flyinghead cd4e4cbdc9 x64 dynarec: check if extension is supported by cpu. seh on win32
Check if FMA/AVX/SSE3 is supported before using it
fully naked main loop in win32 with proper seh directives
win32: more xmm regs to allocate and no need to save them when calling
out
2019-01-18 17:02:50 +01:00
flyinghead ed3f866835 win32 build fix 2019-01-16 17:42:36 +01:00
Flyinghead f852480b88 OSX: build fix 2019-01-16 14:44:40 +01:00
Flyinghead cb8e81d473 arm64: direct memory access and jit rewrite
generates direct vmem read & write accesses
trap sigsegv and rewrite using slow path
add w29 to allocatable registers
get rid of literals and use pc-rel branching
minor optimizations and cleanup
2019-01-16 13:04:16 +01:00
Flyinghead c2a048e8d8 arm64: use explode_spans to allocate regs for V2 and F64 params 2019-01-15 08:47:07 +01:00
Flyinghead e241613b8f x64 dynarec: implemented swaplb, fipr, ftrv, frswap and other fixes
native implementations for swaplb, fipr, ftrv and frswap
use explode_spans to map 2V and F64 to registers
save xmm registers when calling subroutine
2019-01-14 21:15:36 +01:00
Flyinghead b465f744ba dynarec: flush fpu regs before FTRV
fixes issue with tokyo xtreme racer (x64)
might need to flush before other ops
2019-01-13 23:21:58 +01:00
Flyinghead fc05727538 dynarecs clean-up
move GetRegPtr and ngen_FailedToFindBlock to sh4/dyna
2019-01-11 23:52:20 +01:00
Flyinghead 0f026552c9 fix comments 2019-01-11 15:54:03 +01:00
Flyinghead a9a2aad8f6 arm64: use register spans allocation. Implement some opcodes natively 2019-01-09 16:35:23 +01:00
Flyinghead 67a4eb8f1f arm64 dynarec using vixl 2019-01-07 21:50:46 +01:00
Flyinghead 10d9761a65 minor fix 2018-12-12 13:49:53 +01:00
Flyinghead 5763da184c Fix bug in WriteMemBlock_nommu_ptr when size is not word-aligned
Bump max opaque polygon to 8192 (alpilot)
Minor lr backport and clean up

Fix corruption in doa2[m] and alpilot
Fix missing sound in Jambo Safari
2018-12-12 12:40:04 +01:00
Flyinghead fb92d8d8c5 less log 2018-11-09 13:23:47 +01:00
Flyinghead a3f898b7d0 Naomi: implement undocumented SH4 registers to make version h bios happy 2018-11-06 10:54:13 +01:00
Flyinghead 47be33d388 Free dynarec code blocks on exit 2018-10-29 16:10:39 +01:00
Flyinghead 8a56710841 New save state format 2018-10-29 15:11:34 +01:00
Flyinghead 22b18d97a0 Don't flush the dynarec cache when the sh4 instruction cache is flushed
Fixes Shikigami No Shiro II slowness
2018-10-28 01:29:44 +02:00
Flyinghead fb84df6665 Better logging 2018-10-20 19:38:21 +02:00
Flyinghead 4b38b9b788 less log 2018-10-16 15:35:28 +02:00
Flyinghead 82e0fc7f60 Don't crash on invalid ram write size. Report and ignore 2018-10-11 21:15:00 +02:00
flyinghead c135ab0e90 Win32: fix msvc build. removed tick thread 2018-09-25 14:09:07 +02:00
flyinghead 21f47c03ec Fix dynarec x64 crash with mingw64.
Get rid of CDI warning pop up dialog
2018-09-25 12:27:37 +02:00
Flyinghead de147549c3 Save states implementation 2018-09-20 19:48:46 +02:00
Flyinghead 7ce4fccb37 Merge remote-tracking branch 'origin/master' into fh/mymaster 2018-09-20 17:28:41 +02:00
Sven daae7c8e68 add save states 2018-09-02 09:49:23 -04:00
Ender's Games 14fc7d910a Convert Interrupt Hack to name w/ less stigma 2018-08-26 23:13:25 -04:00
Ender's Games d8226c7b5d Fix: "Functions should be declared at file scope" 2018-08-22 21:14:42 -04:00
Ender's Games e5c0f0ee71 https://code.google.com/p/nulldc/source/detail?r=108
Originally ported from nullDC to libretro in commits:
2fa562db1b46c52b663b3dd4bb33a64907357458
f8eb58ac16a9e5adf662b99be5d00729264808e0
Modified for use w/ reicast per-game configuration
2018-08-22 21:14:02 -04:00
Ender's Games eb11d19687 Include header guards to prevent multiple inclusions 2018-08-21 09:28:54 -04:00
Ender's Games 8d9d40dffc Core: Changes provided by Android NDK compiler 2018-08-19 01:54:15 -04:00
Flyinghead 2fb9927688 Less console spamming 2018-08-17 18:30:54 +02:00
Ender's Games a3f585ea1c Port the dynarec safe flag from nullDC (See #84) 2018-08-16 20:00:10 -04:00
Flyinghead 2d3fd59e04 Revert f13b366e8d57c15a6a97cc0721d68ddb5268385f: the fixNaN function is
completely bogus and the correct one doesn't have any effect.
2018-07-14 09:13:56 +02:00
Flyinghead f13b366e8d Set the value for NaN according to the SH4 specs
The SH4 sets the signaling bit to 0 for qNaN: 7fbfffff instead of the
usual 7fffffff. Same games seem to rely on this.
Fixes Fur Fighters freeze and missing geometry in game.
2018-07-13 18:57:51 +02:00
Flyinghead ea35eeb728 Fix FTRC op in both interpreter and dynarec with respect to Inf and NaN
The -ffast-math gcc option implies the -ffinite-math-only option, which
produces wrong results with Inf and NaN. Use integer math to detect the
sign of float numbers in FTRC to avoid these issues.
Also the upper cut off value for conversion was apparently wrong.
Also fixed the x86 dynarec but not tested.
Fixes wrong car color in Tokyo Xtreme Racer car selection screen.
2018-07-13 12:02:32 +02:00
Flyinghead 648988e622 don't log div32 matching and some GDRom ops 2018-07-10 14:36:28 +02:00
Flyinghead 0df91770d2 Increase dynarec code cache size to 10 MB
Fixes frequent code cache invalidation due to lack of space, which kills
performance (Extreme Sports)
2018-07-06 17:19:37 +02:00
Flyinghead 315205caa9 Add setting to disable div32 matching (Pro Pinball Trilogy)
div32 matching doesn't handle division by zero and edge cases, which
causes crashes with some games.
Setting enabled by default for Pro Pinball Trilogy.
2018-07-06 09:49:39 +02:00
Nicolas HOUDELOT 5c343a219c fix typo 2018-03-05 01:57:00 +01:00
Stefanos Kornilios Mitsis Poiitidis 7c5e49a6d2 dyna: Fix f2i canonical + x86 to saturate 2016-05-14 04:15:16 +03:00
twinaphex b606593774 ftrc fix - revert back to nulldc defaults 2016-05-13 14:44:53 +02:00