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Reserve and allocate maximum RAM/VRAM/ARAM in all cases 

Reserve enough virtual memory space for DC and Naomi
Allocate dynarec entry point tables for max possible ram
Free mem and release vmem on exit
This commit is contained in:
Flyinghead 2019-01-24 09:48:58 +01:00
parent 0cce6cc5a5
commit 91cfd4b2f7
9 changed files with 76 additions and 38 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
core/build.h
View File

@ -286,6 +286,10 @@
#define FEAT_HAS_SOFTREND BUILD_COMPILER == COMPILER_VC //GCC wants us to enable sse4 globaly to enable intrins
#endif
#define RAM_SIZE_MAX (32*1024*1024)
#define VRAM_SIZE_MAX (16*1024*1024)
#define ARAM_SIZE_MAX (8*1024*1024)
//Depricated build configs
#ifdef HOST_NO_REC
#error Dont use HOST_NO_REC

10
core/hw/arm7/arm7.cpp
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@ -686,7 +686,7 @@ u8 ARM7_TCB[ICacheSize+4096] __attribute__((section("__TEXT, .text")));
using namespace ARM;
void* EntryPoints[ARAM_SIZE/4];
void* EntryPoints[ARAM_SIZE_MAX/4];
enum OpType
{
@ -1509,7 +1509,7 @@ naked void arm_dispatch()
#if HOST_OS == OS_LINUX
__asm ( "arm_dispatch: \n\t"
"mov %0, %%eax \n\t"
"and $0x1FFFFC, %%eax \n\t"
"and $0x7FFFFC, %%eax \n\t"
"cmp $0, %1 \n\t"
"jne arm_dofiq \n\t"
"jmp *%2(%%eax) \n"
@ -1529,7 +1529,7 @@ naked void arm_dispatch()
{
arm_disp:
mov eax,reg[R15_ARM_NEXT*4].I
and eax,0x1FFFFC
and eax,0x7FFFFC
cmp reg[INTR_PEND*4].I,0
jne arm_dofiq
jmp [EntryPoints+eax]
@ -2146,8 +2146,8 @@ extern "C" void CompileCode()
void FlushCache()
{
icPtr=ICache;
for (u32 i=0;i<ARAM_SIZE/4;i++)
EntryPoints[i]=(void*)&arm_compilecode;
for (u32 i = 0; i < ARRAY_SIZE(EntryPoints); i++)
EntryPoints[i] = &arm_compilecode;
}

55
core/hw/mem/_vmem.cpp
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@ -396,10 +396,15 @@ void _vmem_term()
u8* virt_ram_base;
void* malloc_pages(size_t size) {
u8* rv = (u8*)malloc(size + PAGE_SIZE);
return rv + PAGE_SIZE - ((unat)rv % PAGE_SIZE);
#ifdef _ISOC11_SOURCE
return aligned_alloc(PAGE_SIZE, size);
#else
void *data;
if (posix_memalign(&data, PAGE_SIZE, size) != 0)
return NULL;
else
return data;
#endif
}
bool _vmem_reserve_nonvmem()
@ -437,6 +442,14 @@ void _vmem_bm_reset() {
}
}
static void _vmem_release_nonvmem()
{
free(p_sh4rcb);
free(vram.data);
free(aica_ram.data);
free(mem_b.data);
}
#if !defined(TARGET_NO_NVMEM)
#define MAP_RAM_START_OFFSET 0
@ -483,9 +496,9 @@ void* _nvmem_unused_buffer(u32 start,u32 end)
void* _nvmem_alloc_mem()
{
mem_handle=CreateFileMapping(INVALID_HANDLE_VALUE,0,PAGE_READWRITE ,0,RAM_SIZE + VRAM_SIZE +ARAM_SIZE,0);
mem_handle = CreateFileMapping(INVALID_HANDLE_VALUE, 0, PAGE_READWRITE, 0, RAM_SIZE_MAX + VRAM_SIZE_MAX + ARAM_SIZE_MAX, 0);
void* rv=(u8*)VirtualAlloc(0,512*1024*1024 + sizeof(Sh4RCB) + ARAM_SIZE,MEM_RESERVE,PAGE_NOACCESS);
void* rv= (u8*)VirtualAlloc(0, 512*1024*1024 + sizeof(Sh4RCB) + ARAM_SIZE_MAX, MEM_RESERVE, PAGE_NOACCESS);
if (rv) VirtualFree(rv,0,MEM_RELEASE);
return rv;
}
@ -585,7 +598,7 @@ error:
string path = get_writable_data_path("/dcnzorz_mem");
fd = open(path.c_str(),O_CREAT|O_RDWR|O_TRUNC,S_IRWXU|S_IRWXG|S_IRWXO);
unlink(path.c_str());
verify(ftruncate(fd,RAM_SIZE + VRAM_SIZE +ARAM_SIZE)==0);
verify(ftruncate(fd, RAM_SIZE_MAX + VRAM_SIZE_MAX + ARAM_SIZE_MAX) == 0);
#elif !defined(_ANDROID)
fd = shm_open("/dcnzorz_mem", O_CREAT | O_EXCL | O_RDWR,S_IREAD | S_IWRITE);
shm_unlink("/dcnzorz_mem");
@ -595,10 +608,10 @@ error:
unlink("dcnzorz_mem");
}
verify(ftruncate(fd,RAM_SIZE + VRAM_SIZE +ARAM_SIZE)==0);
verify(ftruncate(fd, RAM_SIZE_MAX + VRAM_SIZE_MAX + ARAM_SIZE_MAX) == 0);
#else
fd = ashmem_create_region(0,RAM_SIZE + VRAM_SIZE +ARAM_SIZE);
fd = ashmem_create_region(0, RAM_SIZE_MAX + VRAM_SIZE_MAX + ARAM_SIZE_MAX);
if (false)//this causes writebacks to flash -> slow and stuttery
{
fd = open("/data/data/com.reicast.emulator/files/dcnzorz_mem",O_CREAT|O_RDWR|O_TRUNC,S_IRWXU|S_IRWXG|S_IRWXO);
@ -608,7 +621,7 @@ error:
u32 sz= 512*1024*1024 + sizeof(Sh4RCB) + ARAM_SIZE + 0x10000;
u32 sz = 512*1024*1024 + sizeof(Sh4RCB) + ARAM_SIZE_MAX + 0x10000;
void* rv=mmap(0, sz, PROT_NONE, MAP_PRIVATE | MAP_ANON, -1, 0);
verify(rv != NULL);
munmap(rv,sz);
@ -695,6 +708,7 @@ bool _vmem_reserve()
p_sh4rcb=(Sh4RCB*)virt_ram_base;
// Map the sh4 context but protect access to Sh4RCB.fpcb[]
#if HOST_OS==OS_WINDOWS
//verify(p_sh4rcb==VirtualAlloc(p_sh4rcb,sizeof(Sh4RCB),MEM_RESERVE|MEM_COMMIT,PAGE_READWRITE));
verify(p_sh4rcb==VirtualAlloc(p_sh4rcb,sizeof(Sh4RCB),MEM_RESERVE,PAGE_NOACCESS));
@ -771,15 +785,30 @@ bool _vmem_reserve()
return virt_ram_base!=0;
}
void _vmem_release()
{
if (!_nvmem_enabled())
_vmem_release_nonvmem();
else
{
if (virt_ram_base != NULL)
{
munmap(virt_ram_base, 0x20000000);
virt_ram_base = NULL;
}
close(fd);
}
}
#else
bool _vmem_reserve()
{
return _vmem_reserve_nonvmem();
}
#endif
void _vmem_release()
{
//TODO
_vmem_release_nonvmem();
}
#endif

2
core/hw/sh4/sh4_if.h
View File

@ -299,7 +299,7 @@ void DYNACALL do_sqw_nommu_full(u32 dst, u8* sqb);
typedef void DYNACALL sqw_fp(u32 dst,u8* sqb);
typedef void DYNACALL TaListVoidFP(void* data);
#define FPCB_SIZE (RAM_SIZE/2)
#define FPCB_SIZE (RAM_SIZE_MAX/2)
#define FPCB_MASK (FPCB_SIZE -1)
//#defeine FPCB_PAD 0x40000
#define FPCB_PAD 0x100000

12
core/rec-ARM/ngen_arm.S
View File

@ -177,14 +177,14 @@ CSYM(no_update): @ next_pc _MUST_ be on r4 *R4 NOT R0 anymore*
cmp r0,#0
beq CSYM(cleanup)
#if DC_PLATFORM == DC_PLATFORM_NAOMI
#if RAM_SIZE_MAX == 33554432
sub r2,r8,#0x4100000
ubfx r1,r4,#1,#24
#elif DC_PLATFORM == DC_PLATFORM_DREAMCAST
ubfx r1,r4,#1,#24 @ 24+1 bits: 32 MB
#elif RAM_SIZE_MAX == 16777216
sub r2,r8,#0x2100000
ubfx r1,r4,#1,#23
ubfx r1,r4,#1,#23 @ 23+1 bits: 16 MB
#else
#error "Define DC_PLATFORM"
#error "Define RAM_SIZE_MAX"
#endif
ldr pc,[r2,r1,lsl #2]
@ -241,7 +241,7 @@ HIDDEN(arm_dispatch)
CSYM(arm_dispatch):
ldrd r0,r1,[r8,#184] @load: Next PC, interrupt
ubfx r2,r0,#2,#21
ubfx r2,r0,#2,#21 @ assuming 8 MB address space max (23 bits)
cmp r1,#0
bne arm_dofiq

8
core/rec-ARM/rec_arm.cpp
View File

@ -402,7 +402,7 @@ u32 DynaRBI::Relink()
#ifdef CALLSTACK
#error offset broken
SUB(r2, r8, -FPCB_OFFSET);
#if RAM_SIZE == 33554432
#if RAM_SIZE_MAX == 33554432
UBFX(r1, r4, 1, 24);
#else
UBFX(r1, r4, 1, 23);
@ -429,7 +429,7 @@ u32 DynaRBI::Relink()
//this is faster
//why ? (Icache ?)
SUB(r2, r8, -FPCB_OFFSET);
#if RAM_SIZE == 33554432
#if RAM_SIZE_MAX == 33554432
UBFX(r1, r4, 1, 24);
#else
UBFX(r1, r4, 1, 23);
@ -448,7 +448,7 @@ u32 DynaRBI::Relink()
{
SUB(r2, r8, -FPCB_OFFSET);
#if RAM_SIZE == 33554432
#if RAM_SIZE_MAX == 33554432
UBFX(r1, r4, 1, 24);
#else
UBFX(r1, r4, 1, 23);
@ -463,7 +463,7 @@ u32 DynaRBI::Relink()
verify(pBranchBlock==0);
SUB(r2, r8, -FPCB_OFFSET);
#if RAM_SIZE == 33554432
#if RAM_SIZE_MAX == 33554432
UBFX(r1, r4, 1, 24);
#else
UBFX(r1, r4, 1, 23);

12
core/rec-ARM64/rec_arm64.cpp
View File

@ -212,12 +212,12 @@ void ngen_mainloop(void* v_cntx)
"movz x2, %[RCB_SIZE], lsl #16 \n\t"
"sub x2, x28, x2 \n\t"
"add x2, x2, %[SH4CTX_SIZE] \n\t"
#if RAM_SIZE == 33554432
"ubfx w1, w29, #1, #24 \n\t"
#elif RAM_SIZE == 16777216
"ubfx w1, w29, #1, #23 \n\t"
#if RAM_SIZE_MAX == 33554432
"ubfx w1, w29, #1, #24 \n\t" // 24+1 bits: 32 MB
#elif RAM_SIZE_MAX == 16777216
"ubfx w1, w29, #1, #23 \n\t" // 23+1 bits: 16 MB
#else
#error "Define RAM_SIZE"
#error "Define RAM_SIZE_MAX"
#endif
"ldr x0, [x2, x1, lsl #3] \n\t"
"br x0 \n"
@ -995,7 +995,7 @@ public:
Mov(x2, sizeof(Sh4RCB));
Sub(x2, x28, x2);
Add(x2, x2, sizeof(Sh4Context)); // x2 now points to FPCB
#if RAM_SIZE == 33554432
#if RAM_SIZE_MAX == 33554432
Ubfx(w1, w29, 1, 24);
#else
Ubfx(w1, w29, 1, 23);

6
core/rec-x64/rec_x64.cpp
View File

@ -66,14 +66,14 @@ static __attribute((used)) void end_slice()
#define STRINGIFY(x) #x
#define _S(x) STRINGIFY(x)
#if RAM_SIZE == 16*1024*1024
#if RAM_SIZE_MAX == 16*1024*1024
#define CPU_RUNNING 68157284
#define PC 68157256
#elif RAM_SIZE == 32*1024*1024
#elif RAM_SIZE_MAX == 32*1024*1024
#define CPU_RUNNING 135266148
#define PC 135266120
#else
#error RAM_SIZE unknown
#error RAM_SIZE_MAX unknown
#endif
#ifdef _WIN32

5
core/types.h
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@ -1004,3 +1004,8 @@ struct OnLoad
typedef void OnLoadFP();
OnLoad(OnLoadFP* fp) { fp(); }
};
#ifndef ARRAY_SIZE
#define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0]))
#endif