dynarec: flush fpu regs before FTRV
fixes issue with tokyo xtreme racer (x64) might need to flush before other ops
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@ -540,6 +540,15 @@ struct RegAlloc
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}
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else
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{
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if (op->op == shop_ftrv)
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{
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for (int sid = 0; sid < 16; sid++)
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{
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flush_span(reg_fr_0 + sid);
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flush_span(reg_xf_0 + sid);
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}
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}
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set<shil_param> reg_wt;
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set<shil_param> reg_rd;
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@ -1083,14 +1092,15 @@ struct RegAlloc
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if (spn->begining(current_opid) && spn->preload)
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{
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//printf("Op %d: Preloading r%d to %d\n",current_opid,spn->regstart,spn->nreg);
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if (spn->fpr)
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{
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//printf("Op %d: Preloading f%d to %d\n",current_opid,spn->regstart,spn->nregf);
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preload_fpu++;
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Preload_FPU(spn->regstart,spn->nregf);
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}
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else
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{
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//printf("Op %d: Preloading r%d to %d\n",current_opid,spn->regstart,spn->nreg);
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preload_gpr++;
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Preload(spn->regstart,spn->nreg);
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}
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@ -1106,14 +1116,15 @@ struct RegAlloc
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if (spn->ending(current_opid) && spn->writeback)
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{
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//printf("Op %d: Writing back r%d to %d\n",current_opid,spn->regstart,spn->nreg);
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if (spn->fpr)
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{
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//printf("Op %d: Writing back f%d from %d\n",current_opid,spn->regstart,spn->nregf);
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writeback_fpu++;
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Writeback_FPU(spn->regstart,spn->nregf);
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}
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else
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{
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//printf("Op %d: Writing back r%d from %d\n",current_opid,spn->regstart,spn->nreg);
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writeback_gpr++;
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Writeback(spn->regstart,spn->nreg);
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}
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@ -1145,4 +1156,4 @@ struct RegAlloc
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virtual void Preload_FPU(u32 reg,nregf_t nreg)=0;
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virtual void Writeback_FPU(u32 reg,nregf_t nreg)=0;
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};
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};
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