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Better logging

This commit is contained in:
Flyinghead 2018-10-20 19:38:21 +02:00
parent 9d327f3592
commit fb84df6665
5 changed files with 49 additions and 67 deletions
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6
core/hw/mem/_vmem.cpp
View File

@ -753,8 +753,6 @@ bool _vmem_reserve()
mem_b.size=RAM_SIZE;
mem_b.data=(u8*)ptr;
printf("A8\n");
//Area 4
//Area 5
//Area 6
@ -765,13 +763,11 @@ bool _vmem_reserve()
printf("vmem reserve: base: %08X, aram: %08x, vram: %08X, ram: %08X\n",virt_ram_base,aica_ram.data,vram.data,mem_b.data);
printf("Resetting mem\n");
aica_ram.Zero();
vram.Zero();
mem_b.Zero();
printf("Mem alloc successful!");
printf("Mem alloc successful!\n");
return virt_ram_base!=0;
}

34
core/hw/naomi/naomi.cpp
View File

@ -354,13 +354,13 @@ u32 _ReadMem_naomi(u32 Addr, u32 sz)
{
verify(sz!=1);
//printf("naomi?WTF? ReadMem: %X, %d\n", Addr, sz);
EMUERROR("naomi?WTF? ReadMem: %X, %d", Addr, sz);
return 1;
}
void _WriteMem_naomi(u32 Addr, u32 data, u32 sz)
{
//printf("naomi?WTF? WriteMem: %X <= %X, %d\n", Addr, data, sz);
EMUERROR("naomi?WTF? WriteMem: %X <= %X, %d", Addr, data, sz);
}
@ -427,16 +427,16 @@ u32 ReadMem_naomi(u32 Addr, u32 sz)
switch(Addr&255)
{
case 0x3c:
//printf("naomi GD? READ: %X, %d\n", Addr, sz);
EMUERROR("naomi GD? READ: %X, %d", Addr, sz);
return reg_dimm_3c | (NaomiDataRead ? 0 : -1); //pretend the board isn't there for the bios
case 0x40:
printf("naomi GD? READ: %X, %d\n", Addr, sz);
EMUERROR("naomi GD? READ: %X, %d", Addr, sz);
return reg_dimm_40;
case 0x44:
printf("naomi GD? READ: %X, %d\n", Addr, sz);
EMUERROR("naomi GD? READ: %X, %d", Addr, sz);
return reg_dimm_44;
case 0x48:
printf("naomi GD? READ: %X, %d\n", Addr, sz);
EMUERROR("naomi GD? READ: %X, %d", Addr, sz);
return reg_dimm_48;
//These are known to be valid on normal ROMs and DIMM board
@ -486,11 +486,11 @@ u32 ReadMem_naomi(u32 Addr, u32 sz)
return DmaOffset&0xFFFF;
case NAOMI_BOARDID_WRITE_addr&255:
printf("naomi ReadMem: %X, %d\n", Addr, sz);
EMUERROR("naomi ReadMem: %X, %d", Addr, sz);
return 1;
case 0x04C:
//printf("naomi GD? READ: %X, %d\n", Addr, sz);
EMUERROR("naomi GD? READ: %X, %d", Addr, sz);
return reg_dimm_4c;
case 0x18:
@ -500,7 +500,7 @@ u32 ReadMem_naomi(u32 Addr, u32 sz)
default: break;
}
//printf("naomi?WTF? ReadMem: %X, %d\n", Addr, sz);
EMUERROR("naomi?WTF? ReadMem: %X, %d", Addr, sz);
return 0;
}
@ -518,20 +518,20 @@ void WriteMem_naomi(u32 Addr, u32 data, u32 sz)
reg_dimm_4c|=1;*/
}
reg_dimm_3c=data;
printf("naomi GD? Write: %X <= %X, %d\n", Addr, data, sz);
EMUERROR("naomi GD? Write: %X <= %X, %d", Addr, data, sz);
return;
case 0x40:
reg_dimm_40=data;
printf("naomi GD? Write: %X <= %X, %d\n", Addr, data, sz);
EMUERROR("naomi GD? Write: %X <= %X, %d", Addr, data, sz);
return;
case 0x44:
reg_dimm_44=data;
printf("naomi GD? Write: %X <= %X, %d\n", Addr, data, sz);
EMUERROR("naomi GD? Write: %X <= %X, %d", Addr, data, sz);
return;
case 0x48:
reg_dimm_48=data;
printf("naomi GD? Write: %X <= %X, %d\n", Addr, data, sz);
EMUERROR("naomi GD? Write: %X <= %X, %d", Addr, data, sz);
return;
case 0x4C:
@ -548,7 +548,7 @@ void WriteMem_naomi(u32 Addr, u32 data, u32 sz)
naomi_process(reg_dimm_3c,reg_dimm_40,reg_dimm_44,reg_dimm_48);
}
reg_dimm_4c=data&~0x100;
printf("naomi GD? Write: %X <= %X, %d\n", Addr, data, sz);
EMUERROR("naomi GD? Write: %X <= %X, %d", Addr, data, sz);
return;
//These are known to be valid on normal ROMs and DIMM board
@ -563,7 +563,7 @@ void WriteMem_naomi(u32 Addr, u32 data, u32 sz)
return;
case NAOMI_ROM_DATA_addr&255:
printf("naomi WriteMem:Write to rom ? sure ? no , i dont think so %%) %X <= %X, %d\n", Addr, data, sz);
EMUERROR("naomi WriteMem:Write to rom ? sure ? no , i dont think so %%) %X <= %X, %d", Addr, data, sz);
return;
case NAOMI_DMA_OFFSETH_addr&255:
@ -605,12 +605,12 @@ void WriteMem_naomi(u32 Addr, u32 data, u32 sz)
//This should be valid
case NAOMI_BOARDID_READ_addr&255:
printf("naomi WriteMem: %X <= %X, %d\n", Addr, data, sz);
EMUERROR("naomi WriteMem: %X <= %X, %d", Addr, data, sz);
return;
default: break;
}
//printf("naomi?WTF? WriteMem: %X <= %X, %d\n", Addr, data, sz);
EMUERROR("naomi?WTF? WriteMem: %X <= %X, %d", Addr, data, sz);
}

4
core/hw/sh4/sh4_mem.cpp
View File

@ -259,7 +259,7 @@ void WriteMemBlock_nommu_ptr(u32 dst,u32* src,u32 size)
u32 dst_msk;
if (size % 4 != 0)
{
printf("WriteMem32_nommu: invalid size %d. Ignored\n", size);
EMUERROR("invalid size %d. Ignored", size);
return;
}
@ -324,7 +324,7 @@ u8* GetMemPtr(u32 Addr,u32 size)
case 6:
case 7:
default:
printf("Get MemPtr unsupported area : addr=0x%X\n",Addr);
EMUERROR("unsupported area : addr=0x%X",Addr);
return 0;
}
}

54
core/hw/sh4/sh4_mmr.cpp
View File

@ -28,17 +28,17 @@ Array<RegisterStruct> SCIF(10,true); //SCIF : 10 registers
u32 sh4io_read_noacc(u32 addr)
{
printf("sh4io: Invalid read access @@ %08X\n",addr);
EMUERROR("sh4io: Invalid read access @@ %08X",addr);
return 0;
}
void sh4io_write_noacc(u32 addr, u32 data)
{
printf("sh4io: Invalid write access @@ %08X %08X\n",addr,data);
EMUERROR("sh4io: Invalid write access @@ %08X %08X",addr,data);
//verify(false);
}
void sh4io_write_const(u32 addr, u32 data)
{
printf("sh4io: Const write ignored @@ %08X <- %08X\n",addr,data);
EMUERROR("sh4io: Const write ignored @@ %08X <- %08X",addr,data);
}
void sh4_rio_reg(Array<RegisterStruct>& arr, u32 addr, RegIO flags, u32 sz, RegReadAddrFP* rf, RegWriteAddrFP* wf)
@ -77,7 +77,7 @@ u32 sh4_rio_read(Array<RegisterStruct>& sb_regs, u32 addr)
#ifdef TRACE
if (offset & 3/*(size-1)*/) //4 is min align size
{
EMUERROR("Unalinged System Bus register read");
EMUERROR("Unaligned System Bus register read");
}
#endif
@ -190,22 +190,19 @@ T DYNACALL ReadMem_P4(u32 addr)
case 0xE1:
case 0xE2:
case 0xE3:
printf("Unhandled p4 read [Store queue] 0x%x\n",addr);
EMUERROR("Unhandled p4 read [Store queue] 0x%x",addr);
return 0;
break;
case 0xF0:
//printf("Unhandled p4 read [Instruction cache address array] 0x%x\n",addr);
return 0;
break;
case 0xF1:
//printf("Unhandled p4 read [Instruction cache data array] 0x%x\n",addr);
return 0;
break;
case 0xF2:
//printf("Unhandled p4 read [Instruction TLB address array] 0x%x\n",addr);
{
u32 entry=(addr>>8)&3;
return ITLB[entry].Address.reg_data | (ITLB[entry].Data.V<<8);
@ -213,7 +210,6 @@ T DYNACALL ReadMem_P4(u32 addr)
break;
case 0xF3:
//printf("Unhandled p4 read [Instruction TLB data arrays 1 and 2] 0x%x\n",addr);
{
u32 entry=(addr>>8)&3;
return ITLB[entry].Data.reg_data;
@ -232,12 +228,10 @@ T DYNACALL ReadMem_P4(u32 addr)
break;
case 0xF5:
//printf("Unhandled p4 read [Operand cache data array] 0x%x",addr);
return 0;
break;
case 0xF6:
//printf("Unhandled p4 read [Unified TLB address array] 0x%x\n",addr);
{
u32 entry=(addr>>8)&63;
u32 rv=UTLB[entry].Address.reg_data;
@ -248,7 +242,6 @@ T DYNACALL ReadMem_P4(u32 addr)
break;
case 0xF7:
//printf("Unhandled p4 read [Unified TLB data arrays 1 and 2] 0x%x\n",addr);
{
u32 entry=(addr>>8)&63;
return UTLB[entry].Data.reg_data;
@ -256,15 +249,15 @@ T DYNACALL ReadMem_P4(u32 addr)
break;
case 0xFF:
printf("Unhandled p4 read [area7] 0x%x\n",addr);
EMUERROR("Unhandled p4 read [area7] 0x%x",addr);
break;
default:
printf("Unhandled p4 read [Reserved] 0x%x\n",addr);
EMUERROR("Unhandled p4 read [Reserved] 0x%x",addr);
break;
}
EMUERROR2("Read from P4 not implemented - addr=%x",addr);
EMUERROR("Read from P4 not implemented - addr=%x",addr);
return 0;
}
@ -286,21 +279,18 @@ void DYNACALL WriteMem_P4(u32 addr,T data)
case 0xE1:
case 0xE2:
case 0xE3:
printf("Unhandled p4 Write [Store queue] 0x%x",addr);
EMUERROR("Unhandled p4 Write [Store queue] 0x%x",addr);
break;
case 0xF0:
//printf("Unhandled p4 Write [Instruction cache address array] 0x%x = %x\n",addr,data);
return;
break;
case 0xF1:
//printf("Unhandled p4 Write [Instruction cache data array] 0x%x = %x\n",addr,data);
return;
break;
case 0xF2:
//printf("Unhandled p4 Write [Instruction TLB address array] 0x%x = %x\n",addr,data);
{
u32 entry=(addr>>8)&3;
ITLB[entry].Address.reg_data=data & 0xFFFFFCFF;
@ -313,11 +303,10 @@ void DYNACALL WriteMem_P4(u32 addr,T data)
case 0xF3:
if (addr&0x800000)
{
printf("Unhandled p4 Write [Instruction TLB data array 2] 0x%x = %x\n",addr,data);
EMUERROR("Unhandled p4 Write [Instruction TLB data array 2] 0x%x = %x",addr,data);
}
else
{
//printf("Unhandled p4 Write [Instruction TLB data array 1] 0x%x = %x\n",addr,data);
u32 entry=(addr>>8)&3;
ITLB[entry].Data.reg_data=data;
ITLB_Sync(entry);
@ -346,7 +335,7 @@ void DYNACALL WriteMem_P4(u32 addr,T data)
if (addr&0x80)
{
#ifdef NO_MMU
printf("Unhandled p4 Write [Unified TLB address array, Associative Write] 0x%x = %x\n",addr,data);
EMUERROR("Unhandled p4 Write [Unified TLB address array, Associative Write] 0x%x = %x",addr,data);
#endif
CCN_PTEH_type t;
@ -393,11 +382,10 @@ void DYNACALL WriteMem_P4(u32 addr,T data)
case 0xF7:
if (addr&0x800000)
{
printf("Unhandled p4 Write [Unified TLB data array 2] 0x%x = %x\n",addr,data);
EMUERROR("Unhandled p4 Write [Unified TLB data array 2] 0x%x = %x",addr,data);
}
else
{
//printf("Unhandled p4 Write [Unified TLB data array 1] 0x%x = %x\n",addr,data);
u32 entry=(addr>>8)&63;
UTLB[entry].Data.reg_data=data;
UTLB_Sync(entry);
@ -406,11 +394,11 @@ void DYNACALL WriteMem_P4(u32 addr,T data)
break;
case 0xFF:
printf("Unhandled p4 Write [area7] 0x%x = %x\n",addr,data);
EMUERROR("Unhandled p4 Write [area7] 0x%x = %x",addr,data);
break;
default:
printf("Unhandled p4 Write [Reserved] 0x%x\n",addr);
EMUERROR("Unhandled p4 Write [Reserved] 0x%x",addr);
break;
}
@ -428,7 +416,7 @@ T DYNACALL ReadMem_sq(u32 addr)
{
if (sz!=4)
{
printf("Store Queue Error - only 4 byte read are possible[x%X]\n",addr);
EMUERROR("Store Queue Error - only 4 byte read are possible[x%X]",addr);
return 0xDE;
}
@ -443,7 +431,7 @@ template <u32 sz,class T>
void DYNACALL WriteMem_sq(u32 addr,T data)
{
if (sz!=4)
printf("Store Queue Error - only 4 byte writes are possible[x%X=0x%X]\n",addr,data);
EMUERROR("Store Queue Error - only 4 byte writes are possible[x%X=0x%X]",addr,data);
u32 united_offset=addr & 0x3C;
@ -816,13 +804,13 @@ T DYNACALL ReadMem_area7_OCR_T(u32 addr)
return (T)*(u32*)&OnChipRAM[addr&OnChipRAM_MASK];
else
{
printf("ReadMem_area7_OCR_T: template SZ is wrong = %d\n",sz);
EMUERROR("ReadMem_area7_OCR_T: template SZ is wrong = %d",sz);
return 0xDE;
}
}
else
{
printf("On Chip Ram Read, but OCR is disabled\n");
EMUERROR("On Chip Ram Read, but OCR is disabled");
return 0xDE;
}
}
@ -841,12 +829,12 @@ void DYNACALL WriteMem_area7_OCR_T(u32 addr,T data)
*(u32*)&OnChipRAM[addr&OnChipRAM_MASK]=data;
else
{
printf("WriteMem_area7_OCR_T: template SZ is wrong = %d\n",sz);
EMUERROR("WriteMem_area7_OCR_T: template SZ is wrong = %d",sz);
}
}
else
{
printf("On Chip Ram Write, but OCR is disabled\n");
EMUERROR("On Chip Ram Write, but OCR is disabled");
}
}
@ -958,4 +946,4 @@ void map_p4()
_vmem_map_block(sq_both,0xE3,0xE3,63);
map_area7(0xE0);
}
}

18
core/types.h
View File

@ -483,16 +483,14 @@ using namespace std;
//basic includes
#include "stdclass.h"
#define EMUERROR(x)( printf("Error in %s:" "%s" ":%d -> " x "\n", __FILE__,__FUNCTION__ ,__LINE__ ))
#define EMUERROR2(x,a)(printf("Error in %s:" "%s" ":%d -> " x "\n",__FILE__,__FUNCTION__,__LINE__,a))
#define EMUERROR3(x,a,b)(printf("Error in %s:" "%s" ":%d -> " x "\n",__FILE__,__FUNCTION__,__LINE__,a,b))
#define EMUERROR4(x,a,b,c)(printf("Error in %s:" "%s" ":%d -> " x "\n",__FILE__,__FUNCTION__,__LINE__,a,b,c))
#define EMUWARN(x)(printf( "Warning in %s:" "%s" ":%d -> " x "\n"),__FILE__,__FUNCTION__,__LINE__))
#define EMUWARN2(x,a)(printf( "Warning in %s:" "%s" ":%d -> " x "\n"),__FILE__,__FUNCTION__,__LINE__,a))
#define EMUWARN3(x,a,b)(printf( "Warning in %s:" "%s" ":%d -> " x "\n"),__FILE__,__FUNCTION__,__LINE__,a,b))
#define EMUWARN4(x,a,b,c)(printf("Warning in %s:" "%s" ":%d -> " x "\n"),__FILE__,__FUNCTION__,__LINE__,a,b,c))
#ifndef RELEASE
#define EMUERROR(format, ...) printf("Error in %s:%s:%d: " format "\n", __FILE__,__FUNCTION__ ,__LINE__, ##__VA_ARGS__)
#else
#define EMUERROR(format, ...)
#endif
#define EMUERROR2 EMUERROR
#define EMUERROR3 EMUERROR
#define EMUERROR4 EMUERROR
#ifndef NO_MMU
#define _X_x_X_MMU_VER_STR "/mmu"