d09d59007a
Arm64Emitter: Add a missing const specifier for an array table
2015-07-02 11:09:44 -04:00
afc3d30f5c
[AArch64] Implement BFI & UBFIZ in the emitter.
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Also fixes a bug in the UBFX instruction emitter. Naughty Naughty PPSSPP, not testing emitter functions you add.
2015-06-29 19:00:22 -05:00
5dc148159f
[AArch64] Implement {U, S}QXTN{,2}
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Also split out XTN to XTN and XTN2.
2015-06-13 23:16:17 -05:00
74b359e390
Arm64Emitter: Remove unused variable from EncodeLoadStoreRegisterOffset
2015-06-13 14:27:15 -04:00
3d2b116323
[AArch64] Implement a couple instructions in the emitter.
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Implements LD2R.
Implements LD1R/LD2R with post-indexing support.
Implements vector min/max instructions.
2015-06-09 18:10:56 -05:00
8ae12d8005
[AArch64] Add ASIMD LDR/STR with register offset
2015-06-07 19:53:05 -05:00
05b72c5d31
[AArch64] Upstream PPSSPP's emitter changes.
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Requires a minor change to in the JIT to make sure everything still works.
2015-06-07 19:50:21 -05:00
30ebb2459e
Set copyright year to when a file was created
2015-05-25 13:22:31 +02:00
cefcb0ace9
Update license headers to GPLv2+
2015-05-25 13:22:31 +02:00
f6511c3ba5
[AArch64] Add an assert to SMOV in the emitter.
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SMOV doesn't have an encoding for moving a 32bit element to a 32bit GPR.
One should use UMOV if they want that.
2015-03-08 12:29:45 -05:00
fbdee7b15f
[AArch64] Handle FPR island registers in a less dumb way.
2015-03-03 00:30:05 -06:00
f1a9db9bdc
[AArch64] Stop violating the AAPCS64 so much.
2015-03-02 11:21:15 -06:00
fad46729b0
[AArch64] Implemented paired pushing/popping for the VFP.
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A bit more efficient if we are only pushing two VFP registers.
We can probably be a bit more efficient in the future by mixing paired loadstores in to the other paths as well.
2015-03-02 06:27:47 -06:00
39e357d62d
[AArch64] Implement VFP loadstore paired in the emitter.
2015-03-02 06:27:17 -06:00
8b8310d28c
[AArch64] Optimize FPR pushing and popping.
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Previously on FPR pushing and popping we would do a single STR/LDR per quad FPR we wanted to push/pop.
In most of our cases when we are pushing and popping VFP registers they will be consecutive registers that will save more efficiently using the NEON
loadstores that can do up to four quad registers.
So this can potentially cutting instructions down to ~1/4th the amount of instructions if the registers are all consecutive.
On the Cortex-A57 this is basically just an icache improvement, but on the Nvidia Denver this may be optimized to be more efficient. Either way it's a
win.
2015-03-02 06:27:13 -06:00
120df4c688
[AArch64] Implement loadstore unscaled.
2015-02-16 22:00:43 -06:00
814aaaf538
[AArch64] Implement a couple of emitter instructions.
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These will be used with the vertex loader JIT recompiler.
2015-02-13 12:16:06 -06:00
20dae1f210
[AArch64] Fix a bunch of emitter asserts.
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Since I've added the msg handler. I found all these asserts that were backwards. So they were asserting on the correct arguments.
2015-02-13 12:16:05 -06:00
c340a324bc
Merge pull request #1947 from Sonicadvance1/AArch64_tu_tl_merge
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[AArch64] Implement TU/TL merging.
2015-01-25 23:07:32 -06:00
f24c466e7e
[AArch64] Fix AArch64 instruction encoding.
2015-01-25 17:26:18 -06:00
6470227a39
[AArch64] Minor fix in the UMULH/SMULH.
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These two instructions ignore the register encoded in to RA.
2015-01-22 18:08:49 -06:00
217c2c9d6a
[AArch64] Add some more scalar VFP ops to the emitter.
2015-01-20 16:34:32 -06:00
8d5947efac
[AArch64] Emitter improvements.
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Adds a bunch of new instructions to the emitter.
2015-01-18 16:25:40 -06:00
c511ee763a
[AArch64] Add the float emitter.
2015-01-08 19:55:31 -06:00
5a0133c478
[AArch64] Add a few more VFP register helpers.
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Renames Is128Bit to IsQuad to line up more with the other helpers.
2015-01-07 13:05:55 -06:00
0a23ca9461
[AArch64] Add MUL/MNEG instruction aliases to the emitter.
2015-01-07 13:03:01 -06:00
d2eaba5cb7
[AArch64] Minor MOVI2R improvement.
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Use the ZR for both input arguments in the case the immediate is the maximum immediate value.
This allows it to be aliased to MVN when disassembling.
2015-01-07 13:00:39 -06:00
8dba84dd7c
[AArch64] Fix 8 & 16 bit loadstore indexes.
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I wasn't bit shifting correctly for 8 and 16bit loadstores.
2015-01-07 12:58:37 -06:00
f4f59ea71e
[AArch64] Fix ADDS/SUBS emitter functions.
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These weren't emitting the flag bit. So they were regular ADD and SUB emitters.
2015-01-07 12:56:45 -06:00
d3c2e8fb0a
[AArch64] Improvements to the AArch64 emitter.
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Fixes issues with negative offsets in loadstore instructions.
Adds ADRP/ADR instructions.
Optimizes MOVI2R function to take advantage of ADRP on pointers, can change a 3 instruction operation down to one.
Adds GPR push/pop operations for ABI related things.
2014-12-20 19:35:52 -06:00
2c39d4044d
[AArch64] Add loadstore paired emitter instructions.
2014-12-02 21:08:34 -06:00
e9b09a4c9f
Arm(64)Emitter: Make some variables static
2014-11-25 23:27:48 -05:00
7608e3f11e
Add AArch64 emitter aliases for MOV and MVN.
2014-09-18 16:30:40 -05:00
17d31ecd6c
Fix AArch64 MOVI2R helper function.
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In the case of a zero immediate, it wouldn't generate code at all.
Also in the case of max u32/u64, use ORN to optimize it.
2014-09-12 05:45:10 -05:00
24f6c98a55
Add sign extending aliases to the ARM64Emitter.
2014-09-10 17:52:54 -05:00
bc331ee809
Common: Fix code styling in Arm64Emitter
2014-09-08 23:39:20 -04:00
f107b5e176
[AArch64-emitter] Initial work on a emitter for 64bit ARM.
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I've tested a few instruction encodings and am expecting most to work as long as one stays away from VFP/SIMD.
This implements mostly instructions to bring up an initial JIT with integer support.
This can be improved to allow ease of use functions in the future, dealing with the raw imms/immr encodings is probably the worst thing ever.
2014-09-06 20:13:44 -05:00
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