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bsnes/higan/sfc/chip/spc7110/spc7110.cpp

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Update to v088r07 release. byuu says: (r05 and r06 were save points between large core modifications) I would really appreciate extensive regression testing (especially around SuperFX, Cx4, ST018, DSP-n, ST-01n, NES, GB) at this point. The most critical core changes should be completed now. And it was an unbelievable amount of restructuring. Changelog: - SuperFX core moved to Processor::GSU - SNES::CPU core moved to Processor::R65816 - SNES::SMP core moved to Processor::SPC700 - NES::CPU core renamed to Processor::R6502 - use filestream to load RAM files from interface - save states store SHA256 instead of CRC32 (CRC32 usage removed entirely from bsnes) - nes/ -> fc/ and NES -> FC - snes/ -> sfc/ and SNES -> SFC - SuperFamicom::MappedRAM::copy uses stream instead of data+size - Linux port uses gcc-4.7 (still using only gcc-4.6 subset, so you can make a gcc-4.6 symlink for now if you like.) - all profiles and all targets compile and work properly All eight instruction set cores have been moved to processor/ now. Consistency's a wonderful thing. The last remnants of NES/SNES are now limited to target-ui code; and the nall/(system) folder names. I'm building with gcc-4.7 on my Linux box now because the resultant binaries are up to 20% faster (seriously) than gcc-4.6.
2012-04-29 06:16:44 +00:00
#include <sfc/sfc.hpp>
First version split into asnes and bsnes.
2010-08-09 13:28:56 +00:00
#define SPC7110_CPP
Update to v088r01 release. byuu says: - GB::CPU::Core -> Processor::LR35902 - Processor::LR35902 -> jump table to switch table - GB::LCD -> GB::PPU - static frequency for DMG (no multiplication on clock ticks) - GB::PPU::interface->videoRefresh() moved outside scheduler (use host thread) - namespace NES -> Famicom - namespace SNES -> SuperFamicom - namespace GB -> GameBoy - namespace GBA -> GameBoyAdvance - removed boot.rom writeout in GB::System
2012-04-26 10:51:13 +00:00
namespace SuperFamicom {
First version split into asnes and bsnes.
2010-08-09 13:28:56 +00:00
Update to v089r04 release. byuu says: Changelog: (SPC7110) - emulated $480b.d0 + $4807 deinterleave mode - cleaned up decompression core (I'd still like to wipe out those static variables, those are bad for save states.) - improved emulation of data port ($481a only increments, never reads) - improved emulation of RTC (block appropriate bits in the hour register based on 12/24h mode select; $4840 modes != 1 all disable the chip; added MDR; etc.)
2012-05-19 06:28:54 +00:00
#include "dcu.cpp"
Update to v089r03 release. byuu says: Substantial improvements to SPC7110 emulation. Added all of the findings from http://byuu.org/temp/spc7110-mmio.txt that I understood. I also completely rewrote the RTC. We only had about ~40% of the chip emulated before. Turns out there's cool stuff like spare RAM, calendar disable, 12-hour mode, IRQs, IRQ masking, duty cycles, etc. So I went ahead and emulated all of it. The upper bits on hour+ don't work as nocash described though, not sure what doc he was reading. The Epson RTC-4513 manual I have doesn't explain any of the registers. The new RTC core also ticks seconds based on the emulated clock, and not on the system clock. This is going to suck for people wanting to keep the in-game clock synced with their computer, who also abuse fast forward and save states. Fast forward makes the clock run faster, and save states will jump the clock to the time it was at when you took the save state. (It will keep track of the number of seconds between unloading the game and loading it again, so time passes normally there.) This is required, however, and how I'm going to rearrange all of the RTCs for all systems. Any other method can be detected by the game, and is thus not faithful emulation. To help with this, I'll probably make an RTC time tool so that you can adjust the time when the emulator isn't running, but I don't intend to bundle that into bsnes. New state format bit-packs the RTCRAM values, and it also uses a 64-bit timestamp. So it's 16 bytes now instead of 20 bytes. S-RTC will drop from 16 to 12 when it's done. The RTC busy flag timing needs to be refined with more hardware tests, there's a slim chance of the game hanging on save at the moment. The SPC7110 ALU delays are emulated now, too. They may not be perfectly accurate, but they get the basic gist down. The only hack that needs to be removed now is the decompression busy flag. That's ... not going to be fun. I also redid the mouse emulation. I was polling the mouse position multiple times per latch. So it should be a bit more precise now, I hope. I read it regardless of latch state, dunno if that's good or not.
2012-05-16 00:27:34 +00:00
#include "data.cpp"
#include "alu.cpp"
#include "serialization.cpp"
First version split into asnes and bsnes.
2010-08-09 13:28:56 +00:00
SPC7110 spc7110;
Update to v089r10 release. byuu says: Changelog: - Cydrak merged all three SPC7110 decompression routines into one, cuts the size in half - fixed masking of $4803.d7 and $4813.d7 - data port out of bounds accesses emulated correctly for app SPC7110 boards - all(?) data port $4810 reload cases now supported - basic timing for $4805-6 seeking; reworked delay timing to work better as well - fixed $480c.d7 flag (1 = ready, not busy) - AbsoluteInput returns -32768 if presentation window lacks focus and you don't always allow input
2012-05-31 12:27:46 +00:00
SPC7110::SPC7110() {
decompressor = new Decompressor(*this);
}
SPC7110::~SPC7110() {
delete decompressor;
}
Update to v089r03 release. byuu says: Substantial improvements to SPC7110 emulation. Added all of the findings from http://byuu.org/temp/spc7110-mmio.txt that I understood. I also completely rewrote the RTC. We only had about ~40% of the chip emulated before. Turns out there's cool stuff like spare RAM, calendar disable, 12-hour mode, IRQs, IRQ masking, duty cycles, etc. So I went ahead and emulated all of it. The upper bits on hour+ don't work as nocash described though, not sure what doc he was reading. The Epson RTC-4513 manual I have doesn't explain any of the registers. The new RTC core also ticks seconds based on the emulated clock, and not on the system clock. This is going to suck for people wanting to keep the in-game clock synced with their computer, who also abuse fast forward and save states. Fast forward makes the clock run faster, and save states will jump the clock to the time it was at when you took the save state. (It will keep track of the number of seconds between unloading the game and loading it again, so time passes normally there.) This is required, however, and how I'm going to rearrange all of the RTCs for all systems. Any other method can be detected by the game, and is thus not faithful emulation. To help with this, I'll probably make an RTC time tool so that you can adjust the time when the emulator isn't running, but I don't intend to bundle that into bsnes. New state format bit-packs the RTCRAM values, and it also uses a 64-bit timestamp. So it's 16 bytes now instead of 20 bytes. S-RTC will drop from 16 to 12 when it's done. The RTC busy flag timing needs to be refined with more hardware tests, there's a slim chance of the game hanging on save at the moment. The SPC7110 ALU delays are emulated now, too. They may not be perfectly accurate, but they get the basic gist down. The only hack that needs to be removed now is the decompression busy flag. That's ... not going to be fun. I also redid the mouse emulation. I was polling the mouse position multiple times per latch. So it should be a bit more precise now, I hope. I read it regardless of latch state, dunno if that's good or not.
2012-05-16 00:27:34 +00:00
void SPC7110::Enter() { spc7110.enter(); }
First version split into asnes and bsnes.
2010-08-09 13:28:56 +00:00
Update to v089r03 release. byuu says: Substantial improvements to SPC7110 emulation. Added all of the findings from http://byuu.org/temp/spc7110-mmio.txt that I understood. I also completely rewrote the RTC. We only had about ~40% of the chip emulated before. Turns out there's cool stuff like spare RAM, calendar disable, 12-hour mode, IRQs, IRQ masking, duty cycles, etc. So I went ahead and emulated all of it. The upper bits on hour+ don't work as nocash described though, not sure what doc he was reading. The Epson RTC-4513 manual I have doesn't explain any of the registers. The new RTC core also ticks seconds based on the emulated clock, and not on the system clock. This is going to suck for people wanting to keep the in-game clock synced with their computer, who also abuse fast forward and save states. Fast forward makes the clock run faster, and save states will jump the clock to the time it was at when you took the save state. (It will keep track of the number of seconds between unloading the game and loading it again, so time passes normally there.) This is required, however, and how I'm going to rearrange all of the RTCs for all systems. Any other method can be detected by the game, and is thus not faithful emulation. To help with this, I'll probably make an RTC time tool so that you can adjust the time when the emulator isn't running, but I don't intend to bundle that into bsnes. New state format bit-packs the RTCRAM values, and it also uses a 64-bit timestamp. So it's 16 bytes now instead of 20 bytes. S-RTC will drop from 16 to 12 when it's done. The RTC busy flag timing needs to be refined with more hardware tests, there's a slim chance of the game hanging on save at the moment. The SPC7110 ALU delays are emulated now, too. They may not be perfectly accurate, but they get the basic gist down. The only hack that needs to be removed now is the decompression busy flag. That's ... not going to be fun. I also redid the mouse emulation. I was polling the mouse position multiple times per latch. So it should be a bit more precise now, I hope. I read it regardless of latch state, dunno if that's good or not.
2012-05-16 00:27:34 +00:00
void SPC7110::enter() {
while(true) {
if(scheduler.sync == Scheduler::SynchronizeMode::All) {
scheduler.exit(Scheduler::ExitReason::SynchronizeEvent);
}
Update to v089r10 release. byuu says: Changelog: - Cydrak merged all three SPC7110 decompression routines into one, cuts the size in half - fixed masking of $4803.d7 and $4813.d7 - data port out of bounds accesses emulated correctly for app SPC7110 boards - all(?) data port $4810 reload cases now supported - basic timing for $4805-6 seeking; reworked delay timing to work better as well - fixed $480c.d7 flag (1 = ready, not busy) - AbsoluteInput returns -32768 if presentation window lacks focus and you don't always allow input
2012-05-31 12:27:46 +00:00
if(dcu_pending) { dcu_pending = 0; dcu_begin_transfer(); }
if(mul_pending) { mul_pending = 0; alu_multiply(); }
if(div_pending) { div_pending = 0; alu_divide(); }
Update to v089r03 release. byuu says: Substantial improvements to SPC7110 emulation. Added all of the findings from http://byuu.org/temp/spc7110-mmio.txt that I understood. I also completely rewrote the RTC. We only had about ~40% of the chip emulated before. Turns out there's cool stuff like spare RAM, calendar disable, 12-hour mode, IRQs, IRQ masking, duty cycles, etc. So I went ahead and emulated all of it. The upper bits on hour+ don't work as nocash described though, not sure what doc he was reading. The Epson RTC-4513 manual I have doesn't explain any of the registers. The new RTC core also ticks seconds based on the emulated clock, and not on the system clock. This is going to suck for people wanting to keep the in-game clock synced with their computer, who also abuse fast forward and save states. Fast forward makes the clock run faster, and save states will jump the clock to the time it was at when you took the save state. (It will keep track of the number of seconds between unloading the game and loading it again, so time passes normally there.) This is required, however, and how I'm going to rearrange all of the RTCs for all systems. Any other method can be detected by the game, and is thus not faithful emulation. To help with this, I'll probably make an RTC time tool so that you can adjust the time when the emulator isn't running, but I don't intend to bundle that into bsnes. New state format bit-packs the RTCRAM values, and it also uses a 64-bit timestamp. So it's 16 bytes now instead of 20 bytes. S-RTC will drop from 16 to 12 when it's done. The RTC busy flag timing needs to be refined with more hardware tests, there's a slim chance of the game hanging on save at the moment. The SPC7110 ALU delays are emulated now, too. They may not be perfectly accurate, but they get the basic gist down. The only hack that needs to be removed now is the decompression busy flag. That's ... not going to be fun. I also redid the mouse emulation. I was polling the mouse position multiple times per latch. So it should be a bit more precise now, I hope. I read it regardless of latch state, dunno if that's good or not.
2012-05-16 00:27:34 +00:00
Update to v089r10 release. byuu says: Changelog: - Cydrak merged all three SPC7110 decompression routines into one, cuts the size in half - fixed masking of $4803.d7 and $4813.d7 - data port out of bounds accesses emulated correctly for app SPC7110 boards - all(?) data port $4810 reload cases now supported - basic timing for $4805-6 seeking; reworked delay timing to work better as well - fixed $480c.d7 flag (1 = ready, not busy) - AbsoluteInput returns -32768 if presentation window lacks focus and you don't always allow input
2012-05-31 12:27:46 +00:00
add_clocks(1);
Update to v089r03 release. byuu says: Substantial improvements to SPC7110 emulation. Added all of the findings from http://byuu.org/temp/spc7110-mmio.txt that I understood. I also completely rewrote the RTC. We only had about ~40% of the chip emulated before. Turns out there's cool stuff like spare RAM, calendar disable, 12-hour mode, IRQs, IRQ masking, duty cycles, etc. So I went ahead and emulated all of it. The upper bits on hour+ don't work as nocash described though, not sure what doc he was reading. The Epson RTC-4513 manual I have doesn't explain any of the registers. The new RTC core also ticks seconds based on the emulated clock, and not on the system clock. This is going to suck for people wanting to keep the in-game clock synced with their computer, who also abuse fast forward and save states. Fast forward makes the clock run faster, and save states will jump the clock to the time it was at when you took the save state. (It will keep track of the number of seconds between unloading the game and loading it again, so time passes normally there.) This is required, however, and how I'm going to rearrange all of the RTCs for all systems. Any other method can be detected by the game, and is thus not faithful emulation. To help with this, I'll probably make an RTC time tool so that you can adjust the time when the emulator isn't running, but I don't intend to bundle that into bsnes. New state format bit-packs the RTCRAM values, and it also uses a 64-bit timestamp. So it's 16 bytes now instead of 20 bytes. S-RTC will drop from 16 to 12 when it's done. The RTC busy flag timing needs to be refined with more hardware tests, there's a slim chance of the game hanging on save at the moment. The SPC7110 ALU delays are emulated now, too. They may not be perfectly accurate, but they get the basic gist down. The only hack that needs to be removed now is the decompression busy flag. That's ... not going to be fun. I also redid the mouse emulation. I was polling the mouse position multiple times per latch. So it should be a bit more precise now, I hope. I read it regardless of latch state, dunno if that's good or not.
2012-05-16 00:27:34 +00:00
}
}
First version split into asnes and bsnes.
2010-08-09 13:28:56 +00:00
Update to v089r10 release. byuu says: Changelog: - Cydrak merged all three SPC7110 decompression routines into one, cuts the size in half - fixed masking of $4803.d7 and $4813.d7 - data port out of bounds accesses emulated correctly for app SPC7110 boards - all(?) data port $4810 reload cases now supported - basic timing for $4805-6 seeking; reworked delay timing to work better as well - fixed $480c.d7 flag (1 = ready, not busy) - AbsoluteInput returns -32768 if presentation window lacks focus and you don't always allow input
2012-05-31 12:27:46 +00:00
void SPC7110::add_clocks(unsigned clocks) {
step(clocks);
synchronize_cpu();
}
Update to v074r10 release. byuu says: Major WIP, countless changes. I really went to town on cleaning up the source today with all kinds of new ideas. I'll post the ones I remember, use diff -ru to get the rest. What I like the most is my new within template: template<unsigned lo, unsigned hi> alwaysinline bool within(unsigned addr) { static const unsigned mask = ~(hi ^ lo); return (addr & mask) == lo; } Before, you would see code like this: if((addr & 0xe0e000) == 0x206000) { //$20-3f:6000-7fff The comment is basically necessary, and you have to trust that the mask is right, or do the math yourself. Now, it looks like this: if(within<0x20, 0x3f, 0x6000, 0x7fff>(addr)) { That's the same as within<0x206000, 0x3f7fff>, I just made an SNES-variant to more closely simulate my XML mapping style: 20-3f:6000-7fff. Now obviously this has limitations, it only works in base-2 and it can't manage some tricky edge cases like (addr & 0x408000) == 0x008000 for 00-3f|80-bf:8000-ffff. But for the most part, I'll be using this where I can. The Game Boy is fully ported over to it (via the MBCs), but the SNES only has the BS-X town cartridge moved over so far. SuperFX and SA-1 at the very least could benefit. Next up, since the memory map is now static, there's really no reason to remap the entire thing at power-on and reset. So it is now set up at cartridge load and that's it. I moved the CPU/PPU/WRAM mapping out of memory.cpp and into their respective processors. A bit of duplication only because there are multiple processor cores for the different profiles, but I'm not worried about that. This is also going to be necessary to fix the debugger. Next, Coprocessor::enable() actually does what I initially intended it to now: it is called once to turn a chip on after cartridge load. It's not called on power cycle anymore. This should help fix power-cycle on my serial simulation code, and was needed to map the bus exactly one time. Although most stuff is mapped through XML, some chips still need some manual hooks for monitoring and such (eg S-DD1.) Next, I've started killing off memory::, it was initially an over-reaction to the question of where to put APURAM (in the SMP or DSP?). The idea was to have this namespace that contained all memory for everything. But it was very annoying and tedious, and various chips ignored the convention anyway like ST-0011 RAM, which couldn't work anyway since it is natively uint16 and not uint8. Cx4 will need 24-bit RAM eventually, too. There's 8->24-bit functions in there now, because the HLE code is hideous. So far, all the cartridge.cpp memory:: types have been destroyed. memory::cartrom, memory::cartram become cartridge.rom and cartridge.ram. memory::cartrtc was moved into the SRTC and SPC7110 classes directly. memory::bsxflash was moved into BSXFlash. memory::bsxram and memory::bsxpram were moved into BSXCartridge (the town cartridge). memory::st[AB](rom|ram) were moved into a new area, snes/chip/sufamiturbo. The snes/chip moniker really doesn't work so well, since it also has base units, and the serial communications stuff which is through the controller port, but oh well, now it also has the base structure for the Sufami Turbo cartridge too. So now we have sufamiturbo.slotA.rom, sufamiturbo.slotB.ram, etc. Next, the ST-0010/ST-0011 actually save the data RAM to disk. This wasn't at all compatible with my old system, and I didn't want to keep adding memory types to check inside the main UI cartridge RAM loading and saving routines. So I built a NonVolatileRAM vector inside SNES::Cartridge, and any chip that has memory it wants to save and load from disk can append onto it : data, size, id ("srm", "rtc", "nec", etc) and slot (0 = cartridge, 1 = slot A, 2 = slot B) To load and save memory, we just do a simple: foreach(memory, SNES::cartridge.nvram) load/saveMemory(memory). As a result, you can now keep your save games in F1 Race of Champions II and Hayazashi Nidan Morita Shougi. Technically I think Metal Combat should work this way as well, having the RAM being part of the chip itself, but for now that chip just writes directly into cartridge.ram, so it also technically saves to disk for now. To avoid a potential conflict with a manipulated memory map, BS-X SRAM and PSRAM are now .bss and .bsp, and not .srm and .psr. Honestly I don't like .srm as an extension either, but it doesn't bother me enough to break save RAM compatibility with other emulators, so don't worry about that changing. I finally killed off MappedRAM initializing size to ~0 (-1U). A size of zero means there is no memory there just the same. This was an old holdover for handling MMIO mapping, if I recall correctly. Something about a size of zero on MMIO-Memory objects causing it to wrap the address, so ~0 would let it map direct addresses ... or something. Whatever, that's not needed at all anymore. BSXBase becomes BSXSatellaview, and I've defaulted the device to being attached since it won't affect non-BSX games anyway. Eventually the GUI needs to make that an option. BSXCart becomes BSXCartridge. BSXFlash remains unchanged. I probably need to make Coprocessor::disable() functions now to free up memory on unload, but it shouldn't hurt anything the way it is. libsnes is most definitely broken to all hell and back now, and the debugger is still shot. I suppose we'll need some tricky code to work with the old ID system, and we'll need to add some more IDs for the new memory types.
2011-01-24 08:59:45 +00:00
void SPC7110::init() {
}
Update to v075 release. byuu says: This release brings improved Super Game Boy emulation, the final SHA256 hashes for the DSP-(1,1B,2,3,4) and ST-(0010,0011) coprocessors, user interface improvements, and major internal code restructuring. Changelog (since v074): - completely rewrote memory sub-system to support 1-byte granularity in XML mapping - removed Memory inheritance and MMIO class completely, any address can be mapped to any function now - SuperFX: removed SuperFXBus : Bus, now implemented manually - SA-1: removed SA1Bus : Bus, now implemented manually - entire bus mapping is now static, happens once on cartridge load - as a result, read/write handlers now handle MMC mapping; slower average case, far faster worst case - namespace memory is no more, RAM arrays are stored inside the chips they are owned by now - GameBoy: improved CPU HALT emulation, fixes Zelda: Link's Awakening scrolling - GameBoy: added serial emulation (cannot connect to another GB yet), fixes Shin Megami Tensei - Devichil - GameBoy: improved LCD STAT emulation, fixes Sagaia - ui: added fullscreen support (F11 key), video settings allows for three scale settings - ui: fixed brightness, contrast, gamma, audio volume, input frequency values on program startup - ui: since Qt is dead, config file becomes bsnes.cfg once again - Super Game Boy: you can now load the BIOS without a game inserted to see a pretty white box - ui-gameboy: can be built without SNES components now - libsnes: now a UI target, compile with 'make ui=ui-libsnes' - libsnes: added WRAM, APURAM, VRAM, OAM, CGRAM access (cheat search, etc) - source: removed launcher/, as the Qt port is now gone - source: Makefile restructuring to better support new ui targets - source: lots of other internal code cleanup work
2011-01-27 08:52:34 +00:00
void SPC7110::load() {
Update to v074r10 release. byuu says: Major WIP, countless changes. I really went to town on cleaning up the source today with all kinds of new ideas. I'll post the ones I remember, use diff -ru to get the rest. What I like the most is my new within template: template<unsigned lo, unsigned hi> alwaysinline bool within(unsigned addr) { static const unsigned mask = ~(hi ^ lo); return (addr & mask) == lo; } Before, you would see code like this: if((addr & 0xe0e000) == 0x206000) { //$20-3f:6000-7fff The comment is basically necessary, and you have to trust that the mask is right, or do the math yourself. Now, it looks like this: if(within<0x20, 0x3f, 0x6000, 0x7fff>(addr)) { That's the same as within<0x206000, 0x3f7fff>, I just made an SNES-variant to more closely simulate my XML mapping style: 20-3f:6000-7fff. Now obviously this has limitations, it only works in base-2 and it can't manage some tricky edge cases like (addr & 0x408000) == 0x008000 for 00-3f|80-bf:8000-ffff. But for the most part, I'll be using this where I can. The Game Boy is fully ported over to it (via the MBCs), but the SNES only has the BS-X town cartridge moved over so far. SuperFX and SA-1 at the very least could benefit. Next up, since the memory map is now static, there's really no reason to remap the entire thing at power-on and reset. So it is now set up at cartridge load and that's it. I moved the CPU/PPU/WRAM mapping out of memory.cpp and into their respective processors. A bit of duplication only because there are multiple processor cores for the different profiles, but I'm not worried about that. This is also going to be necessary to fix the debugger. Next, Coprocessor::enable() actually does what I initially intended it to now: it is called once to turn a chip on after cartridge load. It's not called on power cycle anymore. This should help fix power-cycle on my serial simulation code, and was needed to map the bus exactly one time. Although most stuff is mapped through XML, some chips still need some manual hooks for monitoring and such (eg S-DD1.) Next, I've started killing off memory::, it was initially an over-reaction to the question of where to put APURAM (in the SMP or DSP?). The idea was to have this namespace that contained all memory for everything. But it was very annoying and tedious, and various chips ignored the convention anyway like ST-0011 RAM, which couldn't work anyway since it is natively uint16 and not uint8. Cx4 will need 24-bit RAM eventually, too. There's 8->24-bit functions in there now, because the HLE code is hideous. So far, all the cartridge.cpp memory:: types have been destroyed. memory::cartrom, memory::cartram become cartridge.rom and cartridge.ram. memory::cartrtc was moved into the SRTC and SPC7110 classes directly. memory::bsxflash was moved into BSXFlash. memory::bsxram and memory::bsxpram were moved into BSXCartridge (the town cartridge). memory::st[AB](rom|ram) were moved into a new area, snes/chip/sufamiturbo. The snes/chip moniker really doesn't work so well, since it also has base units, and the serial communications stuff which is through the controller port, but oh well, now it also has the base structure for the Sufami Turbo cartridge too. So now we have sufamiturbo.slotA.rom, sufamiturbo.slotB.ram, etc. Next, the ST-0010/ST-0011 actually save the data RAM to disk. This wasn't at all compatible with my old system, and I didn't want to keep adding memory types to check inside the main UI cartridge RAM loading and saving routines. So I built a NonVolatileRAM vector inside SNES::Cartridge, and any chip that has memory it wants to save and load from disk can append onto it : data, size, id ("srm", "rtc", "nec", etc) and slot (0 = cartridge, 1 = slot A, 2 = slot B) To load and save memory, we just do a simple: foreach(memory, SNES::cartridge.nvram) load/saveMemory(memory). As a result, you can now keep your save games in F1 Race of Champions II and Hayazashi Nidan Morita Shougi. Technically I think Metal Combat should work this way as well, having the RAM being part of the chip itself, but for now that chip just writes directly into cartridge.ram, so it also technically saves to disk for now. To avoid a potential conflict with a manipulated memory map, BS-X SRAM and PSRAM are now .bss and .bsp, and not .srm and .psr. Honestly I don't like .srm as an extension either, but it doesn't bother me enough to break save RAM compatibility with other emulators, so don't worry about that changing. I finally killed off MappedRAM initializing size to ~0 (-1U). A size of zero means there is no memory there just the same. This was an old holdover for handling MMIO mapping, if I recall correctly. Something about a size of zero on MMIO-Memory objects causing it to wrap the address, so ~0 would let it map direct addresses ... or something. Whatever, that's not needed at all anymore. BSXBase becomes BSXSatellaview, and I've defaulted the device to being attached since it won't affect non-BSX games anyway. Eventually the GUI needs to make that an option. BSXCart becomes BSXCartridge. BSXFlash remains unchanged. I probably need to make Coprocessor::disable() functions now to free up memory on unload, but it shouldn't hurt anything the way it is. libsnes is most definitely broken to all hell and back now, and the debugger is still shot. I suppose we'll need some tricky code to work with the old ID system, and we'll need to add some more IDs for the new memory types.
2011-01-24 08:59:45 +00:00
}
First version split into asnes and bsnes.
2010-08-09 13:28:56 +00:00
Update to v075 release. byuu says: This release brings improved Super Game Boy emulation, the final SHA256 hashes for the DSP-(1,1B,2,3,4) and ST-(0010,0011) coprocessors, user interface improvements, and major internal code restructuring. Changelog (since v074): - completely rewrote memory sub-system to support 1-byte granularity in XML mapping - removed Memory inheritance and MMIO class completely, any address can be mapped to any function now - SuperFX: removed SuperFXBus : Bus, now implemented manually - SA-1: removed SA1Bus : Bus, now implemented manually - entire bus mapping is now static, happens once on cartridge load - as a result, read/write handlers now handle MMC mapping; slower average case, far faster worst case - namespace memory is no more, RAM arrays are stored inside the chips they are owned by now - GameBoy: improved CPU HALT emulation, fixes Zelda: Link's Awakening scrolling - GameBoy: added serial emulation (cannot connect to another GB yet), fixes Shin Megami Tensei - Devichil - GameBoy: improved LCD STAT emulation, fixes Sagaia - ui: added fullscreen support (F11 key), video settings allows for three scale settings - ui: fixed brightness, contrast, gamma, audio volume, input frequency values on program startup - ui: since Qt is dead, config file becomes bsnes.cfg once again - Super Game Boy: you can now load the BIOS without a game inserted to see a pretty white box - ui-gameboy: can be built without SNES components now - libsnes: now a UI target, compile with 'make ui=ui-libsnes' - libsnes: added WRAM, APURAM, VRAM, OAM, CGRAM access (cheat search, etc) - source: removed launcher/, as the Qt port is now gone - source: Makefile restructuring to better support new ui targets - source: lots of other internal code cleanup work
2011-01-27 08:52:34 +00:00
void SPC7110::unload() {
Update to v089r15 release. byuu says: Changelog: - SuperFX has its own ROM and RAM - Cx4 has its own ROM - SPC7110 has its own ProgramROM, DataROM and RAM - OBC1 has its own RAM - BsxCartridge has its own ROM, RAM and PSRAM - mapping changes to accommodate the above
2012-07-09 11:40:23 +00:00
prom.reset();
drom.reset();
ram.reset();
Update to v075 release. byuu says: This release brings improved Super Game Boy emulation, the final SHA256 hashes for the DSP-(1,1B,2,3,4) and ST-(0010,0011) coprocessors, user interface improvements, and major internal code restructuring. Changelog (since v074): - completely rewrote memory sub-system to support 1-byte granularity in XML mapping - removed Memory inheritance and MMIO class completely, any address can be mapped to any function now - SuperFX: removed SuperFXBus : Bus, now implemented manually - SA-1: removed SA1Bus : Bus, now implemented manually - entire bus mapping is now static, happens once on cartridge load - as a result, read/write handlers now handle MMC mapping; slower average case, far faster worst case - namespace memory is no more, RAM arrays are stored inside the chips they are owned by now - GameBoy: improved CPU HALT emulation, fixes Zelda: Link's Awakening scrolling - GameBoy: added serial emulation (cannot connect to another GB yet), fixes Shin Megami Tensei - Devichil - GameBoy: improved LCD STAT emulation, fixes Sagaia - ui: added fullscreen support (F11 key), video settings allows for three scale settings - ui: fixed brightness, contrast, gamma, audio volume, input frequency values on program startup - ui: since Qt is dead, config file becomes bsnes.cfg once again - Super Game Boy: you can now load the BIOS without a game inserted to see a pretty white box - ui-gameboy: can be built without SNES components now - libsnes: now a UI target, compile with 'make ui=ui-libsnes' - libsnes: added WRAM, APURAM, VRAM, OAM, CGRAM access (cheat search, etc) - source: removed launcher/, as the Qt port is now gone - source: Makefile restructuring to better support new ui targets - source: lots of other internal code cleanup work
2011-01-27 08:52:34 +00:00
}
First version split into asnes and bsnes.
2010-08-09 13:28:56 +00:00
void SPC7110::power() {
}
void SPC7110::reset() {
Update to v089r10 release. byuu says: Changelog: - Cydrak merged all three SPC7110 decompression routines into one, cuts the size in half - fixed masking of $4803.d7 and $4813.d7 - data port out of bounds accesses emulated correctly for app SPC7110 boards - all(?) data port $4810 reload cases now supported - basic timing for $4805-6 seeking; reworked delay timing to work better as well - fixed $480c.d7 flag (1 = ready, not busy) - AbsoluteInput returns -32768 if presentation window lacks focus and you don't always allow input
2012-05-31 12:27:46 +00:00
create(SPC7110::Enter, 21477272);
Update to v089r03 release. byuu says: Substantial improvements to SPC7110 emulation. Added all of the findings from http://byuu.org/temp/spc7110-mmio.txt that I understood. I also completely rewrote the RTC. We only had about ~40% of the chip emulated before. Turns out there's cool stuff like spare RAM, calendar disable, 12-hour mode, IRQs, IRQ masking, duty cycles, etc. So I went ahead and emulated all of it. The upper bits on hour+ don't work as nocash described though, not sure what doc he was reading. The Epson RTC-4513 manual I have doesn't explain any of the registers. The new RTC core also ticks seconds based on the emulated clock, and not on the system clock. This is going to suck for people wanting to keep the in-game clock synced with their computer, who also abuse fast forward and save states. Fast forward makes the clock run faster, and save states will jump the clock to the time it was at when you took the save state. (It will keep track of the number of seconds between unloading the game and loading it again, so time passes normally there.) This is required, however, and how I'm going to rearrange all of the RTCs for all systems. Any other method can be detected by the game, and is thus not faithful emulation. To help with this, I'll probably make an RTC time tool so that you can adjust the time when the emulator isn't running, but I don't intend to bundle that into bsnes. New state format bit-packs the RTCRAM values, and it also uses a 64-bit timestamp. So it's 16 bytes now instead of 20 bytes. S-RTC will drop from 16 to 12 when it's done. The RTC busy flag timing needs to be refined with more hardware tests, there's a slim chance of the game hanging on save at the moment. The SPC7110 ALU delays are emulated now, too. They may not be perfectly accurate, but they get the basic gist down. The only hack that needs to be removed now is the decompression busy flag. That's ... not going to be fun. I also redid the mouse emulation. I was polling the mouse position multiple times per latch. So it should be a bit more precise now, I hope. I read it regardless of latch state, dunno if that's good or not.
2012-05-16 00:27:34 +00:00
First version split into asnes and bsnes.
2010-08-09 13:28:56 +00:00
r4801 = 0x00;
r4802 = 0x00;
r4803 = 0x00;
r4804 = 0x00;
r4805 = 0x00;
r4806 = 0x00;
r4807 = 0x00;
r4809 = 0x00;
r480a = 0x00;
r480b = 0x00;
r480c = 0x00;
Update to v089r10 release. byuu says: Changelog: - Cydrak merged all three SPC7110 decompression routines into one, cuts the size in half - fixed masking of $4803.d7 and $4813.d7 - data port out of bounds accesses emulated correctly for app SPC7110 boards - all(?) data port $4810 reload cases now supported - basic timing for $4805-6 seeking; reworked delay timing to work better as well - fixed $480c.d7 flag (1 = ready, not busy) - AbsoluteInput returns -32768 if presentation window lacks focus and you don't always allow input
2012-05-31 12:27:46 +00:00
dcu_pending = 0;
Update to v089r04 release. byuu says: Changelog: (SPC7110) - emulated $480b.d0 + $4807 deinterleave mode - cleaned up decompression core (I'd still like to wipe out those static variables, those are bad for save states.) - improved emulation of data port ($481a only increments, never reads) - improved emulation of RTC (block appropriate bits in the hour register based on 12/24h mode select; $4840 modes != 1 all disable the chip; added MDR; etc.)
2012-05-19 06:28:54 +00:00
dcu_mode = 0;
dcu_addr = 0;
First version split into asnes and bsnes.
2010-08-09 13:28:56 +00:00
Update to v089r03 release. byuu says: Substantial improvements to SPC7110 emulation. Added all of the findings from http://byuu.org/temp/spc7110-mmio.txt that I understood. I also completely rewrote the RTC. We only had about ~40% of the chip emulated before. Turns out there's cool stuff like spare RAM, calendar disable, 12-hour mode, IRQs, IRQ masking, duty cycles, etc. So I went ahead and emulated all of it. The upper bits on hour+ don't work as nocash described though, not sure what doc he was reading. The Epson RTC-4513 manual I have doesn't explain any of the registers. The new RTC core also ticks seconds based on the emulated clock, and not on the system clock. This is going to suck for people wanting to keep the in-game clock synced with their computer, who also abuse fast forward and save states. Fast forward makes the clock run faster, and save states will jump the clock to the time it was at when you took the save state. (It will keep track of the number of seconds between unloading the game and loading it again, so time passes normally there.) This is required, however, and how I'm going to rearrange all of the RTCs for all systems. Any other method can be detected by the game, and is thus not faithful emulation. To help with this, I'll probably make an RTC time tool so that you can adjust the time when the emulator isn't running, but I don't intend to bundle that into bsnes. New state format bit-packs the RTCRAM values, and it also uses a 64-bit timestamp. So it's 16 bytes now instead of 20 bytes. S-RTC will drop from 16 to 12 when it's done. The RTC busy flag timing needs to be refined with more hardware tests, there's a slim chance of the game hanging on save at the moment. The SPC7110 ALU delays are emulated now, too. They may not be perfectly accurate, but they get the basic gist down. The only hack that needs to be removed now is the decompression busy flag. That's ... not going to be fun. I also redid the mouse emulation. I was polling the mouse position multiple times per latch. So it should be a bit more precise now, I hope. I read it regardless of latch state, dunno if that's good or not.
2012-05-16 00:27:34 +00:00
r4810 = 0x00;
First version split into asnes and bsnes.
2010-08-09 13:28:56 +00:00
r4811 = 0x00;
r4812 = 0x00;
r4813 = 0x00;
r4814 = 0x00;
r4815 = 0x00;
r4816 = 0x00;
r4817 = 0x00;
r4818 = 0x00;
Update to v089r03 release. byuu says: Substantial improvements to SPC7110 emulation. Added all of the findings from http://byuu.org/temp/spc7110-mmio.txt that I understood. I also completely rewrote the RTC. We only had about ~40% of the chip emulated before. Turns out there's cool stuff like spare RAM, calendar disable, 12-hour mode, IRQs, IRQ masking, duty cycles, etc. So I went ahead and emulated all of it. The upper bits on hour+ don't work as nocash described though, not sure what doc he was reading. The Epson RTC-4513 manual I have doesn't explain any of the registers. The new RTC core also ticks seconds based on the emulated clock, and not on the system clock. This is going to suck for people wanting to keep the in-game clock synced with their computer, who also abuse fast forward and save states. Fast forward makes the clock run faster, and save states will jump the clock to the time it was at when you took the save state. (It will keep track of the number of seconds between unloading the game and loading it again, so time passes normally there.) This is required, however, and how I'm going to rearrange all of the RTCs for all systems. Any other method can be detected by the game, and is thus not faithful emulation. To help with this, I'll probably make an RTC time tool so that you can adjust the time when the emulator isn't running, but I don't intend to bundle that into bsnes. New state format bit-packs the RTCRAM values, and it also uses a 64-bit timestamp. So it's 16 bytes now instead of 20 bytes. S-RTC will drop from 16 to 12 when it's done. The RTC busy flag timing needs to be refined with more hardware tests, there's a slim chance of the game hanging on save at the moment. The SPC7110 ALU delays are emulated now, too. They may not be perfectly accurate, but they get the basic gist down. The only hack that needs to be removed now is the decompression busy flag. That's ... not going to be fun. I also redid the mouse emulation. I was polling the mouse position multiple times per latch. So it should be a bit more precise now, I hope. I read it regardless of latch state, dunno if that's good or not.
2012-05-16 00:27:34 +00:00
r481a = 0x00;
First version split into asnes and bsnes.
2010-08-09 13:28:56 +00:00
r4820 = 0x00;
r4821 = 0x00;
r4822 = 0x00;
r4823 = 0x00;
r4824 = 0x00;
r4825 = 0x00;
r4826 = 0x00;
r4827 = 0x00;
r4828 = 0x00;
r4829 = 0x00;
r482a = 0x00;
r482b = 0x00;
r482c = 0x00;
r482d = 0x00;
r482e = 0x00;
r482f = 0x00;
Update to v089r10 release. byuu says: Changelog: - Cydrak merged all three SPC7110 decompression routines into one, cuts the size in half - fixed masking of $4803.d7 and $4813.d7 - data port out of bounds accesses emulated correctly for app SPC7110 boards - all(?) data port $4810 reload cases now supported - basic timing for $4805-6 seeking; reworked delay timing to work better as well - fixed $480c.d7 flag (1 = ready, not busy) - AbsoluteInput returns -32768 if presentation window lacks focus and you don't always allow input
2012-05-31 12:27:46 +00:00
mul_pending = 0;
div_pending = 0;
Update to v089r03 release. byuu says: Substantial improvements to SPC7110 emulation. Added all of the findings from http://byuu.org/temp/spc7110-mmio.txt that I understood. I also completely rewrote the RTC. We only had about ~40% of the chip emulated before. Turns out there's cool stuff like spare RAM, calendar disable, 12-hour mode, IRQs, IRQ masking, duty cycles, etc. So I went ahead and emulated all of it. The upper bits on hour+ don't work as nocash described though, not sure what doc he was reading. The Epson RTC-4513 manual I have doesn't explain any of the registers. The new RTC core also ticks seconds based on the emulated clock, and not on the system clock. This is going to suck for people wanting to keep the in-game clock synced with their computer, who also abuse fast forward and save states. Fast forward makes the clock run faster, and save states will jump the clock to the time it was at when you took the save state. (It will keep track of the number of seconds between unloading the game and loading it again, so time passes normally there.) This is required, however, and how I'm going to rearrange all of the RTCs for all systems. Any other method can be detected by the game, and is thus not faithful emulation. To help with this, I'll probably make an RTC time tool so that you can adjust the time when the emulator isn't running, but I don't intend to bundle that into bsnes. New state format bit-packs the RTCRAM values, and it also uses a 64-bit timestamp. So it's 16 bytes now instead of 20 bytes. S-RTC will drop from 16 to 12 when it's done. The RTC busy flag timing needs to be refined with more hardware tests, there's a slim chance of the game hanging on save at the moment. The SPC7110 ALU delays are emulated now, too. They may not be perfectly accurate, but they get the basic gist down. The only hack that needs to be removed now is the decompression busy flag. That's ... not going to be fun. I also redid the mouse emulation. I was polling the mouse position multiple times per latch. So it should be a bit more precise now, I hope. I read it regardless of latch state, dunno if that's good or not.
2012-05-16 00:27:34 +00:00
First version split into asnes and bsnes.
2010-08-09 13:28:56 +00:00
r4830 = 0x00;
Update to v089r02 release. (r01 was not posted to the WIP thread) byuu says: r01 changelog: - major improvements to SPC7110 MCU (memory controller unit) - revised SPC7110 memory map to reflect aforementioned improvements - added "Toggle Tracer" hotkey to target-ethos (only works for SFC so far, I plan to use this as a lightweight laevateinn for FEoEZ) r02 changelog: - quick fix: SRAM is mapped to 00-3f|80-bf:6000-7fff - quick fix: $4830.d7 is SRAM chip enable, not SRAM write enable. Reads return 0x00 when this bit is clear
2012-05-14 13:32:55 +00:00
r4831 = 0x00;
r4832 = 0x01;
r4833 = 0x02;
First version split into asnes and bsnes.
2010-08-09 13:28:56 +00:00
r4834 = 0x00;
}
Update to v089r16 release. byuu says: Changelog: - eliminated <mmio>, <mcu> tags [they are merged to their parent nodes now] - added <ram name= size=> tag to EpsonRTC, SharpRTC - added <firmware> tag to DSP-n, ST-01n, ST-018, Cx4 - interface->path(0) now returns the system folder, which can be used for storage now - as a fun proof-of-concept, I've simulated SNES warm power cycles by saving and loading work RAM (same effect if you instantly swapped carts) - long-term, I'm not sure how I want to do this. The power menu option makes no sense with warm RAM - I like the idea of decaying RAM based on timestamp from last play; and power can just force the timestamp to 0 (which will corrupt all RAM) - Interface::firmware is gone. The cores now load firmware inside their boot up routines - you now get a message on the screen if the emulator can't find firmware, should help with "I just get a black screen" messages I'd like to start preparing for a v090 release. I think we're almost there now. Have to update nall/cartridge and purify to handle XML changes first.
2012-07-15 09:47:35 +00:00
uint8 SPC7110::read(unsigned addr) {
Update to v089r03 release. byuu says: Substantial improvements to SPC7110 emulation. Added all of the findings from http://byuu.org/temp/spc7110-mmio.txt that I understood. I also completely rewrote the RTC. We only had about ~40% of the chip emulated before. Turns out there's cool stuff like spare RAM, calendar disable, 12-hour mode, IRQs, IRQ masking, duty cycles, etc. So I went ahead and emulated all of it. The upper bits on hour+ don't work as nocash described though, not sure what doc he was reading. The Epson RTC-4513 manual I have doesn't explain any of the registers. The new RTC core also ticks seconds based on the emulated clock, and not on the system clock. This is going to suck for people wanting to keep the in-game clock synced with their computer, who also abuse fast forward and save states. Fast forward makes the clock run faster, and save states will jump the clock to the time it was at when you took the save state. (It will keep track of the number of seconds between unloading the game and loading it again, so time passes normally there.) This is required, however, and how I'm going to rearrange all of the RTCs for all systems. Any other method can be detected by the game, and is thus not faithful emulation. To help with this, I'll probably make an RTC time tool so that you can adjust the time when the emulator isn't running, but I don't intend to bundle that into bsnes. New state format bit-packs the RTCRAM values, and it also uses a 64-bit timestamp. So it's 16 bytes now instead of 20 bytes. S-RTC will drop from 16 to 12 when it's done. The RTC busy flag timing needs to be refined with more hardware tests, there's a slim chance of the game hanging on save at the moment. The SPC7110 ALU delays are emulated now, too. They may not be perfectly accurate, but they get the basic gist down. The only hack that needs to be removed now is the decompression busy flag. That's ... not going to be fun. I also redid the mouse emulation. I was polling the mouse position multiple times per latch. So it should be a bit more precise now, I hope. I read it regardless of latch state, dunno if that's good or not.
2012-05-16 00:27:34 +00:00
cpu.synchronize_coprocessors();
Update to v089r16 release. byuu says: Changelog: - eliminated <mmio>, <mcu> tags [they are merged to their parent nodes now] - added <ram name= size=> tag to EpsonRTC, SharpRTC - added <firmware> tag to DSP-n, ST-01n, ST-018, Cx4 - interface->path(0) now returns the system folder, which can be used for storage now - as a fun proof-of-concept, I've simulated SNES warm power cycles by saving and loading work RAM (same effect if you instantly swapped carts) - long-term, I'm not sure how I want to do this. The power menu option makes no sense with warm RAM - I like the idea of decaying RAM based on timestamp from last play; and power can just force the timestamp to 0 (which will corrupt all RAM) - Interface::firmware is gone. The cores now load firmware inside their boot up routines - you now get a message on the screen if the emulator can't find firmware, should help with "I just get a black screen" messages I'd like to start preparing for a v090 release. I think we're almost there now. Have to update nall/cartridge and purify to handle XML changes first.
2012-07-15 09:47:35 +00:00
if((addr & 0xff0000) == 0x500000) addr = 0x4800;
Update to v089r09 release. byuu says: Changelog: - SPC7110 data port emulation greatly improved - SPC7110 $480b.d1 emulated (but $4805-4806 does not work right for mode 2 decompression yet) - MSU1 audio output will be muted when the S-DSP FLG ($6c).d6 (mute) flag is set - MSU1 will read filenames from manifest now (defaults to msu1.rom and track-#.pcm if missing ... for now) - bugfixes with MSU1 load state and track seek (and $4804 was wrapping into $4805 to change the track#) - Link coprocessor removed (it was meant for ST018 HLE, which never happened) Notes for things I forgot but need to address: - $4813 needs to be uint7 for the set_data_offset() to not allow reading A23 as set ever (or we can mask) - AbsoluteInput when window doesn't have focus should return -32768, not 0 - need to support input ID lists that aren't linear (0-7), but arbitrary (0,1,6,7 or whatever)
2012-05-29 12:20:46 +00:00
addr = 0x4800 | (addr & 0x3f);
First version split into asnes and bsnes.
2010-08-09 13:28:56 +00:00
switch(addr) {
Update to v089r02 release. (r01 was not posted to the WIP thread) byuu says: r01 changelog: - major improvements to SPC7110 MCU (memory controller unit) - revised SPC7110 memory map to reflect aforementioned improvements - added "Toggle Tracer" hotkey to target-ethos (only works for SFC so far, I plan to use this as a lightweight laevateinn for FEoEZ) r02 changelog: - quick fix: SRAM is mapped to 00-3f|80-bf:6000-7fff - quick fix: $4830.d7 is SRAM chip enable, not SRAM write enable. Reads return 0x00 when this bit is clear
2012-05-14 13:32:55 +00:00
//==================
//decompression unit
//==================
First version split into asnes and bsnes.
2010-08-09 13:28:56 +00:00
Update to v089r02 release. (r01 was not posted to the WIP thread) byuu says: r01 changelog: - major improvements to SPC7110 MCU (memory controller unit) - revised SPC7110 memory map to reflect aforementioned improvements - added "Toggle Tracer" hotkey to target-ethos (only works for SFC so far, I plan to use this as a lightweight laevateinn for FEoEZ) r02 changelog: - quick fix: SRAM is mapped to 00-3f|80-bf:6000-7fff - quick fix: $4830.d7 is SRAM chip enable, not SRAM write enable. Reads return 0x00 when this bit is clear
2012-05-14 13:32:55 +00:00
case 0x4800: {
Update to v089r03 release. byuu says: Substantial improvements to SPC7110 emulation. Added all of the findings from http://byuu.org/temp/spc7110-mmio.txt that I understood. I also completely rewrote the RTC. We only had about ~40% of the chip emulated before. Turns out there's cool stuff like spare RAM, calendar disable, 12-hour mode, IRQs, IRQ masking, duty cycles, etc. So I went ahead and emulated all of it. The upper bits on hour+ don't work as nocash described though, not sure what doc he was reading. The Epson RTC-4513 manual I have doesn't explain any of the registers. The new RTC core also ticks seconds based on the emulated clock, and not on the system clock. This is going to suck for people wanting to keep the in-game clock synced with their computer, who also abuse fast forward and save states. Fast forward makes the clock run faster, and save states will jump the clock to the time it was at when you took the save state. (It will keep track of the number of seconds between unloading the game and loading it again, so time passes normally there.) This is required, however, and how I'm going to rearrange all of the RTCs for all systems. Any other method can be detected by the game, and is thus not faithful emulation. To help with this, I'll probably make an RTC time tool so that you can adjust the time when the emulator isn't running, but I don't intend to bundle that into bsnes. New state format bit-packs the RTCRAM values, and it also uses a 64-bit timestamp. So it's 16 bytes now instead of 20 bytes. S-RTC will drop from 16 to 12 when it's done. The RTC busy flag timing needs to be refined with more hardware tests, there's a slim chance of the game hanging on save at the moment. The SPC7110 ALU delays are emulated now, too. They may not be perfectly accurate, but they get the basic gist down. The only hack that needs to be removed now is the decompression busy flag. That's ... not going to be fun. I also redid the mouse emulation. I was polling the mouse position multiple times per latch. So it should be a bit more precise now, I hope. I read it regardless of latch state, dunno if that's good or not.
2012-05-16 00:27:34 +00:00
uint16 counter = r4809 | r480a << 8;
Update to v089r02 release. (r01 was not posted to the WIP thread) byuu says: r01 changelog: - major improvements to SPC7110 MCU (memory controller unit) - revised SPC7110 memory map to reflect aforementioned improvements - added "Toggle Tracer" hotkey to target-ethos (only works for SFC so far, I plan to use this as a lightweight laevateinn for FEoEZ) r02 changelog: - quick fix: SRAM is mapped to 00-3f|80-bf:6000-7fff - quick fix: $4830.d7 is SRAM chip enable, not SRAM write enable. Reads return 0x00 when this bit is clear
2012-05-14 13:32:55 +00:00
counter--;
Update to v089r04 release. byuu says: Changelog: (SPC7110) - emulated $480b.d0 + $4807 deinterleave mode - cleaned up decompression core (I'd still like to wipe out those static variables, those are bad for save states.) - improved emulation of data port ($481a only increments, never reads) - improved emulation of RTC (block appropriate bits in the hour register based on 12/24h mode select; $4840 modes != 1 all disable the chip; added MDR; etc.)
2012-05-19 06:28:54 +00:00
r4809 = counter >> 0;
Update to v089r02 release. (r01 was not posted to the WIP thread) byuu says: r01 changelog: - major improvements to SPC7110 MCU (memory controller unit) - revised SPC7110 memory map to reflect aforementioned improvements - added "Toggle Tracer" hotkey to target-ethos (only works for SFC so far, I plan to use this as a lightweight laevateinn for FEoEZ) r02 changelog: - quick fix: SRAM is mapped to 00-3f|80-bf:6000-7fff - quick fix: $4830.d7 is SRAM chip enable, not SRAM write enable. Reads return 0x00 when this bit is clear
2012-05-14 13:32:55 +00:00
r480a = counter >> 8;
Update to v089r04 release. byuu says: Changelog: (SPC7110) - emulated $480b.d0 + $4807 deinterleave mode - cleaned up decompression core (I'd still like to wipe out those static variables, those are bad for save states.) - improved emulation of data port ($481a only increments, never reads) - improved emulation of RTC (block appropriate bits in the hour register based on 12/24h mode select; $4840 modes != 1 all disable the chip; added MDR; etc.)
2012-05-19 06:28:54 +00:00
return dcu_read();
Update to v089r02 release. (r01 was not posted to the WIP thread) byuu says: r01 changelog: - major improvements to SPC7110 MCU (memory controller unit) - revised SPC7110 memory map to reflect aforementioned improvements - added "Toggle Tracer" hotkey to target-ethos (only works for SFC so far, I plan to use this as a lightweight laevateinn for FEoEZ) r02 changelog: - quick fix: SRAM is mapped to 00-3f|80-bf:6000-7fff - quick fix: $4830.d7 is SRAM chip enable, not SRAM write enable. Reads return 0x00 when this bit is clear
2012-05-14 13:32:55 +00:00
}
case 0x4801: return r4801;
case 0x4802: return r4802;
case 0x4803: return r4803;
case 0x4804: return r4804;
case 0x4805: return r4805;
case 0x4806: return r4806;
case 0x4807: return r4807;
Update to v089r03 release. byuu says: Substantial improvements to SPC7110 emulation. Added all of the findings from http://byuu.org/temp/spc7110-mmio.txt that I understood. I also completely rewrote the RTC. We only had about ~40% of the chip emulated before. Turns out there's cool stuff like spare RAM, calendar disable, 12-hour mode, IRQs, IRQ masking, duty cycles, etc. So I went ahead and emulated all of it. The upper bits on hour+ don't work as nocash described though, not sure what doc he was reading. The Epson RTC-4513 manual I have doesn't explain any of the registers. The new RTC core also ticks seconds based on the emulated clock, and not on the system clock. This is going to suck for people wanting to keep the in-game clock synced with their computer, who also abuse fast forward and save states. Fast forward makes the clock run faster, and save states will jump the clock to the time it was at when you took the save state. (It will keep track of the number of seconds between unloading the game and loading it again, so time passes normally there.) This is required, however, and how I'm going to rearrange all of the RTCs for all systems. Any other method can be detected by the game, and is thus not faithful emulation. To help with this, I'll probably make an RTC time tool so that you can adjust the time when the emulator isn't running, but I don't intend to bundle that into bsnes. New state format bit-packs the RTCRAM values, and it also uses a 64-bit timestamp. So it's 16 bytes now instead of 20 bytes. S-RTC will drop from 16 to 12 when it's done. The RTC busy flag timing needs to be refined with more hardware tests, there's a slim chance of the game hanging on save at the moment. The SPC7110 ALU delays are emulated now, too. They may not be perfectly accurate, but they get the basic gist down. The only hack that needs to be removed now is the decompression busy flag. That's ... not going to be fun. I also redid the mouse emulation. I was polling the mouse position multiple times per latch. So it should be a bit more precise now, I hope. I read it regardless of latch state, dunno if that's good or not.
2012-05-16 00:27:34 +00:00
case 0x4808: return 0x00;
Update to v089r02 release. (r01 was not posted to the WIP thread) byuu says: r01 changelog: - major improvements to SPC7110 MCU (memory controller unit) - revised SPC7110 memory map to reflect aforementioned improvements - added "Toggle Tracer" hotkey to target-ethos (only works for SFC so far, I plan to use this as a lightweight laevateinn for FEoEZ) r02 changelog: - quick fix: SRAM is mapped to 00-3f|80-bf:6000-7fff - quick fix: $4830.d7 is SRAM chip enable, not SRAM write enable. Reads return 0x00 when this bit is clear
2012-05-14 13:32:55 +00:00
case 0x4809: return r4809;
case 0x480a: return r480a;
case 0x480b: return r480b;
Update to v089r10 release. byuu says: Changelog: - Cydrak merged all three SPC7110 decompression routines into one, cuts the size in half - fixed masking of $4803.d7 and $4813.d7 - data port out of bounds accesses emulated correctly for app SPC7110 boards - all(?) data port $4810 reload cases now supported - basic timing for $4805-6 seeking; reworked delay timing to work better as well - fixed $480c.d7 flag (1 = ready, not busy) - AbsoluteInput returns -32768 if presentation window lacks focus and you don't always allow input
2012-05-31 12:27:46 +00:00
case 0x480c: return r480c;
First version split into asnes and bsnes.
2010-08-09 13:28:56 +00:00
Update to v089r02 release. (r01 was not posted to the WIP thread) byuu says: r01 changelog: - major improvements to SPC7110 MCU (memory controller unit) - revised SPC7110 memory map to reflect aforementioned improvements - added "Toggle Tracer" hotkey to target-ethos (only works for SFC so far, I plan to use this as a lightweight laevateinn for FEoEZ) r02 changelog: - quick fix: SRAM is mapped to 00-3f|80-bf:6000-7fff - quick fix: $4830.d7 is SRAM chip enable, not SRAM write enable. Reads return 0x00 when this bit is clear
2012-05-14 13:32:55 +00:00
//==============
//data port unit
//==============
First version split into asnes and bsnes.
2010-08-09 13:28:56 +00:00
Update to v089r02 release. (r01 was not posted to the WIP thread) byuu says: r01 changelog: - major improvements to SPC7110 MCU (memory controller unit) - revised SPC7110 memory map to reflect aforementioned improvements - added "Toggle Tracer" hotkey to target-ethos (only works for SFC so far, I plan to use this as a lightweight laevateinn for FEoEZ) r02 changelog: - quick fix: SRAM is mapped to 00-3f|80-bf:6000-7fff - quick fix: $4830.d7 is SRAM chip enable, not SRAM write enable. Reads return 0x00 when this bit is clear
2012-05-14 13:32:55 +00:00
case 0x4810: {
Update to v089r03 release. byuu says: Substantial improvements to SPC7110 emulation. Added all of the findings from http://byuu.org/temp/spc7110-mmio.txt that I understood. I also completely rewrote the RTC. We only had about ~40% of the chip emulated before. Turns out there's cool stuff like spare RAM, calendar disable, 12-hour mode, IRQs, IRQ masking, duty cycles, etc. So I went ahead and emulated all of it. The upper bits on hour+ don't work as nocash described though, not sure what doc he was reading. The Epson RTC-4513 manual I have doesn't explain any of the registers. The new RTC core also ticks seconds based on the emulated clock, and not on the system clock. This is going to suck for people wanting to keep the in-game clock synced with their computer, who also abuse fast forward and save states. Fast forward makes the clock run faster, and save states will jump the clock to the time it was at when you took the save state. (It will keep track of the number of seconds between unloading the game and loading it again, so time passes normally there.) This is required, however, and how I'm going to rearrange all of the RTCs for all systems. Any other method can be detected by the game, and is thus not faithful emulation. To help with this, I'll probably make an RTC time tool so that you can adjust the time when the emulator isn't running, but I don't intend to bundle that into bsnes. New state format bit-packs the RTCRAM values, and it also uses a 64-bit timestamp. So it's 16 bytes now instead of 20 bytes. S-RTC will drop from 16 to 12 when it's done. The RTC busy flag timing needs to be refined with more hardware tests, there's a slim chance of the game hanging on save at the moment. The SPC7110 ALU delays are emulated now, too. They may not be perfectly accurate, but they get the basic gist down. The only hack that needs to be removed now is the decompression busy flag. That's ... not going to be fun. I also redid the mouse emulation. I was polling the mouse position multiple times per latch. So it should be a bit more precise now, I hope. I read it regardless of latch state, dunno if that's good or not.
2012-05-16 00:27:34 +00:00
uint8 data = r4810;
Update to v089r09 release. byuu says: Changelog: - SPC7110 data port emulation greatly improved - SPC7110 $480b.d1 emulated (but $4805-4806 does not work right for mode 2 decompression yet) - MSU1 audio output will be muted when the S-DSP FLG ($6c).d6 (mute) flag is set - MSU1 will read filenames from manifest now (defaults to msu1.rom and track-#.pcm if missing ... for now) - bugfixes with MSU1 load state and track seek (and $4804 was wrapping into $4805 to change the track#) - Link coprocessor removed (it was meant for ST018 HLE, which never happened) Notes for things I forgot but need to address: - $4813 needs to be uint7 for the set_data_offset() to not allow reading A23 as set ever (or we can mask) - AbsoluteInput when window doesn't have focus should return -32768, not 0 - need to support input ID lists that aren't linear (0-7), but arbitrary (0,1,6,7 or whatever)
2012-05-29 12:20:46 +00:00
data_port_increment_4810();
Update to v089r02 release. (r01 was not posted to the WIP thread) byuu says: r01 changelog: - major improvements to SPC7110 MCU (memory controller unit) - revised SPC7110 memory map to reflect aforementioned improvements - added "Toggle Tracer" hotkey to target-ethos (only works for SFC so far, I plan to use this as a lightweight laevateinn for FEoEZ) r02 changelog: - quick fix: SRAM is mapped to 00-3f|80-bf:6000-7fff - quick fix: $4830.d7 is SRAM chip enable, not SRAM write enable. Reads return 0x00 when this bit is clear
2012-05-14 13:32:55 +00:00
return data;
}
case 0x4811: return r4811;
case 0x4812: return r4812;
case 0x4813: return r4813;
case 0x4814: return r4814;
case 0x4815: return r4815;
case 0x4816: return r4816;
case 0x4817: return r4817;
case 0x4818: return r4818;
case 0x481a: {
Update to v089r09 release. byuu says: Changelog: - SPC7110 data port emulation greatly improved - SPC7110 $480b.d1 emulated (but $4805-4806 does not work right for mode 2 decompression yet) - MSU1 audio output will be muted when the S-DSP FLG ($6c).d6 (mute) flag is set - MSU1 will read filenames from manifest now (defaults to msu1.rom and track-#.pcm if missing ... for now) - bugfixes with MSU1 load state and track seek (and $4804 was wrapping into $4805 to change the track#) - Link coprocessor removed (it was meant for ST018 HLE, which never happened) Notes for things I forgot but need to address: - $4813 needs to be uint7 for the set_data_offset() to not allow reading A23 as set ever (or we can mask) - AbsoluteInput when window doesn't have focus should return -32768, not 0 - need to support input ID lists that aren't linear (0-7), but arbitrary (0,1,6,7 or whatever)
2012-05-29 12:20:46 +00:00
data_port_increment_481a();
Update to v089r04 release. byuu says: Changelog: (SPC7110) - emulated $480b.d0 + $4807 deinterleave mode - cleaned up decompression core (I'd still like to wipe out those static variables, those are bad for save states.) - improved emulation of data port ($481a only increments, never reads) - improved emulation of RTC (block appropriate bits in the hour register based on 12/24h mode select; $4840 modes != 1 all disable the chip; added MDR; etc.)
2012-05-19 06:28:54 +00:00
return 0x00;
Update to v089r02 release. (r01 was not posted to the WIP thread) byuu says: r01 changelog: - major improvements to SPC7110 MCU (memory controller unit) - revised SPC7110 memory map to reflect aforementioned improvements - added "Toggle Tracer" hotkey to target-ethos (only works for SFC so far, I plan to use this as a lightweight laevateinn for FEoEZ) r02 changelog: - quick fix: SRAM is mapped to 00-3f|80-bf:6000-7fff - quick fix: $4830.d7 is SRAM chip enable, not SRAM write enable. Reads return 0x00 when this bit is clear
2012-05-14 13:32:55 +00:00
}
First version split into asnes and bsnes.
2010-08-09 13:28:56 +00:00
Update to v089r09 release. byuu says: Changelog: - SPC7110 data port emulation greatly improved - SPC7110 $480b.d1 emulated (but $4805-4806 does not work right for mode 2 decompression yet) - MSU1 audio output will be muted when the S-DSP FLG ($6c).d6 (mute) flag is set - MSU1 will read filenames from manifest now (defaults to msu1.rom and track-#.pcm if missing ... for now) - bugfixes with MSU1 load state and track seek (and $4804 was wrapping into $4805 to change the track#) - Link coprocessor removed (it was meant for ST018 HLE, which never happened) Notes for things I forgot but need to address: - $4813 needs to be uint7 for the set_data_offset() to not allow reading A23 as set ever (or we can mask) - AbsoluteInput when window doesn't have focus should return -32768, not 0 - need to support input ID lists that aren't linear (0-7), but arbitrary (0,1,6,7 or whatever)
2012-05-29 12:20:46 +00:00
//=====================
//arithmetic logic unit
//=====================
Update to v089r02 release. (r01 was not posted to the WIP thread) byuu says: r01 changelog: - major improvements to SPC7110 MCU (memory controller unit) - revised SPC7110 memory map to reflect aforementioned improvements - added "Toggle Tracer" hotkey to target-ethos (only works for SFC so far, I plan to use this as a lightweight laevateinn for FEoEZ) r02 changelog: - quick fix: SRAM is mapped to 00-3f|80-bf:6000-7fff - quick fix: $4830.d7 is SRAM chip enable, not SRAM write enable. Reads return 0x00 when this bit is clear
2012-05-14 13:32:55 +00:00
case 0x4820: return r4820;
case 0x4821: return r4821;
case 0x4822: return r4822;
case 0x4823: return r4823;
case 0x4824: return r4824;
case 0x4825: return r4825;
case 0x4826: return r4826;
case 0x4827: return r4827;
case 0x4828: return r4828;
case 0x4829: return r4829;
case 0x482a: return r482a;
case 0x482b: return r482b;
case 0x482c: return r482c;
case 0x482d: return r482d;
case 0x482e: return r482e;
Update to v089r03 release. byuu says: Substantial improvements to SPC7110 emulation. Added all of the findings from http://byuu.org/temp/spc7110-mmio.txt that I understood. I also completely rewrote the RTC. We only had about ~40% of the chip emulated before. Turns out there's cool stuff like spare RAM, calendar disable, 12-hour mode, IRQs, IRQ masking, duty cycles, etc. So I went ahead and emulated all of it. The upper bits on hour+ don't work as nocash described though, not sure what doc he was reading. The Epson RTC-4513 manual I have doesn't explain any of the registers. The new RTC core also ticks seconds based on the emulated clock, and not on the system clock. This is going to suck for people wanting to keep the in-game clock synced with their computer, who also abuse fast forward and save states. Fast forward makes the clock run faster, and save states will jump the clock to the time it was at when you took the save state. (It will keep track of the number of seconds between unloading the game and loading it again, so time passes normally there.) This is required, however, and how I'm going to rearrange all of the RTCs for all systems. Any other method can be detected by the game, and is thus not faithful emulation. To help with this, I'll probably make an RTC time tool so that you can adjust the time when the emulator isn't running, but I don't intend to bundle that into bsnes. New state format bit-packs the RTCRAM values, and it also uses a 64-bit timestamp. So it's 16 bytes now instead of 20 bytes. S-RTC will drop from 16 to 12 when it's done. The RTC busy flag timing needs to be refined with more hardware tests, there's a slim chance of the game hanging on save at the moment. The SPC7110 ALU delays are emulated now, too. They may not be perfectly accurate, but they get the basic gist down. The only hack that needs to be removed now is the decompression busy flag. That's ... not going to be fun. I also redid the mouse emulation. I was polling the mouse position multiple times per latch. So it should be a bit more precise now, I hope. I read it regardless of latch state, dunno if that's good or not.
2012-05-16 00:27:34 +00:00
case 0x482f: return r482f;
First version split into asnes and bsnes.
2010-08-09 13:28:56 +00:00
Update to v089r02 release. (r01 was not posted to the WIP thread) byuu says: r01 changelog: - major improvements to SPC7110 MCU (memory controller unit) - revised SPC7110 memory map to reflect aforementioned improvements - added "Toggle Tracer" hotkey to target-ethos (only works for SFC so far, I plan to use this as a lightweight laevateinn for FEoEZ) r02 changelog: - quick fix: SRAM is mapped to 00-3f|80-bf:6000-7fff - quick fix: $4830.d7 is SRAM chip enable, not SRAM write enable. Reads return 0x00 when this bit is clear
2012-05-14 13:32:55 +00:00
//===================
Update to v089r09 release. byuu says: Changelog: - SPC7110 data port emulation greatly improved - SPC7110 $480b.d1 emulated (but $4805-4806 does not work right for mode 2 decompression yet) - MSU1 audio output will be muted when the S-DSP FLG ($6c).d6 (mute) flag is set - MSU1 will read filenames from manifest now (defaults to msu1.rom and track-#.pcm if missing ... for now) - bugfixes with MSU1 load state and track seek (and $4804 was wrapping into $4805 to change the track#) - Link coprocessor removed (it was meant for ST018 HLE, which never happened) Notes for things I forgot but need to address: - $4813 needs to be uint7 for the set_data_offset() to not allow reading A23 as set ever (or we can mask) - AbsoluteInput when window doesn't have focus should return -32768, not 0 - need to support input ID lists that aren't linear (0-7), but arbitrary (0,1,6,7 or whatever)
2012-05-29 12:20:46 +00:00
//memory control unit
Update to v089r02 release. (r01 was not posted to the WIP thread) byuu says: r01 changelog: - major improvements to SPC7110 MCU (memory controller unit) - revised SPC7110 memory map to reflect aforementioned improvements - added "Toggle Tracer" hotkey to target-ethos (only works for SFC so far, I plan to use this as a lightweight laevateinn for FEoEZ) r02 changelog: - quick fix: SRAM is mapped to 00-3f|80-bf:6000-7fff - quick fix: $4830.d7 is SRAM chip enable, not SRAM write enable. Reads return 0x00 when this bit is clear
2012-05-14 13:32:55 +00:00
//===================
First version split into asnes and bsnes.
2010-08-09 13:28:56 +00:00
Update to v089r02 release. (r01 was not posted to the WIP thread) byuu says: r01 changelog: - major improvements to SPC7110 MCU (memory controller unit) - revised SPC7110 memory map to reflect aforementioned improvements - added "Toggle Tracer" hotkey to target-ethos (only works for SFC so far, I plan to use this as a lightweight laevateinn for FEoEZ) r02 changelog: - quick fix: SRAM is mapped to 00-3f|80-bf:6000-7fff - quick fix: $4830.d7 is SRAM chip enable, not SRAM write enable. Reads return 0x00 when this bit is clear
2012-05-14 13:32:55 +00:00
case 0x4830: return r4830;
case 0x4831: return r4831;
case 0x4832: return r4832;
case 0x4833: return r4833;
case 0x4834: return r4834;
First version split into asnes and bsnes.
2010-08-09 13:28:56 +00:00
}
return cpu.regs.mdr;
}
Update to v089r16 release. byuu says: Changelog: - eliminated <mmio>, <mcu> tags [they are merged to their parent nodes now] - added <ram name= size=> tag to EpsonRTC, SharpRTC - added <firmware> tag to DSP-n, ST-01n, ST-018, Cx4 - interface->path(0) now returns the system folder, which can be used for storage now - as a fun proof-of-concept, I've simulated SNES warm power cycles by saving and loading work RAM (same effect if you instantly swapped carts) - long-term, I'm not sure how I want to do this. The power menu option makes no sense with warm RAM - I like the idea of decaying RAM based on timestamp from last play; and power can just force the timestamp to 0 (which will corrupt all RAM) - Interface::firmware is gone. The cores now load firmware inside their boot up routines - you now get a message on the screen if the emulator can't find firmware, should help with "I just get a black screen" messages I'd like to start preparing for a v090 release. I think we're almost there now. Have to update nall/cartridge and purify to handle XML changes first.
2012-07-15 09:47:35 +00:00
void SPC7110::write(unsigned addr, uint8 data) {
Update to v089r03 release. byuu says: Substantial improvements to SPC7110 emulation. Added all of the findings from http://byuu.org/temp/spc7110-mmio.txt that I understood. I also completely rewrote the RTC. We only had about ~40% of the chip emulated before. Turns out there's cool stuff like spare RAM, calendar disable, 12-hour mode, IRQs, IRQ masking, duty cycles, etc. So I went ahead and emulated all of it. The upper bits on hour+ don't work as nocash described though, not sure what doc he was reading. The Epson RTC-4513 manual I have doesn't explain any of the registers. The new RTC core also ticks seconds based on the emulated clock, and not on the system clock. This is going to suck for people wanting to keep the in-game clock synced with their computer, who also abuse fast forward and save states. Fast forward makes the clock run faster, and save states will jump the clock to the time it was at when you took the save state. (It will keep track of the number of seconds between unloading the game and loading it again, so time passes normally there.) This is required, however, and how I'm going to rearrange all of the RTCs for all systems. Any other method can be detected by the game, and is thus not faithful emulation. To help with this, I'll probably make an RTC time tool so that you can adjust the time when the emulator isn't running, but I don't intend to bundle that into bsnes. New state format bit-packs the RTCRAM values, and it also uses a 64-bit timestamp. So it's 16 bytes now instead of 20 bytes. S-RTC will drop from 16 to 12 when it's done. The RTC busy flag timing needs to be refined with more hardware tests, there's a slim chance of the game hanging on save at the moment. The SPC7110 ALU delays are emulated now, too. They may not be perfectly accurate, but they get the basic gist down. The only hack that needs to be removed now is the decompression busy flag. That's ... not going to be fun. I also redid the mouse emulation. I was polling the mouse position multiple times per latch. So it should be a bit more precise now, I hope. I read it regardless of latch state, dunno if that's good or not.
2012-05-16 00:27:34 +00:00
cpu.synchronize_coprocessors();
Update to v089r09 release. byuu says: Changelog: - SPC7110 data port emulation greatly improved - SPC7110 $480b.d1 emulated (but $4805-4806 does not work right for mode 2 decompression yet) - MSU1 audio output will be muted when the S-DSP FLG ($6c).d6 (mute) flag is set - MSU1 will read filenames from manifest now (defaults to msu1.rom and track-#.pcm if missing ... for now) - bugfixes with MSU1 load state and track seek (and $4804 was wrapping into $4805 to change the track#) - Link coprocessor removed (it was meant for ST018 HLE, which never happened) Notes for things I forgot but need to address: - $4813 needs to be uint7 for the set_data_offset() to not allow reading A23 as set ever (or we can mask) - AbsoluteInput when window doesn't have focus should return -32768, not 0 - need to support input ID lists that aren't linear (0-7), but arbitrary (0,1,6,7 or whatever)
2012-05-29 12:20:46 +00:00
addr = 0x4800 | (addr & 0x3f);
First version split into asnes and bsnes.
2010-08-09 13:28:56 +00:00
switch(addr) {
Update to v089r02 release. (r01 was not posted to the WIP thread) byuu says: r01 changelog: - major improvements to SPC7110 MCU (memory controller unit) - revised SPC7110 memory map to reflect aforementioned improvements - added "Toggle Tracer" hotkey to target-ethos (only works for SFC so far, I plan to use this as a lightweight laevateinn for FEoEZ) r02 changelog: - quick fix: SRAM is mapped to 00-3f|80-bf:6000-7fff - quick fix: $4830.d7 is SRAM chip enable, not SRAM write enable. Reads return 0x00 when this bit is clear
2012-05-14 13:32:55 +00:00
//==================
//decompression unit
//==================
case 0x4801: r4801 = data; break;
case 0x4802: r4802 = data; break;
Update to v089r10 release. byuu says: Changelog: - Cydrak merged all three SPC7110 decompression routines into one, cuts the size in half - fixed masking of $4803.d7 and $4813.d7 - data port out of bounds accesses emulated correctly for app SPC7110 boards - all(?) data port $4810 reload cases now supported - basic timing for $4805-6 seeking; reworked delay timing to work better as well - fixed $480c.d7 flag (1 = ready, not busy) - AbsoluteInput returns -32768 if presentation window lacks focus and you don't always allow input
2012-05-31 12:27:46 +00:00
case 0x4803: r4803 = data; break;
Update to v089r04 release. byuu says: Changelog: (SPC7110) - emulated $480b.d0 + $4807 deinterleave mode - cleaned up decompression core (I'd still like to wipe out those static variables, those are bad for save states.) - improved emulation of data port ($481a only increments, never reads) - improved emulation of RTC (block appropriate bits in the hour register based on 12/24h mode select; $4840 modes != 1 all disable the chip; added MDR; etc.)
2012-05-19 06:28:54 +00:00
case 0x4804: r4804 = data; dcu_load_address(); break;
Update to v089r02 release. (r01 was not posted to the WIP thread) byuu says: r01 changelog: - major improvements to SPC7110 MCU (memory controller unit) - revised SPC7110 memory map to reflect aforementioned improvements - added "Toggle Tracer" hotkey to target-ethos (only works for SFC so far, I plan to use this as a lightweight laevateinn for FEoEZ) r02 changelog: - quick fix: SRAM is mapped to 00-3f|80-bf:6000-7fff - quick fix: $4830.d7 is SRAM chip enable, not SRAM write enable. Reads return 0x00 when this bit is clear
2012-05-14 13:32:55 +00:00
case 0x4805: r4805 = data; break;
Update to v089r10 release. byuu says: Changelog: - Cydrak merged all three SPC7110 decompression routines into one, cuts the size in half - fixed masking of $4803.d7 and $4813.d7 - data port out of bounds accesses emulated correctly for app SPC7110 boards - all(?) data port $4810 reload cases now supported - basic timing for $4805-6 seeking; reworked delay timing to work better as well - fixed $480c.d7 flag (1 = ready, not busy) - AbsoluteInput returns -32768 if presentation window lacks focus and you don't always allow input
2012-05-31 12:27:46 +00:00
case 0x4806: r4806 = data; r480c &= 0x7f; dcu_pending = 1; break;
Update to v089r02 release. (r01 was not posted to the WIP thread) byuu says: r01 changelog: - major improvements to SPC7110 MCU (memory controller unit) - revised SPC7110 memory map to reflect aforementioned improvements - added "Toggle Tracer" hotkey to target-ethos (only works for SFC so far, I plan to use this as a lightweight laevateinn for FEoEZ) r02 changelog: - quick fix: SRAM is mapped to 00-3f|80-bf:6000-7fff - quick fix: $4830.d7 is SRAM chip enable, not SRAM write enable. Reads return 0x00 when this bit is clear
2012-05-14 13:32:55 +00:00
case 0x4807: r4807 = data; break;
Update to v089r03 release. byuu says: Substantial improvements to SPC7110 emulation. Added all of the findings from http://byuu.org/temp/spc7110-mmio.txt that I understood. I also completely rewrote the RTC. We only had about ~40% of the chip emulated before. Turns out there's cool stuff like spare RAM, calendar disable, 12-hour mode, IRQs, IRQ masking, duty cycles, etc. So I went ahead and emulated all of it. The upper bits on hour+ don't work as nocash described though, not sure what doc he was reading. The Epson RTC-4513 manual I have doesn't explain any of the registers. The new RTC core also ticks seconds based on the emulated clock, and not on the system clock. This is going to suck for people wanting to keep the in-game clock synced with their computer, who also abuse fast forward and save states. Fast forward makes the clock run faster, and save states will jump the clock to the time it was at when you took the save state. (It will keep track of the number of seconds between unloading the game and loading it again, so time passes normally there.) This is required, however, and how I'm going to rearrange all of the RTCs for all systems. Any other method can be detected by the game, and is thus not faithful emulation. To help with this, I'll probably make an RTC time tool so that you can adjust the time when the emulator isn't running, but I don't intend to bundle that into bsnes. New state format bit-packs the RTCRAM values, and it also uses a 64-bit timestamp. So it's 16 bytes now instead of 20 bytes. S-RTC will drop from 16 to 12 when it's done. The RTC busy flag timing needs to be refined with more hardware tests, there's a slim chance of the game hanging on save at the moment. The SPC7110 ALU delays are emulated now, too. They may not be perfectly accurate, but they get the basic gist down. The only hack that needs to be removed now is the decompression busy flag. That's ... not going to be fun. I also redid the mouse emulation. I was polling the mouse position multiple times per latch. So it should be a bit more precise now, I hope. I read it regardless of latch state, dunno if that's good or not.
2012-05-16 00:27:34 +00:00
case 0x4808: break;
Update to v089r02 release. (r01 was not posted to the WIP thread) byuu says: r01 changelog: - major improvements to SPC7110 MCU (memory controller unit) - revised SPC7110 memory map to reflect aforementioned improvements - added "Toggle Tracer" hotkey to target-ethos (only works for SFC so far, I plan to use this as a lightweight laevateinn for FEoEZ) r02 changelog: - quick fix: SRAM is mapped to 00-3f|80-bf:6000-7fff - quick fix: $4830.d7 is SRAM chip enable, not SRAM write enable. Reads return 0x00 when this bit is clear
2012-05-14 13:32:55 +00:00
case 0x4809: r4809 = data; break;
case 0x480a: r480a = data; break;
Update to v089r03 release. byuu says: Substantial improvements to SPC7110 emulation. Added all of the findings from http://byuu.org/temp/spc7110-mmio.txt that I understood. I also completely rewrote the RTC. We only had about ~40% of the chip emulated before. Turns out there's cool stuff like spare RAM, calendar disable, 12-hour mode, IRQs, IRQ masking, duty cycles, etc. So I went ahead and emulated all of it. The upper bits on hour+ don't work as nocash described though, not sure what doc he was reading. The Epson RTC-4513 manual I have doesn't explain any of the registers. The new RTC core also ticks seconds based on the emulated clock, and not on the system clock. This is going to suck for people wanting to keep the in-game clock synced with their computer, who also abuse fast forward and save states. Fast forward makes the clock run faster, and save states will jump the clock to the time it was at when you took the save state. (It will keep track of the number of seconds between unloading the game and loading it again, so time passes normally there.) This is required, however, and how I'm going to rearrange all of the RTCs for all systems. Any other method can be detected by the game, and is thus not faithful emulation. To help with this, I'll probably make an RTC time tool so that you can adjust the time when the emulator isn't running, but I don't intend to bundle that into bsnes. New state format bit-packs the RTCRAM values, and it also uses a 64-bit timestamp. So it's 16 bytes now instead of 20 bytes. S-RTC will drop from 16 to 12 when it's done. The RTC busy flag timing needs to be refined with more hardware tests, there's a slim chance of the game hanging on save at the moment. The SPC7110 ALU delays are emulated now, too. They may not be perfectly accurate, but they get the basic gist down. The only hack that needs to be removed now is the decompression busy flag. That's ... not going to be fun. I also redid the mouse emulation. I was polling the mouse position multiple times per latch. So it should be a bit more precise now, I hope. I read it regardless of latch state, dunno if that's good or not.
2012-05-16 00:27:34 +00:00
case 0x480b: r480b = data & 0x03; break;
Update to v089r02 release. (r01 was not posted to the WIP thread) byuu says: r01 changelog: - major improvements to SPC7110 MCU (memory controller unit) - revised SPC7110 memory map to reflect aforementioned improvements - added "Toggle Tracer" hotkey to target-ethos (only works for SFC so far, I plan to use this as a lightweight laevateinn for FEoEZ) r02 changelog: - quick fix: SRAM is mapped to 00-3f|80-bf:6000-7fff - quick fix: $4830.d7 is SRAM chip enable, not SRAM write enable. Reads return 0x00 when this bit is clear
2012-05-14 13:32:55 +00:00
//==============
//data port unit
//==============
Update to v089r03 release. byuu says: Substantial improvements to SPC7110 emulation. Added all of the findings from http://byuu.org/temp/spc7110-mmio.txt that I understood. I also completely rewrote the RTC. We only had about ~40% of the chip emulated before. Turns out there's cool stuff like spare RAM, calendar disable, 12-hour mode, IRQs, IRQ masking, duty cycles, etc. So I went ahead and emulated all of it. The upper bits on hour+ don't work as nocash described though, not sure what doc he was reading. The Epson RTC-4513 manual I have doesn't explain any of the registers. The new RTC core also ticks seconds based on the emulated clock, and not on the system clock. This is going to suck for people wanting to keep the in-game clock synced with their computer, who also abuse fast forward and save states. Fast forward makes the clock run faster, and save states will jump the clock to the time it was at when you took the save state. (It will keep track of the number of seconds between unloading the game and loading it again, so time passes normally there.) This is required, however, and how I'm going to rearrange all of the RTCs for all systems. Any other method can be detected by the game, and is thus not faithful emulation. To help with this, I'll probably make an RTC time tool so that you can adjust the time when the emulator isn't running, but I don't intend to bundle that into bsnes. New state format bit-packs the RTCRAM values, and it also uses a 64-bit timestamp. So it's 16 bytes now instead of 20 bytes. S-RTC will drop from 16 to 12 when it's done. The RTC busy flag timing needs to be refined with more hardware tests, there's a slim chance of the game hanging on save at the moment. The SPC7110 ALU delays are emulated now, too. They may not be perfectly accurate, but they get the basic gist down. The only hack that needs to be removed now is the decompression busy flag. That's ... not going to be fun. I also redid the mouse emulation. I was polling the mouse position multiple times per latch. So it should be a bit more precise now, I hope. I read it regardless of latch state, dunno if that's good or not.
2012-05-16 00:27:34 +00:00
case 0x4811: r4811 = data; break;
case 0x4812: r4812 = data; break;
Update to v089r10 release. byuu says: Changelog: - Cydrak merged all three SPC7110 decompression routines into one, cuts the size in half - fixed masking of $4803.d7 and $4813.d7 - data port out of bounds accesses emulated correctly for app SPC7110 boards - all(?) data port $4810 reload cases now supported - basic timing for $4805-6 seeking; reworked delay timing to work better as well - fixed $480c.d7 flag (1 = ready, not busy) - AbsoluteInput returns -32768 if presentation window lacks focus and you don't always allow input
2012-05-31 12:27:46 +00:00
case 0x4813: r4813 = data; data_port_read(); break;
Update to v089r09 release. byuu says: Changelog: - SPC7110 data port emulation greatly improved - SPC7110 $480b.d1 emulated (but $4805-4806 does not work right for mode 2 decompression yet) - MSU1 audio output will be muted when the S-DSP FLG ($6c).d6 (mute) flag is set - MSU1 will read filenames from manifest now (defaults to msu1.rom and track-#.pcm if missing ... for now) - bugfixes with MSU1 load state and track seek (and $4804 was wrapping into $4805 to change the track#) - Link coprocessor removed (it was meant for ST018 HLE, which never happened) Notes for things I forgot but need to address: - $4813 needs to be uint7 for the set_data_offset() to not allow reading A23 as set ever (or we can mask) - AbsoluteInput when window doesn't have focus should return -32768, not 0 - need to support input ID lists that aren't linear (0-7), but arbitrary (0,1,6,7 or whatever)
2012-05-29 12:20:46 +00:00
case 0x4814: r4814 = data; data_port_increment_4814(); break;
Update to v089r10 release. byuu says: Changelog: - Cydrak merged all three SPC7110 decompression routines into one, cuts the size in half - fixed masking of $4803.d7 and $4813.d7 - data port out of bounds accesses emulated correctly for app SPC7110 boards - all(?) data port $4810 reload cases now supported - basic timing for $4805-6 seeking; reworked delay timing to work better as well - fixed $480c.d7 flag (1 = ready, not busy) - AbsoluteInput returns -32768 if presentation window lacks focus and you don't always allow input
2012-05-31 12:27:46 +00:00
case 0x4815: r4815 = data; if(r4818 & 2) data_port_read(); data_port_increment_4815(); break;
Update to v089r02 release. (r01 was not posted to the WIP thread) byuu says: r01 changelog: - major improvements to SPC7110 MCU (memory controller unit) - revised SPC7110 memory map to reflect aforementioned improvements - added "Toggle Tracer" hotkey to target-ethos (only works for SFC so far, I plan to use this as a lightweight laevateinn for FEoEZ) r02 changelog: - quick fix: SRAM is mapped to 00-3f|80-bf:6000-7fff - quick fix: $4830.d7 is SRAM chip enable, not SRAM write enable. Reads return 0x00 when this bit is clear
2012-05-14 13:32:55 +00:00
case 0x4816: r4816 = data; break;
case 0x4817: r4817 = data; break;
Update to v089r09 release. byuu says: Changelog: - SPC7110 data port emulation greatly improved - SPC7110 $480b.d1 emulated (but $4805-4806 does not work right for mode 2 decompression yet) - MSU1 audio output will be muted when the S-DSP FLG ($6c).d6 (mute) flag is set - MSU1 will read filenames from manifest now (defaults to msu1.rom and track-#.pcm if missing ... for now) - bugfixes with MSU1 load state and track seek (and $4804 was wrapping into $4805 to change the track#) - Link coprocessor removed (it was meant for ST018 HLE, which never happened) Notes for things I forgot but need to address: - $4813 needs to be uint7 for the set_data_offset() to not allow reading A23 as set ever (or we can mask) - AbsoluteInput when window doesn't have focus should return -32768, not 0 - need to support input ID lists that aren't linear (0-7), but arbitrary (0,1,6,7 or whatever)
2012-05-29 12:20:46 +00:00
case 0x4818: r4818 = data & 0x7f; data_port_read(); break;
Update to v089r02 release. (r01 was not posted to the WIP thread) byuu says: r01 changelog: - major improvements to SPC7110 MCU (memory controller unit) - revised SPC7110 memory map to reflect aforementioned improvements - added "Toggle Tracer" hotkey to target-ethos (only works for SFC so far, I plan to use this as a lightweight laevateinn for FEoEZ) r02 changelog: - quick fix: SRAM is mapped to 00-3f|80-bf:6000-7fff - quick fix: $4830.d7 is SRAM chip enable, not SRAM write enable. Reads return 0x00 when this bit is clear
2012-05-14 13:32:55 +00:00
Update to v089r09 release. byuu says: Changelog: - SPC7110 data port emulation greatly improved - SPC7110 $480b.d1 emulated (but $4805-4806 does not work right for mode 2 decompression yet) - MSU1 audio output will be muted when the S-DSP FLG ($6c).d6 (mute) flag is set - MSU1 will read filenames from manifest now (defaults to msu1.rom and track-#.pcm if missing ... for now) - bugfixes with MSU1 load state and track seek (and $4804 was wrapping into $4805 to change the track#) - Link coprocessor removed (it was meant for ST018 HLE, which never happened) Notes for things I forgot but need to address: - $4813 needs to be uint7 for the set_data_offset() to not allow reading A23 as set ever (or we can mask) - AbsoluteInput when window doesn't have focus should return -32768, not 0 - need to support input ID lists that aren't linear (0-7), but arbitrary (0,1,6,7 or whatever)
2012-05-29 12:20:46 +00:00
//=====================
//arithmetic logic unit
//=====================
Update to v089r02 release. (r01 was not posted to the WIP thread) byuu says: r01 changelog: - major improvements to SPC7110 MCU (memory controller unit) - revised SPC7110 memory map to reflect aforementioned improvements - added "Toggle Tracer" hotkey to target-ethos (only works for SFC so far, I plan to use this as a lightweight laevateinn for FEoEZ) r02 changelog: - quick fix: SRAM is mapped to 00-3f|80-bf:6000-7fff - quick fix: $4830.d7 is SRAM chip enable, not SRAM write enable. Reads return 0x00 when this bit is clear
2012-05-14 13:32:55 +00:00
case 0x4820: r4820 = data; break;
case 0x4821: r4821 = data; break;
case 0x4822: r4822 = data; break;
case 0x4823: r4823 = data; break;
case 0x4824: r4824 = data; break;
Update to v089r10 release. byuu says: Changelog: - Cydrak merged all three SPC7110 decompression routines into one, cuts the size in half - fixed masking of $4803.d7 and $4813.d7 - data port out of bounds accesses emulated correctly for app SPC7110 boards - all(?) data port $4810 reload cases now supported - basic timing for $4805-6 seeking; reworked delay timing to work better as well - fixed $480c.d7 flag (1 = ready, not busy) - AbsoluteInput returns -32768 if presentation window lacks focus and you don't always allow input
2012-05-31 12:27:46 +00:00
case 0x4825: r4825 = data; r482f |= 0x81; mul_pending = 1; break;
Update to v089r02 release. (r01 was not posted to the WIP thread) byuu says: r01 changelog: - major improvements to SPC7110 MCU (memory controller unit) - revised SPC7110 memory map to reflect aforementioned improvements - added "Toggle Tracer" hotkey to target-ethos (only works for SFC so far, I plan to use this as a lightweight laevateinn for FEoEZ) r02 changelog: - quick fix: SRAM is mapped to 00-3f|80-bf:6000-7fff - quick fix: $4830.d7 is SRAM chip enable, not SRAM write enable. Reads return 0x00 when this bit is clear
2012-05-14 13:32:55 +00:00
case 0x4826: r4826 = data; break;
Update to v089r10 release. byuu says: Changelog: - Cydrak merged all three SPC7110 decompression routines into one, cuts the size in half - fixed masking of $4803.d7 and $4813.d7 - data port out of bounds accesses emulated correctly for app SPC7110 boards - all(?) data port $4810 reload cases now supported - basic timing for $4805-6 seeking; reworked delay timing to work better as well - fixed $480c.d7 flag (1 = ready, not busy) - AbsoluteInput returns -32768 if presentation window lacks focus and you don't always allow input
2012-05-31 12:27:46 +00:00
case 0x4827: r4827 = data; r482f |= 0x80; div_pending = 1; break;
Update to v089r03 release. byuu says: Substantial improvements to SPC7110 emulation. Added all of the findings from http://byuu.org/temp/spc7110-mmio.txt that I understood. I also completely rewrote the RTC. We only had about ~40% of the chip emulated before. Turns out there's cool stuff like spare RAM, calendar disable, 12-hour mode, IRQs, IRQ masking, duty cycles, etc. So I went ahead and emulated all of it. The upper bits on hour+ don't work as nocash described though, not sure what doc he was reading. The Epson RTC-4513 manual I have doesn't explain any of the registers. The new RTC core also ticks seconds based on the emulated clock, and not on the system clock. This is going to suck for people wanting to keep the in-game clock synced with their computer, who also abuse fast forward and save states. Fast forward makes the clock run faster, and save states will jump the clock to the time it was at when you took the save state. (It will keep track of the number of seconds between unloading the game and loading it again, so time passes normally there.) This is required, however, and how I'm going to rearrange all of the RTCs for all systems. Any other method can be detected by the game, and is thus not faithful emulation. To help with this, I'll probably make an RTC time tool so that you can adjust the time when the emulator isn't running, but I don't intend to bundle that into bsnes. New state format bit-packs the RTCRAM values, and it also uses a 64-bit timestamp. So it's 16 bytes now instead of 20 bytes. S-RTC will drop from 16 to 12 when it's done. The RTC busy flag timing needs to be refined with more hardware tests, there's a slim chance of the game hanging on save at the moment. The SPC7110 ALU delays are emulated now, too. They may not be perfectly accurate, but they get the basic gist down. The only hack that needs to be removed now is the decompression busy flag. That's ... not going to be fun. I also redid the mouse emulation. I was polling the mouse position multiple times per latch. So it should be a bit more precise now, I hope. I read it regardless of latch state, dunno if that's good or not.
2012-05-16 00:27:34 +00:00
case 0x482e: r482e = data & 0x01; break;
Update to v089r02 release. (r01 was not posted to the WIP thread) byuu says: r01 changelog: - major improvements to SPC7110 MCU (memory controller unit) - revised SPC7110 memory map to reflect aforementioned improvements - added "Toggle Tracer" hotkey to target-ethos (only works for SFC so far, I plan to use this as a lightweight laevateinn for FEoEZ) r02 changelog: - quick fix: SRAM is mapped to 00-3f|80-bf:6000-7fff - quick fix: $4830.d7 is SRAM chip enable, not SRAM write enable. Reads return 0x00 when this bit is clear
2012-05-14 13:32:55 +00:00
//===================
Update to v089r09 release. byuu says: Changelog: - SPC7110 data port emulation greatly improved - SPC7110 $480b.d1 emulated (but $4805-4806 does not work right for mode 2 decompression yet) - MSU1 audio output will be muted when the S-DSP FLG ($6c).d6 (mute) flag is set - MSU1 will read filenames from manifest now (defaults to msu1.rom and track-#.pcm if missing ... for now) - bugfixes with MSU1 load state and track seek (and $4804 was wrapping into $4805 to change the track#) - Link coprocessor removed (it was meant for ST018 HLE, which never happened) Notes for things I forgot but need to address: - $4813 needs to be uint7 for the set_data_offset() to not allow reading A23 as set ever (or we can mask) - AbsoluteInput when window doesn't have focus should return -32768, not 0 - need to support input ID lists that aren't linear (0-7), but arbitrary (0,1,6,7 or whatever)
2012-05-29 12:20:46 +00:00
//memory control unit
Update to v089r02 release. (r01 was not posted to the WIP thread) byuu says: r01 changelog: - major improvements to SPC7110 MCU (memory controller unit) - revised SPC7110 memory map to reflect aforementioned improvements - added "Toggle Tracer" hotkey to target-ethos (only works for SFC so far, I plan to use this as a lightweight laevateinn for FEoEZ) r02 changelog: - quick fix: SRAM is mapped to 00-3f|80-bf:6000-7fff - quick fix: $4830.d7 is SRAM chip enable, not SRAM write enable. Reads return 0x00 when this bit is clear
2012-05-14 13:32:55 +00:00
//===================
case 0x4830: r4830 = data & 0x87; break;
case 0x4831: r4831 = data & 0x07; break;
case 0x4832: r4832 = data & 0x07; break;
case 0x4833: r4833 = data & 0x07; break;
case 0x4834: r4834 = data & 0x07; break;
First version split into asnes and bsnes.
2010-08-09 13:28:56 +00:00
}
}
Update to v089r02 release. (r01 was not posted to the WIP thread) byuu says: r01 changelog: - major improvements to SPC7110 MCU (memory controller unit) - revised SPC7110 memory map to reflect aforementioned improvements - added "Toggle Tracer" hotkey to target-ethos (only works for SFC so far, I plan to use this as a lightweight laevateinn for FEoEZ) r02 changelog: - quick fix: SRAM is mapped to 00-3f|80-bf:6000-7fff - quick fix: $4830.d7 is SRAM chip enable, not SRAM write enable. Reads return 0x00 when this bit is clear
2012-05-14 13:32:55 +00:00
//===============
//SPC7110::MCUROM
//===============
First version split into asnes and bsnes.
2010-08-09 13:28:56 +00:00
Update to v089r02 release. (r01 was not posted to the WIP thread) byuu says: r01 changelog: - major improvements to SPC7110 MCU (memory controller unit) - revised SPC7110 memory map to reflect aforementioned improvements - added "Toggle Tracer" hotkey to target-ethos (only works for SFC so far, I plan to use this as a lightweight laevateinn for FEoEZ) r02 changelog: - quick fix: SRAM is mapped to 00-3f|80-bf:6000-7fff - quick fix: $4830.d7 is SRAM chip enable, not SRAM write enable. Reads return 0x00 when this bit is clear
2012-05-14 13:32:55 +00:00
uint8 SPC7110::mcurom_read(unsigned addr) {
Update to v089r03 release. byuu says: Substantial improvements to SPC7110 emulation. Added all of the findings from http://byuu.org/temp/spc7110-mmio.txt that I understood. I also completely rewrote the RTC. We only had about ~40% of the chip emulated before. Turns out there's cool stuff like spare RAM, calendar disable, 12-hour mode, IRQs, IRQ masking, duty cycles, etc. So I went ahead and emulated all of it. The upper bits on hour+ don't work as nocash described though, not sure what doc he was reading. The Epson RTC-4513 manual I have doesn't explain any of the registers. The new RTC core also ticks seconds based on the emulated clock, and not on the system clock. This is going to suck for people wanting to keep the in-game clock synced with their computer, who also abuse fast forward and save states. Fast forward makes the clock run faster, and save states will jump the clock to the time it was at when you took the save state. (It will keep track of the number of seconds between unloading the game and loading it again, so time passes normally there.) This is required, however, and how I'm going to rearrange all of the RTCs for all systems. Any other method can be detected by the game, and is thus not faithful emulation. To help with this, I'll probably make an RTC time tool so that you can adjust the time when the emulator isn't running, but I don't intend to bundle that into bsnes. New state format bit-packs the RTCRAM values, and it also uses a 64-bit timestamp. So it's 16 bytes now instead of 20 bytes. S-RTC will drop from 16 to 12 when it's done. The RTC busy flag timing needs to be refined with more hardware tests, there's a slim chance of the game hanging on save at the moment. The SPC7110 ALU delays are emulated now, too. They may not be perfectly accurate, but they get the basic gist down. The only hack that needs to be removed now is the decompression busy flag. That's ... not going to be fun. I also redid the mouse emulation. I was polling the mouse position multiple times per latch. So it should be a bit more precise now, I hope. I read it regardless of latch state, dunno if that's good or not.
2012-05-16 00:27:34 +00:00
unsigned mask = (1 << (r4834 & 3)) - 1; //8mbit, 16mbit, 32mbit, 64mbit DROM
Update to v089r02 release. (r01 was not posted to the WIP thread) byuu says: r01 changelog: - major improvements to SPC7110 MCU (memory controller unit) - revised SPC7110 memory map to reflect aforementioned improvements - added "Toggle Tracer" hotkey to target-ethos (only works for SFC so far, I plan to use this as a lightweight laevateinn for FEoEZ) r02 changelog: - quick fix: SRAM is mapped to 00-3f|80-bf:6000-7fff - quick fix: $4830.d7 is SRAM chip enable, not SRAM write enable. Reads return 0x00 when this bit is clear
2012-05-14 13:32:55 +00:00
if((addr & 0x708000) == 0x008000 //$00-0f|80-8f:8000-ffff
|| (addr & 0xf00000) == 0xc00000 // $c0-cf:0000-ffff
) {
addr &= 0x0fffff;
Update to v089r15 release. byuu says: Changelog: - SuperFX has its own ROM and RAM - Cx4 has its own ROM - SPC7110 has its own ProgramROM, DataROM and RAM - OBC1 has its own RAM - BsxCartridge has its own ROM, RAM and PSRAM - mapping changes to accommodate the above
2012-07-09 11:40:23 +00:00
if(prom.size()) { //8mbit PROM
return prom.read(bus.mirror(0x000000 + addr, prom.size()));
Update to v089r02 release. (r01 was not posted to the WIP thread) byuu says: r01 changelog: - major improvements to SPC7110 MCU (memory controller unit) - revised SPC7110 memory map to reflect aforementioned improvements - added "Toggle Tracer" hotkey to target-ethos (only works for SFC so far, I plan to use this as a lightweight laevateinn for FEoEZ) r02 changelog: - quick fix: SRAM is mapped to 00-3f|80-bf:6000-7fff - quick fix: $4830.d7 is SRAM chip enable, not SRAM write enable. Reads return 0x00 when this bit is clear
2012-05-14 13:32:55 +00:00
}
Update to v089r03 release. byuu says: Substantial improvements to SPC7110 emulation. Added all of the findings from http://byuu.org/temp/spc7110-mmio.txt that I understood. I also completely rewrote the RTC. We only had about ~40% of the chip emulated before. Turns out there's cool stuff like spare RAM, calendar disable, 12-hour mode, IRQs, IRQ masking, duty cycles, etc. So I went ahead and emulated all of it. The upper bits on hour+ don't work as nocash described though, not sure what doc he was reading. The Epson RTC-4513 manual I have doesn't explain any of the registers. The new RTC core also ticks seconds based on the emulated clock, and not on the system clock. This is going to suck for people wanting to keep the in-game clock synced with their computer, who also abuse fast forward and save states. Fast forward makes the clock run faster, and save states will jump the clock to the time it was at when you took the save state. (It will keep track of the number of seconds between unloading the game and loading it again, so time passes normally there.) This is required, however, and how I'm going to rearrange all of the RTCs for all systems. Any other method can be detected by the game, and is thus not faithful emulation. To help with this, I'll probably make an RTC time tool so that you can adjust the time when the emulator isn't running, but I don't intend to bundle that into bsnes. New state format bit-packs the RTCRAM values, and it also uses a 64-bit timestamp. So it's 16 bytes now instead of 20 bytes. S-RTC will drop from 16 to 12 when it's done. The RTC busy flag timing needs to be refined with more hardware tests, there's a slim chance of the game hanging on save at the moment. The SPC7110 ALU delays are emulated now, too. They may not be perfectly accurate, but they get the basic gist down. The only hack that needs to be removed now is the decompression busy flag. That's ... not going to be fun. I also redid the mouse emulation. I was polling the mouse position multiple times per latch. So it should be a bit more precise now, I hope. I read it regardless of latch state, dunno if that's good or not.
2012-05-16 00:27:34 +00:00
addr |= 0x100000 * (r4830 & 7);
return datarom_read(addr);
Update to v089r02 release. (r01 was not posted to the WIP thread) byuu says: r01 changelog: - major improvements to SPC7110 MCU (memory controller unit) - revised SPC7110 memory map to reflect aforementioned improvements - added "Toggle Tracer" hotkey to target-ethos (only works for SFC so far, I plan to use this as a lightweight laevateinn for FEoEZ) r02 changelog: - quick fix: SRAM is mapped to 00-3f|80-bf:6000-7fff - quick fix: $4830.d7 is SRAM chip enable, not SRAM write enable. Reads return 0x00 when this bit is clear
2012-05-14 13:32:55 +00:00
}
if((addr & 0x708000) == 0x108000 //$10-1f|90-9f:8000-ffff
|| (addr & 0xf00000) == 0xd00000 // $d0-df:0000-ffff
) {
addr &= 0x0fffff;
if(r4834 & 4) { //16mbit PROM
Update to v089r15 release. byuu says: Changelog: - SuperFX has its own ROM and RAM - Cx4 has its own ROM - SPC7110 has its own ProgramROM, DataROM and RAM - OBC1 has its own RAM - BsxCartridge has its own ROM, RAM and PSRAM - mapping changes to accommodate the above
2012-07-09 11:40:23 +00:00
return prom.read(bus.mirror(0x100000 + addr, prom.size()));
Update to v089r02 release. (r01 was not posted to the WIP thread) byuu says: r01 changelog: - major improvements to SPC7110 MCU (memory controller unit) - revised SPC7110 memory map to reflect aforementioned improvements - added "Toggle Tracer" hotkey to target-ethos (only works for SFC so far, I plan to use this as a lightweight laevateinn for FEoEZ) r02 changelog: - quick fix: SRAM is mapped to 00-3f|80-bf:6000-7fff - quick fix: $4830.d7 is SRAM chip enable, not SRAM write enable. Reads return 0x00 when this bit is clear
2012-05-14 13:32:55 +00:00
}
Update to v089r03 release. byuu says: Substantial improvements to SPC7110 emulation. Added all of the findings from http://byuu.org/temp/spc7110-mmio.txt that I understood. I also completely rewrote the RTC. We only had about ~40% of the chip emulated before. Turns out there's cool stuff like spare RAM, calendar disable, 12-hour mode, IRQs, IRQ masking, duty cycles, etc. So I went ahead and emulated all of it. The upper bits on hour+ don't work as nocash described though, not sure what doc he was reading. The Epson RTC-4513 manual I have doesn't explain any of the registers. The new RTC core also ticks seconds based on the emulated clock, and not on the system clock. This is going to suck for people wanting to keep the in-game clock synced with their computer, who also abuse fast forward and save states. Fast forward makes the clock run faster, and save states will jump the clock to the time it was at when you took the save state. (It will keep track of the number of seconds between unloading the game and loading it again, so time passes normally there.) This is required, however, and how I'm going to rearrange all of the RTCs for all systems. Any other method can be detected by the game, and is thus not faithful emulation. To help with this, I'll probably make an RTC time tool so that you can adjust the time when the emulator isn't running, but I don't intend to bundle that into bsnes. New state format bit-packs the RTCRAM values, and it also uses a 64-bit timestamp. So it's 16 bytes now instead of 20 bytes. S-RTC will drop from 16 to 12 when it's done. The RTC busy flag timing needs to be refined with more hardware tests, there's a slim chance of the game hanging on save at the moment. The SPC7110 ALU delays are emulated now, too. They may not be perfectly accurate, but they get the basic gist down. The only hack that needs to be removed now is the decompression busy flag. That's ... not going to be fun. I also redid the mouse emulation. I was polling the mouse position multiple times per latch. So it should be a bit more precise now, I hope. I read it regardless of latch state, dunno if that's good or not.
2012-05-16 00:27:34 +00:00
addr |= 0x100000 * (r4831 & 7);
return datarom_read(addr);
Update to v089r02 release. (r01 was not posted to the WIP thread) byuu says: r01 changelog: - major improvements to SPC7110 MCU (memory controller unit) - revised SPC7110 memory map to reflect aforementioned improvements - added "Toggle Tracer" hotkey to target-ethos (only works for SFC so far, I plan to use this as a lightweight laevateinn for FEoEZ) r02 changelog: - quick fix: SRAM is mapped to 00-3f|80-bf:6000-7fff - quick fix: $4830.d7 is SRAM chip enable, not SRAM write enable. Reads return 0x00 when this bit is clear
2012-05-14 13:32:55 +00:00
}
if((addr & 0x708000) == 0x208000 //$20-2f|a0-af:8000-ffff
|| (addr & 0xf00000) == 0xe00000 // $e0-ef:0000-ffff
) {
addr &= 0x0fffff;
Update to v089r03 release. byuu says: Substantial improvements to SPC7110 emulation. Added all of the findings from http://byuu.org/temp/spc7110-mmio.txt that I understood. I also completely rewrote the RTC. We only had about ~40% of the chip emulated before. Turns out there's cool stuff like spare RAM, calendar disable, 12-hour mode, IRQs, IRQ masking, duty cycles, etc. So I went ahead and emulated all of it. The upper bits on hour+ don't work as nocash described though, not sure what doc he was reading. The Epson RTC-4513 manual I have doesn't explain any of the registers. The new RTC core also ticks seconds based on the emulated clock, and not on the system clock. This is going to suck for people wanting to keep the in-game clock synced with their computer, who also abuse fast forward and save states. Fast forward makes the clock run faster, and save states will jump the clock to the time it was at when you took the save state. (It will keep track of the number of seconds between unloading the game and loading it again, so time passes normally there.) This is required, however, and how I'm going to rearrange all of the RTCs for all systems. Any other method can be detected by the game, and is thus not faithful emulation. To help with this, I'll probably make an RTC time tool so that you can adjust the time when the emulator isn't running, but I don't intend to bundle that into bsnes. New state format bit-packs the RTCRAM values, and it also uses a 64-bit timestamp. So it's 16 bytes now instead of 20 bytes. S-RTC will drop from 16 to 12 when it's done. The RTC busy flag timing needs to be refined with more hardware tests, there's a slim chance of the game hanging on save at the moment. The SPC7110 ALU delays are emulated now, too. They may not be perfectly accurate, but they get the basic gist down. The only hack that needs to be removed now is the decompression busy flag. That's ... not going to be fun. I also redid the mouse emulation. I was polling the mouse position multiple times per latch. So it should be a bit more precise now, I hope. I read it regardless of latch state, dunno if that's good or not.
2012-05-16 00:27:34 +00:00
addr |= 0x100000 * (r4832 & 7);
return datarom_read(addr);
Update to v089r02 release. (r01 was not posted to the WIP thread) byuu says: r01 changelog: - major improvements to SPC7110 MCU (memory controller unit) - revised SPC7110 memory map to reflect aforementioned improvements - added "Toggle Tracer" hotkey to target-ethos (only works for SFC so far, I plan to use this as a lightweight laevateinn for FEoEZ) r02 changelog: - quick fix: SRAM is mapped to 00-3f|80-bf:6000-7fff - quick fix: $4830.d7 is SRAM chip enable, not SRAM write enable. Reads return 0x00 when this bit is clear
2012-05-14 13:32:55 +00:00
}
if((addr & 0x708000) == 0x308000 //$30-3f|b0-bf:8000-ffff
|| (addr & 0xf00000) == 0xf00000 // $f0-ff:0000-ffff
) {
addr &= 0x0fffff;
Update to v089r03 release. byuu says: Substantial improvements to SPC7110 emulation. Added all of the findings from http://byuu.org/temp/spc7110-mmio.txt that I understood. I also completely rewrote the RTC. We only had about ~40% of the chip emulated before. Turns out there's cool stuff like spare RAM, calendar disable, 12-hour mode, IRQs, IRQ masking, duty cycles, etc. So I went ahead and emulated all of it. The upper bits on hour+ don't work as nocash described though, not sure what doc he was reading. The Epson RTC-4513 manual I have doesn't explain any of the registers. The new RTC core also ticks seconds based on the emulated clock, and not on the system clock. This is going to suck for people wanting to keep the in-game clock synced with their computer, who also abuse fast forward and save states. Fast forward makes the clock run faster, and save states will jump the clock to the time it was at when you took the save state. (It will keep track of the number of seconds between unloading the game and loading it again, so time passes normally there.) This is required, however, and how I'm going to rearrange all of the RTCs for all systems. Any other method can be detected by the game, and is thus not faithful emulation. To help with this, I'll probably make an RTC time tool so that you can adjust the time when the emulator isn't running, but I don't intend to bundle that into bsnes. New state format bit-packs the RTCRAM values, and it also uses a 64-bit timestamp. So it's 16 bytes now instead of 20 bytes. S-RTC will drop from 16 to 12 when it's done. The RTC busy flag timing needs to be refined with more hardware tests, there's a slim chance of the game hanging on save at the moment. The SPC7110 ALU delays are emulated now, too. They may not be perfectly accurate, but they get the basic gist down. The only hack that needs to be removed now is the decompression busy flag. That's ... not going to be fun. I also redid the mouse emulation. I was polling the mouse position multiple times per latch. So it should be a bit more precise now, I hope. I read it regardless of latch state, dunno if that's good or not.
2012-05-16 00:27:34 +00:00
addr |= 0x100000 * (r4833 & 7);
return datarom_read(addr);
Update to v089r02 release. (r01 was not posted to the WIP thread) byuu says: r01 changelog: - major improvements to SPC7110 MCU (memory controller unit) - revised SPC7110 memory map to reflect aforementioned improvements - added "Toggle Tracer" hotkey to target-ethos (only works for SFC so far, I plan to use this as a lightweight laevateinn for FEoEZ) r02 changelog: - quick fix: SRAM is mapped to 00-3f|80-bf:6000-7fff - quick fix: $4830.d7 is SRAM chip enable, not SRAM write enable. Reads return 0x00 when this bit is clear
2012-05-14 13:32:55 +00:00
}
return cpu.regs.mdr;
First version split into asnes and bsnes.
2010-08-09 13:28:56 +00:00
}
Update to v089r02 release. (r01 was not posted to the WIP thread) byuu says: r01 changelog: - major improvements to SPC7110 MCU (memory controller unit) - revised SPC7110 memory map to reflect aforementioned improvements - added "Toggle Tracer" hotkey to target-ethos (only works for SFC so far, I plan to use this as a lightweight laevateinn for FEoEZ) r02 changelog: - quick fix: SRAM is mapped to 00-3f|80-bf:6000-7fff - quick fix: $4830.d7 is SRAM chip enable, not SRAM write enable. Reads return 0x00 when this bit is clear
2012-05-14 13:32:55 +00:00
void SPC7110::mcurom_write(unsigned addr, uint8 data) {
}
//===============
//SPC7110::MCURAM
//===============
First version split into asnes and bsnes.
2010-08-09 13:28:56 +00:00
Update to v089r02 release. (r01 was not posted to the WIP thread) byuu says: r01 changelog: - major improvements to SPC7110 MCU (memory controller unit) - revised SPC7110 memory map to reflect aforementioned improvements - added "Toggle Tracer" hotkey to target-ethos (only works for SFC so far, I plan to use this as a lightweight laevateinn for FEoEZ) r02 changelog: - quick fix: SRAM is mapped to 00-3f|80-bf:6000-7fff - quick fix: $4830.d7 is SRAM chip enable, not SRAM write enable. Reads return 0x00 when this bit is clear
2012-05-14 13:32:55 +00:00
uint8 SPC7110::mcuram_read(unsigned addr) {
//$00-3f|80-bf:6000-7fff
if(r4830 & 0x80) {
unsigned bank = (addr >> 16) & 0x3f;
Update to v089r15 release. byuu says: Changelog: - SuperFX has its own ROM and RAM - Cx4 has its own ROM - SPC7110 has its own ProgramROM, DataROM and RAM - OBC1 has its own RAM - BsxCartridge has its own ROM, RAM and PSRAM - mapping changes to accommodate the above
2012-07-09 11:40:23 +00:00
addr = bus.mirror(bank * 0x2000 + (addr & 0x1fff), ram.size());
return ram.read(addr);
Update to v089r02 release. (r01 was not posted to the WIP thread) byuu says: r01 changelog: - major improvements to SPC7110 MCU (memory controller unit) - revised SPC7110 memory map to reflect aforementioned improvements - added "Toggle Tracer" hotkey to target-ethos (only works for SFC so far, I plan to use this as a lightweight laevateinn for FEoEZ) r02 changelog: - quick fix: SRAM is mapped to 00-3f|80-bf:6000-7fff - quick fix: $4830.d7 is SRAM chip enable, not SRAM write enable. Reads return 0x00 when this bit is clear
2012-05-14 13:32:55 +00:00
}
return 0x00;
First version split into asnes and bsnes.
2010-08-09 13:28:56 +00:00
}
Update to v089r02 release. (r01 was not posted to the WIP thread) byuu says: r01 changelog: - major improvements to SPC7110 MCU (memory controller unit) - revised SPC7110 memory map to reflect aforementioned improvements - added "Toggle Tracer" hotkey to target-ethos (only works for SFC so far, I plan to use this as a lightweight laevateinn for FEoEZ) r02 changelog: - quick fix: SRAM is mapped to 00-3f|80-bf:6000-7fff - quick fix: $4830.d7 is SRAM chip enable, not SRAM write enable. Reads return 0x00 when this bit is clear
2012-05-14 13:32:55 +00:00
void SPC7110::mcuram_write(unsigned addr, uint8 data) {
//$00-3f|80-bf:6000-7fff
if(r4830 & 0x80) {
unsigned bank = (addr >> 16) & 0x3f;
Update to v089r15 release. byuu says: Changelog: - SuperFX has its own ROM and RAM - Cx4 has its own ROM - SPC7110 has its own ProgramROM, DataROM and RAM - OBC1 has its own RAM - BsxCartridge has its own ROM, RAM and PSRAM - mapping changes to accommodate the above
2012-07-09 11:40:23 +00:00
addr = bus.mirror(bank * 0x2000 + (addr & 0x1fff), ram.size());
ram.write(addr, data);
Update to v089r02 release. (r01 was not posted to the WIP thread) byuu says: r01 changelog: - major improvements to SPC7110 MCU (memory controller unit) - revised SPC7110 memory map to reflect aforementioned improvements - added "Toggle Tracer" hotkey to target-ethos (only works for SFC so far, I plan to use this as a lightweight laevateinn for FEoEZ) r02 changelog: - quick fix: SRAM is mapped to 00-3f|80-bf:6000-7fff - quick fix: $4830.d7 is SRAM chip enable, not SRAM write enable. Reads return 0x00 when this bit is clear
2012-05-14 13:32:55 +00:00
}
First version split into asnes and bsnes.
2010-08-09 13:28:56 +00:00
}
}