mirror of https://github.com/bsnes-emu/bsnes.git
339 lines
7.4 KiB
C++
Executable File
339 lines
7.4 KiB
C++
Executable File
#include <sfc/sfc.hpp>
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#define SPC7110_CPP
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namespace SuperFamicom {
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#include "dcu.cpp"
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#include "data.cpp"
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#include "alu.cpp"
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#include "serialization.cpp"
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SPC7110 spc7110;
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SPC7110::SPC7110() {
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decompressor = new Decompressor(*this);
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}
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SPC7110::~SPC7110() {
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delete decompressor;
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}
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void SPC7110::Enter() { spc7110.enter(); }
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void SPC7110::enter() {
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while(true) {
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if(scheduler.sync == Scheduler::SynchronizeMode::All) {
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scheduler.exit(Scheduler::ExitReason::SynchronizeEvent);
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}
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if(dcu_pending) { dcu_pending = 0; dcu_begin_transfer(); }
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if(mul_pending) { mul_pending = 0; alu_multiply(); }
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if(div_pending) { div_pending = 0; alu_divide(); }
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add_clocks(1);
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}
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}
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void SPC7110::add_clocks(unsigned clocks) {
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step(clocks);
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synchronize_cpu();
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}
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void SPC7110::init() {
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}
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void SPC7110::load() {
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}
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void SPC7110::unload() {
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prom.reset();
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drom.reset();
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ram.reset();
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}
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void SPC7110::power() {
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}
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void SPC7110::reset() {
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create(SPC7110::Enter, 21477272);
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r4801 = 0x00;
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r4802 = 0x00;
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r4803 = 0x00;
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r4804 = 0x00;
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r4805 = 0x00;
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r4806 = 0x00;
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r4807 = 0x00;
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r4809 = 0x00;
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r480a = 0x00;
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r480b = 0x00;
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r480c = 0x00;
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dcu_pending = 0;
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dcu_mode = 0;
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dcu_addr = 0;
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r4810 = 0x00;
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r4811 = 0x00;
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r4812 = 0x00;
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r4813 = 0x00;
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r4814 = 0x00;
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r4815 = 0x00;
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r4816 = 0x00;
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r4817 = 0x00;
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r4818 = 0x00;
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r481a = 0x00;
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r4820 = 0x00;
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r4821 = 0x00;
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r4822 = 0x00;
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r4823 = 0x00;
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r4824 = 0x00;
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r4825 = 0x00;
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r4826 = 0x00;
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r4827 = 0x00;
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r4828 = 0x00;
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r4829 = 0x00;
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r482a = 0x00;
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r482b = 0x00;
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r482c = 0x00;
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r482d = 0x00;
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r482e = 0x00;
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r482f = 0x00;
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mul_pending = 0;
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div_pending = 0;
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r4830 = 0x00;
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r4831 = 0x00;
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r4832 = 0x01;
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r4833 = 0x02;
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r4834 = 0x00;
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}
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uint8 SPC7110::read(unsigned addr) {
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cpu.synchronize_coprocessors();
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if((addr & 0xff0000) == 0x500000) addr = 0x4800;
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addr = 0x4800 | (addr & 0x3f);
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switch(addr) {
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//==================
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//decompression unit
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//==================
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case 0x4800: {
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uint16 counter = r4809 | r480a << 8;
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counter--;
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r4809 = counter >> 0;
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r480a = counter >> 8;
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return dcu_read();
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}
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case 0x4801: return r4801;
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case 0x4802: return r4802;
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case 0x4803: return r4803;
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case 0x4804: return r4804;
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case 0x4805: return r4805;
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case 0x4806: return r4806;
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case 0x4807: return r4807;
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case 0x4808: return 0x00;
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case 0x4809: return r4809;
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case 0x480a: return r480a;
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case 0x480b: return r480b;
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case 0x480c: return r480c;
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//==============
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//data port unit
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//==============
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case 0x4810: {
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uint8 data = r4810;
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data_port_increment_4810();
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return data;
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}
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case 0x4811: return r4811;
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case 0x4812: return r4812;
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case 0x4813: return r4813;
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case 0x4814: return r4814;
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case 0x4815: return r4815;
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case 0x4816: return r4816;
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case 0x4817: return r4817;
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case 0x4818: return r4818;
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case 0x481a: {
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data_port_increment_481a();
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return 0x00;
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}
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//=====================
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//arithmetic logic unit
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//=====================
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case 0x4820: return r4820;
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case 0x4821: return r4821;
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case 0x4822: return r4822;
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case 0x4823: return r4823;
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case 0x4824: return r4824;
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case 0x4825: return r4825;
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case 0x4826: return r4826;
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case 0x4827: return r4827;
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case 0x4828: return r4828;
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case 0x4829: return r4829;
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case 0x482a: return r482a;
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case 0x482b: return r482b;
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case 0x482c: return r482c;
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case 0x482d: return r482d;
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case 0x482e: return r482e;
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case 0x482f: return r482f;
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//===================
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//memory control unit
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//===================
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case 0x4830: return r4830;
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case 0x4831: return r4831;
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case 0x4832: return r4832;
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case 0x4833: return r4833;
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case 0x4834: return r4834;
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}
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return cpu.regs.mdr;
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}
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void SPC7110::write(unsigned addr, uint8 data) {
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cpu.synchronize_coprocessors();
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addr = 0x4800 | (addr & 0x3f);
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switch(addr) {
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//==================
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//decompression unit
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//==================
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case 0x4801: r4801 = data; break;
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case 0x4802: r4802 = data; break;
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case 0x4803: r4803 = data; break;
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case 0x4804: r4804 = data; dcu_load_address(); break;
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case 0x4805: r4805 = data; break;
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case 0x4806: r4806 = data; r480c &= 0x7f; dcu_pending = 1; break;
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case 0x4807: r4807 = data; break;
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case 0x4808: break;
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case 0x4809: r4809 = data; break;
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case 0x480a: r480a = data; break;
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case 0x480b: r480b = data & 0x03; break;
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//==============
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//data port unit
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//==============
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case 0x4811: r4811 = data; break;
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case 0x4812: r4812 = data; break;
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case 0x4813: r4813 = data; data_port_read(); break;
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case 0x4814: r4814 = data; data_port_increment_4814(); break;
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case 0x4815: r4815 = data; if(r4818 & 2) data_port_read(); data_port_increment_4815(); break;
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case 0x4816: r4816 = data; break;
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case 0x4817: r4817 = data; break;
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case 0x4818: r4818 = data & 0x7f; data_port_read(); break;
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//=====================
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//arithmetic logic unit
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//=====================
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case 0x4820: r4820 = data; break;
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case 0x4821: r4821 = data; break;
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case 0x4822: r4822 = data; break;
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case 0x4823: r4823 = data; break;
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case 0x4824: r4824 = data; break;
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case 0x4825: r4825 = data; r482f |= 0x81; mul_pending = 1; break;
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case 0x4826: r4826 = data; break;
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case 0x4827: r4827 = data; r482f |= 0x80; div_pending = 1; break;
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case 0x482e: r482e = data & 0x01; break;
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//===================
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//memory control unit
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//===================
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case 0x4830: r4830 = data & 0x87; break;
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case 0x4831: r4831 = data & 0x07; break;
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case 0x4832: r4832 = data & 0x07; break;
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case 0x4833: r4833 = data & 0x07; break;
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case 0x4834: r4834 = data & 0x07; break;
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}
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}
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//===============
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//SPC7110::MCUROM
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//===============
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uint8 SPC7110::mcurom_read(unsigned addr) {
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unsigned mask = (1 << (r4834 & 3)) - 1; //8mbit, 16mbit, 32mbit, 64mbit DROM
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if((addr & 0x708000) == 0x008000 //$00-0f|80-8f:8000-ffff
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|| (addr & 0xf00000) == 0xc00000 // $c0-cf:0000-ffff
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) {
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addr &= 0x0fffff;
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if(prom.size()) { //8mbit PROM
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return prom.read(bus.mirror(0x000000 + addr, prom.size()));
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}
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addr |= 0x100000 * (r4830 & 7);
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return datarom_read(addr);
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}
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if((addr & 0x708000) == 0x108000 //$10-1f|90-9f:8000-ffff
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|| (addr & 0xf00000) == 0xd00000 // $d0-df:0000-ffff
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) {
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addr &= 0x0fffff;
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if(r4834 & 4) { //16mbit PROM
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return prom.read(bus.mirror(0x100000 + addr, prom.size()));
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}
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addr |= 0x100000 * (r4831 & 7);
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return datarom_read(addr);
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}
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if((addr & 0x708000) == 0x208000 //$20-2f|a0-af:8000-ffff
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|| (addr & 0xf00000) == 0xe00000 // $e0-ef:0000-ffff
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) {
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addr &= 0x0fffff;
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addr |= 0x100000 * (r4832 & 7);
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return datarom_read(addr);
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}
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if((addr & 0x708000) == 0x308000 //$30-3f|b0-bf:8000-ffff
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|| (addr & 0xf00000) == 0xf00000 // $f0-ff:0000-ffff
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) {
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addr &= 0x0fffff;
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addr |= 0x100000 * (r4833 & 7);
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return datarom_read(addr);
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}
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return cpu.regs.mdr;
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}
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void SPC7110::mcurom_write(unsigned addr, uint8 data) {
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}
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//===============
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//SPC7110::MCURAM
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//===============
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uint8 SPC7110::mcuram_read(unsigned addr) {
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//$00-3f|80-bf:6000-7fff
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if(r4830 & 0x80) {
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unsigned bank = (addr >> 16) & 0x3f;
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addr = bus.mirror(bank * 0x2000 + (addr & 0x1fff), ram.size());
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return ram.read(addr);
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}
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return 0x00;
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}
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void SPC7110::mcuram_write(unsigned addr, uint8 data) {
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//$00-3f|80-bf:6000-7fff
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if(r4830 & 0x80) {
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unsigned bank = (addr >> 16) & 0x3f;
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addr = bus.mirror(bank * 0x2000 + (addr & 0x1fff), ram.size());
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ram.write(addr, data);
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}
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}
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}
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