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bsnes
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Update to v089r15 release. 

byuu says:

Changelog:
- SuperFX has its own ROM and RAM
- Cx4 has its own ROM
- SPC7110 has its own ProgramROM, DataROM and RAM
- OBC1 has its own RAM
- BsxCartridge has its own ROM, RAM and PSRAM
- mapping changes to accommodate the above
This commit is contained in:
Tim Allen 2012-07-09 21:40:23 +10:00
parent 27af50099f
commit 791e64951b
26 changed files with 209 additions and 171 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
bsnes/emulator/emulator.hpp
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@ -3,7 +3,7 @@
namespace Emulator {
static const char Name[] = "bsnes";
static const char Version[] = "089.14";
static const char Version[] = "089.15";
static const char Author[] = "byuu";
static const char License[] = "GPLv3";
}

6
bsnes/profile/BS-X Satellaview.sfc/manifest.xml
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@ -1,9 +1,9 @@
<?xml version="1.0" encoding="UTF-8"?>
<cartridge region="NTSC">
<rom name="program.rom" size="0x100000"/>
<ram name="save.ram" size="0x8000"/>
<psram name="bsx.ram" size="0x40000"/>
<bsx>
<rom name="program.rom" size="0x100000"/>
<ram name="save.rwm" size="0x8000"/>
<psram name="flash.rwm" size="0x40000"/>
<mcu>
<map address="00-3f:8000-ffff"/>
<map address="80-bf:8000-ffff"/>

18
bsnes/sfc/cartridge/cartridge.cpp
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@ -48,7 +48,23 @@ void Cartridge::load(const string &manifest) {
//Super Famicom
else {
sha256 = nall::sha256(rom.data(), rom.size());
sha256_ctx sha;
uint8_t hash[32];
sha256_init(&sha);
//hash each ROM image that exists; any with size() == 0 is ignored by sha256_chunk()
sha256_chunk(&sha, rom.data(), rom.size());
sha256_chunk(&sha, bsxcartridge.rom.data(), bsxcartridge.rom.size());
sha256_chunk(&sha, sa1.rom.data(), sa1.rom.size());
sha256_chunk(&sha, superfx.rom.data(), superfx.rom.size());
sha256_chunk(&sha, hitachidsp.rom.data(), hitachidsp.rom.size());
sha256_chunk(&sha, spc7110.prom.data(), spc7110.prom.size());
sha256_chunk(&sha, spc7110.drom.data(), spc7110.drom.size());
sha256_chunk(&sha, sdd1.rom.data(), sdd1.rom.size());
sha256_final(&sha);
sha256_hash(&sha, hash);
string result;
for(auto &byte : hash) result.append(hex<2>(byte));
sha256 = result;
}
rom.write_protect(true);

169
bsnes/sfc/cartridge/markup.cpp
View File

@ -127,6 +127,12 @@ void Cartridge::parse_markup_bsx(XML::Node &root) {
interface->loadRequest(ID::Satellaview, "BS-X Satellaview", "bs");
if(has_bs_cart) {
parse_markup_memory(bsxcartridge.rom, root["rom"], ID::BsxROM, false);
parse_markup_memory(bsxcartridge.ram, root["ram"], ID::BsxRAM, true);
parse_markup_memory(bsxcartridge.psram, root["psram"], ID::BsxPSRAM, true);
}
for(auto &node : root["slot"]) {
if(node.name != "map") continue;
if(bsxflash.memory.size() == 0) continue;
@ -208,36 +214,31 @@ void Cartridge::parse_markup_sa1(XML::Node &root) {
if(root.exists() == false) return;
has_sa1 = true;
auto &rom = root["rom"];
auto &iram = root["iram"];
auto &bwram = root["bwram"];
auto &mmio = root["mmio"];
parse_markup_memory(sa1.rom, rom, ID::SA1ROM, false);
for(auto &node : rom) {
parse_markup_memory(sa1.rom, root["rom"], ID::SA1ROM, false);
for(auto &node : root["rom"]) {
if(node.name != "map") continue;
Mapping m({&SA1::mmc_read, &sa1}, {&SA1::mmc_write, &sa1});
parse_markup_map(m, node);
mapping.append(m);
}
parse_markup_memory(sa1.iram, iram, ID::SA1IRAM, true);
for(auto &node : iram) {
parse_markup_memory(sa1.iram, root["iram"], ID::SA1IRAM, true);
for(auto &node : root["iram"]) {
if(node.name != "map") continue;
Mapping m({&SA1::mmc_read, &sa1}, {&SA1::mmc_write, &sa1});
parse_markup_map(m, node);
mapping.append(m);
}
parse_markup_memory(sa1.bwram, bwram, ID::SA1BWRAM, true);
for(auto &node : bwram) {
parse_markup_memory(sa1.bwram, root["bwram"], ID::SA1BWRAM, true);
for(auto &node : root["bwram"]) {
if(node.name != "map") continue;
Mapping m({&SA1::mmc_read, &sa1}, {&SA1::mmc_write, &sa1});
parse_markup_map(m, node);
mapping.append(m);
}
for(auto &node : mmio) {
for(auto &node : root["mmio"]) {
if(node.name != "map") continue;
Mapping m({&SA1::mmio_read, &sa1}, {&SA1::mmio_write, &sa1});
parse_markup_map(m, node);
@ -249,36 +250,28 @@ void Cartridge::parse_markup_superfx(XML::Node &root) {
if(root.exists() == false) return;
has_superfx = true;
for(auto &node : root) {
if(node.name == "rom") {
parse_markup_memory(rom, node, ID::ROM, false);
parse_markup_memory(superfx.rom, root["rom"], ID::SuperFXROM, false);
for(auto &node : root["rom"]) {
if(node.name != "map") continue;
Mapping m(superfx.cpurom);
parse_markup_map(m, node);
mapping.append(m);
}
for(auto &leaf : node) {
if(leaf.name != "map") continue;
Mapping m(superfx.rom);
parse_markup_map(m, leaf);
mapping.append(m);
}
}
if(node.name == "ram") {
parse_markup_memory(ram, node, ID::RAM, false);
parse_markup_memory(superfx.ram, root["ram"], ID::SuperFXRAM, true);
for(auto &node : root["ram"]) {
if(node.name != "map") continue;
Mapping m(superfx.cpuram);
parse_markup_map(m, node);
if(m.size == 0) m.size = superfx.ram.size();
mapping.append(m);
}
for(auto &leaf : node) {
if(leaf.name != "map") continue;
Mapping m(superfx.ram);
parse_markup_map(m, leaf);
if(m.size == 0) m.size = ram.size();
mapping.append(m);
}
}
if(node.name == "mmio") {
for(auto &leaf : node) {
if(leaf.name != "map") continue;
Mapping m({&SuperFX::mmio_read, &superfx}, {&SuperFX::mmio_write, &superfx});
parse_markup_map(m, leaf);
mapping.append(m);
}
}
for(auto &node : root["mmio"]) {
if(node.name != "map") continue;
Mapping m({&SuperFX::mmio_read, &superfx}, {&SuperFX::mmio_write, &superfx});
parse_markup_map(m, node);
mapping.append(m);
}
}
@ -312,22 +305,18 @@ void Cartridge::parse_markup_hitachidsp(XML::Node &root) {
interface->loadRequest(ID::HitachiDSP, firmware);
for(auto &node : root) {
if(node.name == "rom") {
for(auto &leaf : node) {
if(leaf.name != "map") continue;
Mapping m({&HitachiDSP::rom_read, &hitachidsp}, {&HitachiDSP::rom_write, &hitachidsp});
parse_markup_map(m, leaf);
mapping.append(m);
}
}
if(node.name == "mmio") {
for(auto &leaf : node) {
Mapping m({&HitachiDSP::dsp_read, &hitachidsp}, {&HitachiDSP::dsp_write, &hitachidsp});
parse_markup_map(m, leaf);
mapping.append(m);
}
}
parse_markup_memory(hitachidsp.rom, root["rom"], ID::HitachiDSPROM, false);
for(auto &node : root["rom"]) {
if(node.name != "map") continue;
Mapping m({&HitachiDSP::rom_read, &hitachidsp}, {&HitachiDSP::rom_write, &hitachidsp});
parse_markup_map(m, node);
mapping.append(m);
}
for(auto &node : root["mmio"]) {
Mapping m({&HitachiDSP::dsp_read, &hitachidsp}, {&HitachiDSP::dsp_write, &hitachidsp});
parse_markup_map(m, node);
mapping.append(m);
}
}
@ -358,28 +347,25 @@ void Cartridge::parse_markup_necdsp(XML::Node &root) {
memory.append({ID::NecDSPRAM, name});
}
for(auto &node : root) {
if(node.name == "dr") {
for(auto &leaf : node) {
Mapping m({&NECDSP::dr_read, &necdsp}, {&NECDSP::dr_write, &necdsp});
parse_markup_map(m, leaf);
mapping.append(m);
}
}
if(node.name == "sr") {
for(auto &leaf : node) {
Mapping m({&NECDSP::sr_read, &necdsp}, {&NECDSP::sr_write, &necdsp});
parse_markup_map(m, leaf);
mapping.append(m);
}
}
if(node.name == "dp") {
for(auto &leaf : node) {
Mapping m({&NECDSP::dp_read, &necdsp}, {&NECDSP::dp_write, &necdsp});
parse_markup_map(m, leaf);
mapping.append(m);
}
}
for(auto &node : root["ram"]) {
if(node.name != "map") continue;
Mapping m({&NECDSP::dp_read, &necdsp}, {&NECDSP::dp_write, &necdsp});
parse_markup_map(m, node);
mapping.append(m);
}
for(auto &node : root["dr"]) {
if(node.name != "map") continue;
Mapping m({&NECDSP::dr_read, &necdsp}, {&NECDSP::dr_write, &necdsp});
parse_markup_map(m, node);
mapping.append(m);
}
for(auto &node : root["sr"]) {
if(node.name != "map") continue;
Mapping m({&NECDSP::sr_read, &necdsp}, {&NECDSP::sr_write, &necdsp});
parse_markup_map(m, node);
mapping.append(m);
}
}
@ -419,41 +405,31 @@ void Cartridge::parse_markup_spc7110(XML::Node &root) {
if(root.exists() == false) return;
has_spc7110 = true;
auto &rom = root["rom"];
auto &ram = root["ram"];
auto &mmio = root["mmio"];
auto &dcu = root["dcu"];
spc7110.prom_base = numeral(rom["program"]["offset"].data);
spc7110.prom_size = numeral(rom["program"]["size"].data);
spc7110.drom_base = numeral(rom["data"]["offset"].data);
spc7110.drom_size = numeral(rom["data"]["size"].data);
parse_markup_memory(cartridge.rom, rom, ID::ROM, false);
for(auto &node : rom) {
parse_markup_memory(spc7110.prom, root["rom"]["program"], ID::SPC7110PROM, false);
parse_markup_memory(spc7110.drom, root["rom"]["data"], ID::SPC7110DROM, false);
for(auto &node : root["rom"]) {
if(node.name != "map") continue;
Mapping m({&SPC7110::mcurom_read, &spc7110}, {&SPC7110::mcurom_write, &spc7110});
parse_markup_map(m, node);
mapping.append(m);
}
parse_markup_memory(cartridge.ram, ram, ID::RAM, true);
for(auto &node : ram) {
parse_markup_memory(spc7110.ram, root["ram"], ID::SPC7110RAM, true);
for(auto &node : root["ram"]) {
if(node.name != "map") continue;
Mapping m({&SPC7110::mcuram_read, &spc7110}, {&SPC7110::mcuram_write, &spc7110});
parse_markup_map(m, node);
mapping.append(m);
}
for(auto &node : mmio) {
for(auto &node : root["mmio"]) {
if(node.name != "map") continue;
Mapping m({&SPC7110::mmio_read, &spc7110}, {&SPC7110::mmio_write, &spc7110});
parse_markup_map(m, node);
mapping.append(m);
}
for(auto &node : dcu) {
for(auto &node : root["dcu"]) {
if(node.name != "map") continue;
Mapping m({&SPC7110::dcu_read, &spc7110}, {&SPC7110::dcu_write, &spc7110});
parse_markup_map(m, node);
@ -493,7 +469,8 @@ void Cartridge::parse_markup_obc1(XML::Node &root) {
if(root.exists() == false) return;
has_obc1 = true;
for(auto &node : root) {
parse_markup_memory(obc1.ram, root["ram"], ID::OBC1RAM, true);
for(auto &node : root["ram"]) {
if(node.name != "map") continue;
Mapping m({&OBC1::read, &obc1}, {&OBC1::write, &obc1});
parse_markup_map(m, node);

11
bsnes/sfc/chip/bsx/cartridge/cartridge.cpp
View File

@ -10,6 +10,9 @@ void BSXCartridge::load() {
}
void BSXCartridge::unload() {
rom.reset();
ram.reset();
psram.reset();
}
void BSXCartridge::power() {
@ -42,14 +45,14 @@ uint8 BSXCartridge::mcu_access(bool write, unsigned addr, uint8 data) {
if((addr & 0xe08000) == 0x008000) { //$00-1f:8000-ffff
if(r07 == 1) {
addr = ((addr & 0x1f0000) >> 1) | (addr & 0x7fff);
return memory_access(write, cartridge.rom, addr, data);
return memory_access(write, rom, addr, data);
}
}
if((addr & 0xe08000) == 0x808000) { //$80-9f:8000-ffff
if(r08 == 1) {
addr = ((addr & 0x1f0000) >> 1) | (addr & 0x7fff);
return memory_access(write, cartridge.rom, addr, data);
return memory_access(write, rom, addr, data);
}
}
@ -99,7 +102,7 @@ uint8 BSXCartridge::mmio_read(unsigned addr) {
}
if((addr & 0xf8f000) == 0x105000) { //$10-17:5000-5fff
return memory_read(cartridge.ram, ((addr >> 16) & 7) * 0x1000 + (addr & 0xfff));
return memory_read(ram, ((addr >> 16) & 7) * 0x1000 + (addr & 0xfff));
}
return 0x00;
@ -114,7 +117,7 @@ void BSXCartridge::mmio_write(unsigned addr, uint8 data) {
}
if((addr & 0xf8f000) == 0x105000) { //$10-17:5000-5fff
return memory_write(cartridge.ram, ((addr >> 16) & 7) * 0x1000 + (addr & 0xfff), data);
return memory_write(ram, ((addr >> 16) & 7) * 0x1000 + (addr & 0xfff), data);
}
}

2
bsnes/sfc/chip/bsx/cartridge/cartridge.hpp
View File

@ -1,4 +1,6 @@
struct BSXCartridge {
MappedRAM rom;
MappedRAM ram;
MappedRAM psram;
void init();

1
bsnes/sfc/chip/bsx/cartridge/serialization.cpp
View File

@ -1,3 +1,4 @@
void BSXCartridge::serialize(serializer &s) {
s.array(ram.data(), ram.size());
s.array(psram.data(), psram.size());
}

4
bsnes/sfc/chip/bsx/satellaview/satellaview.cpp
View File

@ -6,8 +6,8 @@ void BSXSatellaview::init() {
}
void BSXSatellaview::load() {
bus.map(Bus::MapMode::Direct, 0x00, 0x3f, 0x2188, 0x219f, { &BSXSatellaview::mmio_read, &bsxsatellaview }, { &BSXSatellaview::mmio_write, &bsxsatellaview });
bus.map(Bus::MapMode::Direct, 0x80, 0xbf, 0x2188, 0x219f, { &BSXSatellaview::mmio_read, &bsxsatellaview }, { &BSXSatellaview::mmio_write, &bsxsatellaview });
bus.map(Bus::MapMode::Direct, 0x00, 0x3f, 0x2188, 0x219f, {&BSXSatellaview::mmio_read, &bsxsatellaview}, {&BSXSatellaview::mmio_write, &bsxsatellaview});
bus.map(Bus::MapMode::Direct, 0x80, 0xbf, 0x2188, 0x219f, {&BSXSatellaview::mmio_read, &bsxsatellaview}, {&BSXSatellaview::mmio_write, &bsxsatellaview});
}
void BSXSatellaview::unload() {

1
bsnes/sfc/chip/hitachidsp/hitachidsp.cpp
View File

@ -37,6 +37,7 @@ void HitachiDSP::load() {
}
void HitachiDSP::unload() {
rom.reset();
}
void HitachiDSP::power() {

2
bsnes/sfc/chip/hitachidsp/hitachidsp.hpp
View File

@ -1,4 +1,6 @@
struct HitachiDSP : Processor::HG51B, Coprocessor {
MappedRAM rom;
unsigned frequency;
#include "mmio.hpp"

4
bsnes/sfc/chip/hitachidsp/memory.cpp
View File

@ -11,12 +11,12 @@ void HitachiDSP::bus_write(uint24 addr, uint8 data) {
uint8 HitachiDSP::rom_read(unsigned addr) {
if(co_active() == cpu.thread) {
if(regs.halt) return cartridge.rom.read(addr);
if(regs.halt) return rom.read(addr);
if((addr & 0x40ffe0) == 0x00ffe0) return mmio.vector[addr & 0x1f];
return cpu.regs.mdr;
}
if(co_active() == hitachidsp.thread) {
return cartridge.rom.read(addr);
return rom.read(addr);
}
return cpu.regs.mdr;
}

5
bsnes/sfc/chip/obc1/obc1.cpp
View File

@ -13,6 +13,7 @@ void OBC1::load() {
}
void OBC1::unload() {
ram.reset();
}
void OBC1::power() {
@ -69,11 +70,11 @@ void OBC1::write(unsigned addr, uint8 data) {
}
uint8 OBC1::ram_read(unsigned addr) {
return cartridge.ram.read(addr & 0x1fff);
return ram.read(addr & 0x1fff);
}
void OBC1::ram_write(unsigned addr, uint8 data) {
cartridge.ram.write(addr & 0x1fff, data);
ram.write(addr & 0x1fff, data);
}
}

2
bsnes/sfc/chip/obc1/obc1.hpp
View File

@ -1,4 +1,6 @@
struct OBC1 {
MappedRAM ram;
void init();
void load();
void unload();

2
bsnes/sfc/chip/obc1/serialization.cpp
View File

@ -1,6 +1,8 @@
#ifdef OBC1_CPP
void OBC1::serialize(serializer &s) {
s.array(ram.data(), ram.size());
s.integer(status.address);
s.integer(status.baseptr);
s.integer(status.shift);

2
bsnes/sfc/chip/spc7110/data.cpp
View File

@ -5,7 +5,7 @@ uint8 SPC7110::datarom_read(unsigned addr) {
unsigned mask = 0x100000 * size - 1;
unsigned offset = addr & mask;
if((r4834 & 3) != 3 && (addr & 0x400000)) return 0x00;
return cartridge.rom.read(drom_base + Bus::mirror(offset, drom_size));
return drom.read(Bus::mirror(offset, drom.size()));
}
unsigned SPC7110::data_offset() { return r4811 | r4812 << 8 | r4813 << 16; }

2
bsnes/sfc/chip/spc7110/serialization.cpp
View File

@ -1,6 +1,8 @@
#ifdef SPC7110_CPP
void SPC7110::serialize(serializer &s) {
s.array(ram.data(), ram.size());
s.integer(r4801);
s.integer(r4802);
s.integer(r4803);

17
bsnes/sfc/chip/spc7110/spc7110.cpp
View File

@ -45,6 +45,9 @@ void SPC7110::load() {
}
void SPC7110::unload() {
prom.reset();
drom.reset();
ram.reset();
}
void SPC7110::power() {
@ -279,8 +282,8 @@ uint8 SPC7110::mcurom_read(unsigned addr) {
|| (addr & 0xf00000) == 0xc00000 // $c0-cf:0000-ffff
) {
addr &= 0x0fffff;
if(prom_size) { //8mbit PROM
return cartridge.rom.read(prom_base + bus.mirror(0x000000 + addr, prom_size));
if(prom.size()) { //8mbit PROM
return prom.read(bus.mirror(0x000000 + addr, prom.size()));
}
addr |= 0x100000 * (r4830 & 7);
return datarom_read(addr);
@ -291,7 +294,7 @@ uint8 SPC7110::mcurom_read(unsigned addr) {
) {
addr &= 0x0fffff;
if(r4834 & 4) { //16mbit PROM
return cartridge.rom.read(prom_base + bus.mirror(0x100000 + addr, prom_size));
return prom.read(bus.mirror(0x100000 + addr, prom.size()));
}
addr |= 0x100000 * (r4831 & 7);
return datarom_read(addr);
@ -327,8 +330,8 @@ uint8 SPC7110::mcuram_read(unsigned addr) {
//$00-3f|80-bf:6000-7fff
if(r4830 & 0x80) {
unsigned bank = (addr >> 16) & 0x3f;
addr = bus.mirror(bank * 0x2000 + (addr & 0x1fff), cartridge.ram.size());
return cartridge.ram.read(addr);
addr = bus.mirror(bank * 0x2000 + (addr & 0x1fff), ram.size());
return ram.read(addr);
}
return 0x00;
}
@ -337,8 +340,8 @@ void SPC7110::mcuram_write(unsigned addr, uint8 data) {
//$00-3f|80-bf:6000-7fff
if(r4830 & 0x80) {
unsigned bank = (addr >> 16) & 0x3f;
addr = bus.mirror(bank * 0x2000 + (addr & 0x1fff), cartridge.ram.size());
cartridge.ram.write(addr, data);
addr = bus.mirror(bank * 0x2000 + (addr & 0x1fff), ram.size());
ram.write(addr, data);
}
}

5
bsnes/sfc/chip/spc7110/spc7110.hpp
View File

@ -1,8 +1,9 @@
struct Decompressor;
struct SPC7110 : Coprocessor {
unsigned prom_base, prom_size; //program ROM
unsigned drom_base, drom_size; //data ROM
MappedRAM prom; //program ROM
MappedRAM drom; //data ROM
MappedRAM ram;
static void Enter();
void enter();

24
bsnes/sfc/chip/superfx/bus/bus.cpp
View File

@ -2,11 +2,11 @@
//ROM / RAM access from the S-CPU
unsigned SuperFX::ROM::size() const {
return cartridge.rom.size();
unsigned SuperFX::CPUROM::size() const {
return superfx.rom.size();
}
uint8 SuperFX::ROM::read(unsigned addr) {
uint8 SuperFX::CPUROM::read(unsigned addr) {
if(superfx.regs.sfr.g && superfx.regs.scmr.ron) {
static const uint8_t data[16] = {
0x00, 0x01, 0x00, 0x01, 0x04, 0x01, 0x00, 0x01,
@ -14,24 +14,24 @@ uint8 SuperFX::ROM::read(unsigned addr) {
};
return data[addr & 15];
}
return cartridge.rom.read(addr);
return superfx.rom.read(addr);
}
void SuperFX::ROM::write(unsigned addr, uint8 data) {
cartridge.rom.write(addr, data);
void SuperFX::CPUROM::write(unsigned addr, uint8 data) {
superfx.rom.write(addr, data);
}
unsigned SuperFX::RAM::size() const {
return cartridge.ram.size();
unsigned SuperFX::CPURAM::size() const {
return superfx.ram.size();
}
uint8 SuperFX::RAM::read(unsigned addr) {
uint8 SuperFX::CPURAM::read(unsigned addr) {
if(superfx.regs.sfr.g && superfx.regs.scmr.ran) return cpu.regs.mdr;
return cartridge.ram.read(addr);
return superfx.ram.read(addr);
}
void SuperFX::RAM::write(unsigned addr, uint8 data) {
cartridge.ram.write(addr, data);
void SuperFX::CPURAM::write(unsigned addr, uint8 data) {
superfx.ram.write(addr, data);
}
#endif

8
bsnes/sfc/chip/superfx/bus/bus.hpp
View File

@ -1,11 +1,11 @@
struct ROM : Memory {
struct CPUROM : Memory {
unsigned size() const;
uint8 read(unsigned);
void write(unsigned, uint8);
} rom;
} cpurom;
struct RAM : Memory {
struct CPURAM : Memory {
unsigned size() const;
uint8 read(unsigned);
void write(unsigned, uint8);
} ram;
} cpuram;

12
bsnes/sfc/chip/superfx/memory/memory.cpp
View File

@ -6,7 +6,7 @@ uint8 SuperFX::bus_read(unsigned addr) {
step(6);
synchronize_cpu();
}
return cartridge.rom.read((((addr & 0x3f0000) >> 1) | (addr & 0x7fff)) & rom_mask);
return rom.read((((addr & 0x3f0000) >> 1) | (addr & 0x7fff)) & rom_mask);
}
if((addr & 0xe00000) == 0x400000) { //$40-5f:0000-ffff
@ -14,7 +14,7 @@ uint8 SuperFX::bus_read(unsigned addr) {
step(6);
synchronize_cpu();
}
return cartridge.rom.read(addr & rom_mask);
return rom.read(addr & rom_mask);
}
if((addr & 0xe00000) == 0x600000) { //$60-7f:0000-ffff
@ -22,7 +22,7 @@ uint8 SuperFX::bus_read(unsigned addr) {
step(6);
synchronize_cpu();
}
return cartridge.ram.read(addr & ram_mask);
return ram.read(addr & ram_mask);
}
}
@ -32,7 +32,7 @@ void SuperFX::bus_write(unsigned addr, uint8 data) {
step(6);
synchronize_cpu();
}
return cartridge.ram.write(addr & ram_mask, data);
return ram.write(addr & ram_mask, data);
}
}
@ -96,8 +96,8 @@ void SuperFX::cache_mmio_write(uint16 addr, uint8 data) {
}
void SuperFX::memory_reset() {
rom_mask = cartridge.rom.size() - 1;
ram_mask = cartridge.ram.size() - 1;
rom_mask = rom.size() - 1;
ram_mask = ram.size() - 1;
for(unsigned n = 0; n < 512; n++) cache.buffer[n] = 0x00;
for(unsigned n = 0; n < 32; n++) cache.valid[n] = false;

2
bsnes/sfc/chip/superfx/serialization.cpp
View File

@ -4,6 +4,8 @@ void SuperFX::serialize(serializer &s) {
GSU::serialize(s);
Thread::serialize(s);
s.array(ram.data(), ram.size());
s.integer(clockmode);
s.integer(instruction_counter);

2
bsnes/sfc/chip/superfx/superfx.cpp
View File

@ -47,6 +47,8 @@ void SuperFX::load() {
}
void SuperFX::unload() {
rom.reset();
ram.reset();
}
void SuperFX::power() {

3
bsnes/sfc/chip/superfx/superfx.hpp
View File

@ -1,4 +1,7 @@
struct SuperFX : Processor::GSU, Coprocessor {
MappedRAM rom;
MappedRAM ram;
#include "bus/bus.hpp"
#include "core/core.hpp"
#include "memory/memory.hpp"

62
bsnes/sfc/interface/interface.cpp
View File

@ -30,15 +30,24 @@ unsigned Interface::group(unsigned id) {
case ID::SA1ROM:
case ID::SA1IRAM:
case ID::SA1BWRAM:
case ID::SuperFXROM:
case ID::SuperFXRAM:
case ID::ArmDSP:
case ID::HitachiDSP:
case ID::HitachiDSPROM:
case ID::Nec7725DSP:
case ID::Nec96050DSP:
case ID::NecDSPRAM:
case ID::EpsonRTC:
case ID::SharpRTC:
case ID::SPC7110PROM:
case ID::SPC7110DROM:
case ID::SPC7110RAM:
case ID::SDD1ROM:
case ID::SDD1RAM:
case ID::OBC1RAM:
case ID::BsxROM:
case ID::BsxRAM:
case ID::BsxPSRAM:
return 0;
case ID::SuperGameBoy:
@ -86,6 +95,9 @@ void Interface::load(unsigned id, const stream &stream, const string &manifest)
if(id == ID::SA1IRAM) sa1.iram.read(stream);
if(id == ID::SA1BWRAM) sa1.bwram.read(stream);
if(id == ID::SuperFXROM) superfx.rom.read(stream);
if(id == ID::SuperFXRAM) superfx.ram.read(stream);
if(id == ID::ArmDSP) {
stream.read(armdsp.firmware, stream.size());
}
@ -94,6 +106,8 @@ void Interface::load(unsigned id, const stream &stream, const string &manifest)
for(unsigned n = 0; n < 1024; n++) hitachidsp.dataROM[n] = stream.readl(3);
}
if(id == ID::HitachiDSPROM) hitachidsp.rom.read(stream);
if(id == ID::Nec7725DSP) {
for(unsigned n = 0; n < 2048; n++) necdsp.programROM[n] = stream.readl(3);
for(unsigned n = 0; n < 1024; n++) necdsp.dataROM[n] = stream.readl(2);
@ -120,9 +134,15 @@ void Interface::load(unsigned id, const stream &stream, const string &manifest)
sharprtc.load(data);
}
if(id == ID::SPC7110PROM) spc7110.prom.read(stream);
if(id == ID::SPC7110DROM) spc7110.drom.read(stream);
if(id == ID::SPC7110RAM) spc7110.ram.read(stream);
if(id == ID::SDD1ROM) sdd1.rom.read(stream);
if(id == ID::SDD1RAM) sdd1.ram.read(stream);
if(id == ID::OBC1RAM) obc1.ram.read(stream);
if(id == ID::SuperGameBoyROM) {
stream.read(GameBoy::cartridge.romdata, min(GameBoy::cartridge.romsize, stream.size()));
}
@ -131,30 +151,23 @@ void Interface::load(unsigned id, const stream &stream, const string &manifest)
stream.read(GameBoy::cartridge.ramdata, min(GameBoy::cartridge.ramsize, stream.size()));
}
if(id == ID::BsxFlashROM) {
bsxflash.memory.read(stream);
}
if(id == ID::BsxPSRAM) {
stream.read(bsxcartridge.psram.data(), min(stream.size(), bsxcartridge.psram.size()));
}
if(id == ID::BsxFlashROM) bsxflash.memory.read(stream);
if(id == ID::BsxROM) bsxcartridge.rom.read(stream);
if(id == ID::BsxRAM) bsxcartridge.ram.read(stream);
if(id == ID::BsxPSRAM) bsxcartridge.psram.read(stream);
if(id == ID::SufamiTurboSlotAROM) sufamiturbo.slotA.rom.read(stream);
if(id == ID::SufamiTurboSlotBROM) sufamiturbo.slotB.rom.read(stream);
if(id == ID::SufamiTurboSlotARAM) {
stream.read(sufamiturbo.slotA.ram.data(), min(sufamiturbo.slotA.ram.size(), stream.size()));
}
if(id == ID::SufamiTurboSlotBRAM) {
stream.read(sufamiturbo.slotB.ram.data(), min(sufamiturbo.slotB.ram.size(), stream.size()));
}
if(id == ID::SufamiTurboSlotARAM) sufamiturbo.slotA.ram.read(stream);
if(id == ID::SufamiTurboSlotBRAM) sufamiturbo.slotB.ram.read(stream);
}
void Interface::save(unsigned id, const stream &stream) {
if(id == ID::RAM) stream.write(cartridge.ram.data(), cartridge.ram.size());
if(id == ID::SA1IRAM) stream.write(sa1.iram.data(), sa1.iram.size());
if(id == ID::SA1BWRAM) stream.write(sa1.bwram.data(), sa1.bwram.size());
if(id == ID::SuperFXRAM) stream.write(superfx.ram.data(), superfx.ram.size());
if(id == ID::NecDSPRAM) {
for(unsigned n = 0; n < 2048; n++) stream.writel(necdsp.dataRAM[n], 2);
@ -172,24 +185,17 @@ void Interface::save(unsigned id, const stream &stream) {
stream.write(data, sizeof data);
}
if(id == ID::SPC7110RAM) stream.write(spc7110.ram.data(), spc7110.ram.size());
if(id == ID::SDD1RAM) stream.write(sdd1.ram.data(), sdd1.ram.size());
if(id == ID::OBC1RAM) stream.write(obc1.ram.data(), obc1.ram.size());
if(id == ID::SuperGameBoyRAM) {
stream.write(GameBoy::cartridge.ramdata, GameBoy::cartridge.ramsize);
}
if(id == ID::SuperGameBoyRAM) stream.write(GameBoy::cartridge.ramdata, GameBoy::cartridge.ramsize);
if(id == ID::BsxPSRAM) {
stream.write(bsxcartridge.psram.data(), bsxcartridge.psram.size());
}
if(id == ID::BsxRAM) stream.write(bsxcartridge.ram.data(), bsxcartridge.ram.size());
if(id == ID::BsxPSRAM) stream.write(bsxcartridge.psram.data(), bsxcartridge.psram.size());
if(id == ID::SufamiTurboSlotARAM) {
stream.write(sufamiturbo.slotA.ram.data(), sufamiturbo.slotA.ram.size());
}
if(id == ID::SufamiTurboSlotBRAM) {
stream.write(sufamiturbo.slotB.ram.data(), sufamiturbo.slotB.ram.size());
}
if(id == ID::SufamiTurboSlotARAM) stream.write(sufamiturbo.slotA.ram.data(), sufamiturbo.slotA.ram.size());
if(id == ID::SufamiTurboSlotBRAM) stream.write(sufamiturbo.slotB.ram.data(), sufamiturbo.slotB.ram.size());
}
void Interface::unload() {

12
bsnes/sfc/interface/interface.hpp
View File

@ -21,8 +21,12 @@ struct ID {
SA1IRAM,
SA1BWRAM,
SuperFXROM,
SuperFXRAM,
ArmDSP,
HitachiDSP,
HitachiDSPROM,
Nec7725DSP,
Nec96050DSP,
NecDSPRAM,
@ -30,13 +34,21 @@ struct ID {
EpsonRTC,
SharpRTC,
SPC7110PROM,
SPC7110DROM,
SPC7110RAM,
SDD1ROM,
SDD1RAM,
OBC1RAM,
SuperGameBoyROM,
SuperGameBoyRAM,
BsxFlashROM,
BsxROM,
BsxRAM,
BsxPSRAM,
SufamiTurboSlotAROM,