alyosha-tas
|
76df4758db
|
A2600: update ball emulation
A7800: update m6532 to match 2600
|
2019-08-03 19:17:28 -04:00 |
|
alyosha-tas
|
f058933342
|
Vectrex: Fix firmware
|
2019-08-03 09:26:30 -04:00 |
|
alyosha-tas
|
6948b999f1
|
A2600: Fix ram buffer
|
2019-08-01 08:51:32 -04:00 |
|
alyosha-tas
|
dce8db231b
|
GBHawk: color regs writable
|
2019-07-29 14:09:51 -04:00 |
|
Tony Konzel
|
58513ea22f
|
Merge pull request #1607 from TASVideos/c64-refactor
C64: General improvements (disk writing, CIA/VIA timers, 6502X decimal mode fixes)
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2019-07-22 09:29:22 -05:00 |
|
alyosha-tas
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fca98ffe34
|
Various code cleanup
|
2019-07-21 09:05:07 -04:00 |
|
alyosha-tas
|
6a773ac272
|
Atari 2600: more bug fixes
|
2019-07-20 14:47:36 -04:00 |
|
SaxxonPike
|
1e5fe55f30
|
C64: Don't reallocate the SID filter buffer every time (purely perf)
|
2019-07-19 19:09:08 -05:00 |
|
alyosha-tas
|
cf6cdf4ecc
|
A2600: Bug fixes and Improvements
|
2019-07-19 20:03:30 -04:00 |
|
SaxxonPike
|
a119420c79
|
C64: VC count enable seems to need to be delayed by 1 cycle after badline
- which doesn't affect normal operation
- which DOES affect VSP
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2019-07-14 20:22:07 -05:00 |
|
SaxxonPike
|
4d6ed8d6c8
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C64: Savestate should include the new variables
|
2019-07-14 16:32:53 -05:00 |
|
SaxxonPike
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ad7cae8b71
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Merge branch 'master' into c64-refactor
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2019-07-14 10:45:44 -05:00 |
|
SaxxonPike
|
8e8d3a6a1b
|
C64: Writes to some registers on the VIC in phase 2 by the CPU should only take effect on the following cycle
|
2019-07-14 10:44:56 -05:00 |
|
SaxxonPike
|
e8902b829a
|
C64: Apparently the 6502X core needs interrupts delayed by a cycle, do that with IRQ and NMI
|
2019-07-14 10:43:52 -05:00 |
|
SaxxonPike
|
3bbfb98fc2
|
C64: Split out VIC IRQ delays
|
2019-07-13 19:28:44 -05:00 |
|
alyosha-tas
|
7df8ed1f27
|
A2600: Add HMCLR delay
|
2019-07-13 18:33:54 -04:00 |
|
SaxxonPike
|
154eefd2ad
|
C64: Give BA/IRQ counting another go, seems to resolve many issues
|
2019-07-13 16:51:30 -05:00 |
|
SaxxonPike
|
db38d5e65b
|
C64: Try counting IRQ and BA correctly
|
2019-07-13 15:28:57 -05:00 |
|
SaxxonPike
|
f22c9b7abd
|
C64: CPU reads open bus when !AEC is asserted
|
2019-07-13 15:25:40 -05:00 |
|
SaxxonPike
|
894adbb610
|
C64: Remove an unused variable
|
2019-07-13 15:02:18 -05:00 |
|
SaxxonPike
|
76679bc8bc
|
C64: Use the correct background color in bitmapped modes for 0
|
2019-07-13 15:01:11 -05:00 |
|
SaxxonPike
|
bd20b355f0
|
C64: Writing to CPU port writes open bus data to 00/01
|
2019-07-13 14:06:23 -05:00 |
|
SaxxonPike
|
f18e7c8833
|
C64: Make the system debuggable for once
|
2019-07-13 13:15:50 -05:00 |
|
SaxxonPike
|
cae3340946
|
C64: No need to expose these with the CPU link in place
|
2019-07-13 12:53:34 -05:00 |
|
SaxxonPike
|
3369dbf43f
|
C64: IRQ is implemented as a delay line; no delay added (yet)
|
2019-07-13 12:51:39 -05:00 |
|
SaxxonPike
|
d39f3e2e61
|
6502X: pending IRQs are not delayed when !RDY is asserted
|
2019-07-13 12:31:09 -05:00 |
|
SaxxonPike
|
bf2cba0e23
|
6502X: remove a comment (this is indeed a dummy fetch)
|
2019-07-13 11:38:03 -05:00 |
|
SaxxonPike
|
d62f2ac3fe
|
C64: 0F7 is a badline eligible raster (fixes 26-line text demo in Frodo test suite)
|
2019-07-13 01:41:58 -05:00 |
|
SaxxonPike
|
e6871b2cc3
|
C64: Move VIC raster IRQ to phase 1
|
2019-07-13 00:27:08 -05:00 |
|
SaxxonPike
|
dbf6b39e7f
|
C64: Split out VIC phase1/phase2
|
2019-07-12 23:51:55 -05:00 |
|
SaxxonPike
|
85bc92b688
|
Merge remote-tracking branch 'origin/c64-refactor' into c64-refactor
# Conflicts:
# BizHawk.Emulation.Cores/Computers/Commodore64/MOS/Chip6510.cs
|
2019-07-12 22:10:08 -05:00 |
|
alyosha-tas
|
66cf00a917
|
Vectrex: Add frame buffer to state an set to released
|
2019-07-12 18:15:25 -04:00 |
|
alyosha-tas
|
5e2b097902
|
MC6809: fix DAA
|
2019-07-10 19:30:17 -04:00 |
|
alyosha-tas
|
fd51934ea4
|
Vectrex: Fix some bugs
|
2019-07-10 15:42:01 -04:00 |
|
alyosha-tas
|
9fe277a3ff
|
Vectrex: a bit more controller and frame cleanup
|
2019-07-10 06:58:41 -04:00 |
|
SaxxonPike
|
0a7dc52aa0
|
C64: BA and raster IRQ cleanup
|
2019-07-09 22:41:12 -05:00 |
|
SaxxonPike
|
3a135c7c26
|
C64: Raster interrupt bit can be set even if not enabled, just won't actually assert IRQ
|
2019-07-09 21:40:03 -05:00 |
|
SaxxonPike
|
e63d10b608
|
C64: Interrupts generated in phase 2 by the VIC won't trigger for the CPU until next cycle, also buffer BA
|
2019-07-09 20:55:14 -05:00 |
|
SaxxonPike
|
b471fdc692
|
C64: The CPU can trigger VIC badlines on its own (needed for VSP)
|
2019-07-09 20:53:54 -05:00 |
|
SaxxonPike
|
2abe832289
|
C64: AEC does not prohibit the CPU from functioning, only BA (RDY) does
|
2019-07-09 20:52:51 -05:00 |
|
SaxxonPike
|
9758efe604
|
6502X: CPU does a read or write regardless if the result is trashed, even during reset and dummy pushes
|
2019-07-09 19:46:33 -05:00 |
|
alyosha-tas
|
84b0917f65
|
Vectrex: Add schema and do some miscellanous clean up
|
2019-07-09 20:01:45 -04:00 |
|
SaxxonPike
|
a8fd85157c
|
VIC: Use correct color mapping for non-multicolor bitmap mode
|
2019-07-09 08:02:55 -05:00 |
|
SaxxonPike
|
83b6553749
|
VIC: Respect idle state background color registers, plus black in undocumented gfx mode
|
2019-07-09 06:58:13 -05:00 |
|
SaxxonPike
|
89fa153477
|
VIC: Resolve background color registers separately to color matrix memory
|
2019-07-09 06:55:55 -05:00 |
|
SaxxonPike
|
9f733d3e7a
|
VIC: More accurate pixel pipeline
|
2019-07-09 05:26:26 -05:00 |
|
SaxxonPike
|
3efea15038
|
6502X: When !RDY is asserted, still do other operations. Plus, do dummy reads on stack ops
|
2019-07-09 05:24:47 -05:00 |
|
alyosha-tas
|
f544c044bf
|
NES MMC3: Mapper test indicates IRQ was happening one ppu tick too late.
|
2019-07-08 08:16:43 -04:00 |
|
alyosha-tas
|
5b2ed7e4ff
|
MC6800: disassembler and cleanup
|
2019-07-07 17:32:14 -04:00 |
|
alyosha-tas
|
53dd500875
|
MC6800: More cleanup
|
2019-07-07 09:08:26 -04:00 |