Commit Graph

8 Commits

Author SHA1 Message Date
brandman211 10274734f9 -My jumping seems to work, so I enabled it in Execute.
-Finished the disassembler except for branching.
-Merged the XXXI instructions with XXX@ for R7 as the address register as they are redundant.
2012-07-19 06:58:14 +00:00
brandman211 e73c48219a -Loaded EROM / GROM.
-Fixed disassembly for JMP:
--Now it uses the parameter pc, not RegisterPC.
--I was loading both the second and third value from the second's address.
--Casting the calculated addresses to bytes when addresses are 16-bit was a bad idea.
--Removed a closing parenthesis I accidentally stuck in the formatting.

It seems that I've gotten far enough to use the Executive ROM as a test case! Now to go instruction by instruction and see if they work as planned and hope this will all eventually make something.
2012-07-19 00:05:08 +00:00
brandman211 32baa013af -Made the memory map use ushort arrays because the Intellivision is 16-bit.
-Fixed JMP disassembly; I need to return on an invalid opcode because I was breaking out of the inner switch statement, not both that and the outer one.
2012-07-09 23:19:57 +00:00
brandman211 9b8a9d93f1 Opcodes up to 0x07F. 2012-07-09 03:27:27 +00:00
brandman211 bb532aa2d9 Opcodes up to 0x5F. 2012-07-08 21:49:09 +00:00
brandman211 61cada6190 -Made HLT throw an exception.
-Made all instructions in the executor, even implemented ones, throw exceptions. I will get rid of the exceptions as I test the instructions.
-Added instructions up to and including 0x57 to disassembly and executor.
2012-07-08 19:52:12 +00:00
brandman211 a4912e66c0 -Wasn't supposed to actually increment the PC in the disassembler.
-Cleaned up the 0x004 (Jump) disassembler.
-Implemented 0x004 in the executor.
2012-07-08 08:42:32 +00:00
brandman211 778274a12d -Set up the disassembly decoder just like the executor.
-Disassembled opcodes up to and including 0x7.
2012-07-08 08:17:07 +00:00