2013-11-04 00:36:15 +00:00
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using BizHawk.Common;
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2014-07-03 17:23:03 +00:00
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using BizHawk.Common.NumberExtensions;
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2013-11-04 00:36:15 +00:00
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2013-11-14 13:15:41 +00:00
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namespace BizHawk.Emulation.Cores.Nintendo.NES
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2011-04-18 23:55:47 +00:00
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{
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2011-06-13 08:38:10 +00:00
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//AKA half of mapper 034 (the other half is BxROM which is entirely different..)
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2013-08-25 01:08:17 +00:00
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public sealed class AVE_NINA_001 : NES.NESBoardBase
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2011-06-13 08:38:10 +00:00
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{
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//configuration
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int prg_bank_mask_32k, chr_bank_mask_4k;
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//state
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IntBuffer chr_banks_4k = new IntBuffer(2);
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int prg_bank_32k;
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public override void Dispose()
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{
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base.Dispose();
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chr_banks_4k.Dispose();
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}
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public override void SyncState(Serializer ser)
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{
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base.SyncState(ser);
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ser.Sync("chr_banks_4k", ref chr_banks_4k);
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ser.Sync("prg_bank_32k", ref prg_bank_32k);
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}
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public override bool Configure(NES.EDetectionOrigin origin)
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{
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2011-04-18 23:55:47 +00:00
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switch (Cart.board_type)
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{
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2014-01-23 23:32:53 +00:00
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case "AVE-NINA-02": // untested
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2011-06-13 08:38:10 +00:00
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case "AVE-NINA-01": //Impossible Mission 2 (U)
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AssertPrg(64); AssertChr(64); AssertWram(8); AssertVram(0);
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2011-04-18 23:55:47 +00:00
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break;
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2011-06-13 08:38:10 +00:00
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2011-04-18 23:55:47 +00:00
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default:
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return false;
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}
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2011-06-13 08:38:10 +00:00
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prg_bank_mask_32k = Cart.prg_size / 32 - 1;
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chr_bank_mask_4k = Cart.chr_size / 4 - 1;
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SetMirrorType(Cart.pad_h, Cart.pad_v);
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return true;
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}
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public override byte ReadPPU(int addr)
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{
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if (addr < 0x2000)
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{
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int bank_4k = addr >> 12;
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int ofs = addr & ((1 << 12) - 1);
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bank_4k = chr_banks_4k[bank_4k];
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addr = (bank_4k << 12) | ofs;
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return VROM[addr];
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}
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else return base.ReadPPU(addr);
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}
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public override byte ReadPRG(int addr)
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{
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addr |= (prg_bank_32k << 15);
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2014-01-12 16:19:14 +00:00
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return ROM[addr];
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2011-06-13 08:38:10 +00:00
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}
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public override void WriteWRAM(int addr, byte value)
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{
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switch (addr)
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{
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case 0x1FFD: //$7FFD: Select 32k PRG @ $8000
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prg_bank_32k = value;
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prg_bank_32k &= prg_bank_mask_32k;
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break;
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case 0x1FFE:
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chr_banks_4k[0] = value;
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chr_banks_4k[0] &= chr_bank_mask_4k;
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break;
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case 0x1FFF:
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chr_banks_4k[1] = value;
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chr_banks_4k[1] &= chr_bank_mask_4k;
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break;
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default:
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//apparently these regs are patched in over the WRAM..
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2014-01-12 16:19:14 +00:00
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base.WriteWRAM(addr, value);
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2011-06-13 08:38:10 +00:00
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break;
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}
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}
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}
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2014-01-12 16:19:14 +00:00
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// according to the latest on nesdev:
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// mapper 079: [.... PCCC] @ 4100
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// mapper 113: [MCPP PCCC] @ 4100 (no games for this are in bootgod)
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2011-06-13 08:38:10 +00:00
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class AVE_NINA_006 : NES.NESBoardBase
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{
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//configuration
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int prg_bank_mask_32k, chr_bank_mask_8k;
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2014-01-12 16:19:14 +00:00
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bool mirror_control_enabled;
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2011-06-13 08:38:10 +00:00
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//state
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int chr_bank_8k, prg_bank_32k;
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2011-04-18 23:55:47 +00:00
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public override void SyncState(Serializer ser)
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2011-06-13 08:38:10 +00:00
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{
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2011-04-18 23:55:47 +00:00
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base.SyncState(ser);
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2011-06-13 08:38:10 +00:00
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ser.Sync("chr_bank_8k", ref chr_bank_8k);
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ser.Sync("prg_bank_32k", ref prg_bank_32k);
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}
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public override bool Configure(NES.EDetectionOrigin origin)
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{
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//configure
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switch (Cart.board_type)
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{
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2012-03-22 06:20:10 +00:00
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case "MAPPER079":
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2014-01-12 16:19:14 +00:00
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AssertPrg(32, 64); AssertChr(32, 64);
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2012-03-22 06:20:10 +00:00
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break;
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2014-01-23 23:08:56 +00:00
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case "TXC-74*138/175": // untested
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break;
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2012-03-22 06:20:10 +00:00
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case "MAPPER113":
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2014-01-12 16:19:14 +00:00
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mirror_control_enabled = true;
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2012-03-22 06:20:10 +00:00
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break;
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2011-06-13 08:38:10 +00:00
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case "AVE-NINA-06": //Blackjack (U)
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case "AVE-NINA-03": //F-15 City War (U)
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case "AVE-MB-91": //Deathbots (U)
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2014-01-15 23:27:02 +00:00
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if (Cart.chips.Count == 0) // some boards had no mapper chips on them
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return false;
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2011-06-13 08:38:10 +00:00
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AssertPrg(32, 64); AssertChr(32, 64); AssertWram(0); AssertVram(0);
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break;
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default:
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return false;
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}
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prg_bank_mask_32k = Cart.prg_size / 32 - 1;
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chr_bank_mask_8k = Cart.chr_size / 8 - 1;
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SetMirrorType(Cart.pad_h, Cart.pad_v);
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prg_bank_32k = 0;
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return true;
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}
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//FCEUX responds to this for PRG writes as well.. ?
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public override void WriteEXP(int addr, byte value)
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{
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addr &= 0x4100;
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switch (addr)
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{
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case 0x0100: //$4100: [.CPP PCCC]
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chr_bank_8k = (value & 7) | ((value >> 3) & 0x8);
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2011-09-25 00:21:19 +00:00
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chr_bank_8k &= chr_bank_mask_8k;
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prg_bank_32k = ((value >> 3) & 7);
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2011-06-13 08:38:10 +00:00
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prg_bank_32k &= prg_bank_mask_32k;
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2014-01-12 16:19:14 +00:00
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if (mirror_control_enabled)
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SetMirrorType(value.Bit(7) ? EMirrorType.Vertical : EMirrorType.Horizontal);
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2011-06-13 08:38:10 +00:00
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//NES.LogLine("chr={0:X2}, prg={1:X2}, with val={2:X2}", chr_reg, prg_reg, value);
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break;
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}
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}
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public override byte ReadPRG(int addr)
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{
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addr |= (prg_bank_32k << 15);
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return ROM[addr];
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}
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public override byte ReadPPU(int addr)
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{
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if (addr < 0x2000)
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{
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addr |= (chr_bank_8k << 13);
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return VROM[addr];
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}
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2014-01-12 16:19:14 +00:00
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else
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return base.ReadPPU(addr);
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2011-06-13 08:38:10 +00:00
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}
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}
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2011-04-18 23:55:47 +00:00
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}
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